hassan mostafa & m. anis & m. elmasry university of waterloo, ontario, canada
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Hassan Mostafa & M. Anis & M. Elmasry
University of Waterloo, Ontario, Canada
Statistical Timing Yield Improvement of Dynamic Circuits Using Negative
Capacitance Technique
ISCAS 2010 Slide 2
Outline
Introduction and Background
Motivation and Objectives
Negative Capacitance Circuits
Statistical Timing Yield Improvement Using Negative Capacitance
Results and Discussions
Conclusion
Introduction and Background
ISCAS 2010 Slide 3
Outline
Introduction and BackgroundVariabilityWide Fan-in Dynamic OR gate
Motivation and Objectives
Negative Capacitance Circuits
Statistical Timing Yield Improvement Using Negative Capacitance
Results and Discussions
Conclusion
Introduction and Background
ISCAS 2010 Slide 4
Variability Classification
Die-to-Die (D2D) Affects all devices on the chip in the same way
e.g., all devices on a chip have the same Vt
Within-Die (WID)Variations within a single chip
Affecting devices on the same chip differently
e.g., devices on the same chip have different Vt
Introduction and Background
Die index
D2D
WID
ISCAS 2010 Slide 5
Design Methodologies
Introduction and Background
Nominal
Corner-Based
Statistical
Design Methodology Performance Distribution Cost (e.g. power)
FAIL
FAIL
FAIL
50% Timing Yield
100% Timing Yield
>99.9% Timing Yield
www.nowpublishers.com
Frequency
(Overhead)
ISCAS 2010 Slide 6
T. C. Chen et al., ISSCC06
Process Variations SourcesRandom Dopant Fluctuations (RDF)
As CMOS devices are scaled, number of dopant atoms decreases
The number of dopant atoms has variations around its nominal value resulting in Vt variations
σVt α (WL)-0.5
As transistor area decreases with scaling, σVt increases
Channel Length VariationDifficulty to control the critical dimensions at sub-wavelength lithography
Large variations in the channel length (L)
Vt α exp(-L) due to short channel effects
A small variations in L results in large variations in Vt
Introduction and Background
Variations increase with technology scaling
1980 1990 2000 2020
100nm
1m
10nm
2010
193nm248nm
365nmLithographyWavelength
Generation
Gap
32nm
`
13nm EUV
Sub-wavelength lithography
65nm
90nm
130nm
45nm
180nm
[1]
S. Borkar et al., DAC04
ISCAS 2010 Slide 7
Variability and Yield
Delay
Delay distribution
Target delay
PASS FAIL
Process variations causes the device parameters to have fluctuations around their nominal values
The system parameters such as delay and power have a spread around their nominal values
This result in a percentage of the systems does not meet the required function or the required parameter constraint
Yield loss
Variability results in Yield loss
Introduction and Background
ISCAS 2010 Slide 8
Wide Fan-in Dynamic OR GateUsed in the processor critical path
Wide Fan-in (i.e., 16-input dynamic OR gate)
Wide Fan-in Dynamic OR gates are essential for high performance processor modules
Introduction and Background
ISCAS 2010 Slide 9
Wide Fan-in Dynamic OR Gate
Keeper transistor designSmall W/L
To avoid delay and power increase due to contention
Large W/LTo hold the floating output node at VDD against the increased leakage currents, especially, with technology scaling
With technology scaling, the increased leakage and variability result in larger delay and power
Introduction and Background
ISCAS 2010 Slide 10
Wide Fan-in Dynamic OR GateTiming yield improvement techniques
Keeper control circuitsDigitally controlled keeper sizing
Large leakage Large keeper W/L
Small Leakage Small keeper W/L
Body bias controlled keeper sizing
Large leakage Smaller keeper Vt
Small leakage Larger keeper Vt
These techniques utilize a leakage current sensor (analog)
Analog to digital converter
Digital control circuit
Previous timing yield improvement techniques exhibitlarge area overhead Negative capacitance to the rescue
Introduction and Background
ISCAS 2010 Slide 11
Outline
Introduction and BackgroundMotivation and Objectives
Negative Capacitance Circuits
Statistical Timing Yield Improvement Using Negative Capacitance
Results and Discussions
Conclusion
Motivation and Objectives
ISCAS 2010 Slide 12
Motivation and ObjectivesWide Fan-in dynamic OR gates are essential blocks in high performance processor modules
The increased variability and leakage result in timing yield loss
The existing timing yield improvement techniques exhibit large overhead (area and power)
Main idea:Delay α Output Capacitance
Dynamic Power α Output Capacitance
Motivation and Objectives
Reducing the output capacitance reduces the delay and the dynamic power
Negative capacitance breaks the power-performance trade-off
ISCAS 2010 Slide 13
Outline
Introduction and BackgroundMotivation and ObjectivesNegative Capacitance Circuits
Statistical Timing Yield Improvement Using Negative Capacitance
Results and Discussions
Conclusion
Negative Capacitance Circuits
ISCAS 2010 Slide 14
Negative Capacitance Circuits
1- Miller effect based circuit
Using A ≥ 1, A negative capacitance is realized
Differential Amplifier Buffer AmplifierNegative Capacitance Circuits
ISCAS 2010 Slide 15
Negative Capacitance Circuits
2- Negative Impedance Converter (NIC) based circuit
Current Conveyor
For Current conveyor NIC,
Negative Capacitance Circuits
ISCAS 2010 Slide 16
Negative Capacitance Circuits
The buffer amplifier based negative capacitance circuit:
A higher supply voltage is needed (VDDH)
High Vt transistors to reduce the static power consumption
VDDHVDDL
VDDL
VDDH
Negative Capacitance Circuits
ISCAS 2010 Slide 17
Outline
Introduction and BackgroundMotivation and ObjectivesNegative Capacitance CircuitsStatistical Timing Yield Improvement Using Negative Capacitance
Results and Discussions
Conclusion
Statistical Timing Yield Improvement
ISCAS 2010 Slide 18
Statistical Timing Yield Improvement Using Negative Capacitance
Timing yield improvement
n = 3 for YO = 99.87%
Statistical Timing Yield Improvement
ISCAS 2010 Slide 19
Outline
Introduction and BackgroundMotivation and ObjectivesNegative Capacitance CircuitsStatistical Timing Yield Improvement Using Negative CapacitanceResults and Discussions
Future Work
Conclusions
Results and Discussions
ISCAS 2010 Slide 20
Results and Discussions
16-input OR gate is used
The target delay (AO) = 102.4 psec and σ = 10.61 psec
The output capacitance Cout = 9.38 fF and the constant ʒ = 10.92 psec/fF.
The required negative capacitance CNEG = - 2.9 fF is realized by:
Using the buffer amplifier, A= 30 and CF = 0.1 fF
Using the differential amplifier, A= 3.9 and CF = 1 fF
Using the current conveyor, CL = 2.9 fF
Results and Discussions
ISCAS 2010 Slide 21
Results and DiscussionsTarget Delay
5000 Monte Carlo
Timing yield = 100%Mean delay reduction by 31%
OR gate power reduction by 10%
Delay standard deviation reduction by 58%
All the three proposed negative capacitance circuits provide similar results
Results and Discussions
ISCAS 2010 Slide 22
Results and Discussions
Why the delay standard deviation reduction is reduced?
∆AO = ∆ʒ X Cout
∆A’O = ∆ʒ X C’out
Since Cout > C’out
StabilityThe OR gate becomes unstable when |CNEG| > Cout (i.e.,C’out< 0 ), which will not happen because A’O is always positive.
∆AO > ∆A’O
Results and Discussions
ISCAS 2010 Slide 23
Results and Discussions
Power overhead:
The buffer amplifier (CF = 0.1 fF)
No power overhead (power saving of 5%)
Dual supply voltage and high Vt transistors needed
The differential amplifier (CF = 1 fF)
Power overhead = 5%
Limited by the constant gain-bandwidth product
The current conveyor (CL = 2.9 fF)
Power overhead = 30%
Suitable for high frequency applications ( No constant gain-bandwidth product limitation)
Results and Discussions
ISCAS 2010 Slide 24
Outline
Introduction and BackgroundMotivation and ObjectivesNegative Capacitance CircuitsStatistical Timing Yield Improvement Using Negative CapacitanceResults and DiscussionsConclusion
Conclusion
ISCAS 2010 Slide 25
Conclusion
A negative capacitance circuit is introduced for timing yield improvement in wide fan-in dynamic OR gates.
All the proposed negative capacitance circuits improve the timing yield (by reducing the mean delay), reduce the delay variability by 58%, and reduce the OR gate power by 10%.
The buffer amplifier circuit exhibits no overhead (5% total power saving) but a dual supply voltage and high-Vt transistors are required.
The differential amplifier and the current conveyor circuits have power overhead of 5% and 30%, respectively.
Conclusion
ISCAS 2010 Slide 27
64-input OR gate
NO CNEG
Buffer AmplifierCNEG
Differential Amplifier CNEG
Current Conveyor CNEG
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