i2s user guide - 京微雅格 · 2015-03-13 · receiver(master) sd control signals sd sck ws ws...
Post on 16-Mar-2020
0 Views
Preview:
TRANSCRIPT
I2S
User Guide
02/2015
Capital Microelectronics, Inc.
China
User Guide of I2S
http://www.capital-micro.com 2
Contents
Contents ................................................................................................................................................. 2
1 Introduction ..................................................................................................................................... 3
2 I2S Overview .................................................................................................................................... 4
2.1 Pin Description .......................................................................................................................... 4
2.2 Block Diagram ........................................................................................................................... 5
3 I2S IP Usage ...................................................................................................................................... 7
3.1 I2S operation timing diagram ..................................................................................................... 7
3.2 Wizard usage introduction ......................................................................................................... 7
4 Resource usage ................................................................................................................................. 9
5 Generate File Directory Structure .................................................................................................... 10
Revision History..................................................................................................................................... 12
User Guide of I2S
http://www.capital-micro.com 3
1 Introduction
This document mainly describes the usage of the I2S(Inter-IC Sound) IP. I2S bus is developed by Philips
Semiconductors as a serial link especially for digital audio, to standardize communication structures for both
the equipment and the IC manufacturer, because they increase system flexibility.
The I2S IP supports the following features:
Configurable operation mode (Tx/Rx, Master/Slave)
Configurable data width
Configurable sample data resolution
Normal interface
Device family support:
CME-M5,CME-M7,CME-HR3,CME_HR2
User Guide of I2S
http://www.capital-micro.com 4
2 I2S Overview
2.1 Pin Description
Table 2-1 I2S Pin description
Interface Name Direction Width Description
System clk_i Input 1 System clock
Control
interface
conf_res_i Input 5 Sample data resolution. Detail see the
note below the table
conf_ration_i Input 8 Clock divider ration. Detail see the note
below the table
conf_swap_i Input 1 Left/right sample order. Detail see the
note below the table
conf_en_i Input 1 Transmitter/receiver enable
Data
interface
sample_dat_i Input DATA_WIDTH Parallel data input, when receiver, it is
ignored
sample_dat_o Output DATA_WIDTH Paralleldata output, when transmitter, it is
ignored
rdwr_o Output 1 Write/readenable signal to buffer
I2S
interface
i2s_sd_i Input 1 Serial data input, when transmitter, it is
ignored
i2s_sck_i Input 1 Serial clock signal input, when master, it is
ignored
i2s_ws_i Input 1 Wordselect input,1-right channel,
0-left channel, when master, it is ignored
i2s_sd_o Output 1 Serial data output, when receiver, it is
ignored
i2s_sck_o Output 1 Serial clock signal output, when slave, it is
ignored
i2s_ws_o Output 1 Word select output,1-right channel,0-left
channel, when slave, it is ignored
Note:
1. The input port "conf_res_i " controls the number of bits .When transmitter, it means how many bits which
are transmitted from each item of data in the sample buffer and when receiver, it indicates how many bits are
received from the serial data line(i2s_sd_i) of each I2S data. It must be less than or equal to DATA_WIDTH and
the valid value is from 8 to 32. Any value that is less than 8 or more than 32bits, it will be set to the default
value of 8.
For example, When transmitter,ifconf_res_i is 24 and DATA_WIDTH is 32, then only the lower 24 bits of data
from data buffer are transmitted and the higher 8 bits of data are ignored. When receiver, it means that only
User Guide of I2S
http://www.capital-micro.com 5
lower 24 bits of data stored in the sample buffer are filled with data received from the i2s_sd_i port and the
higher 8 bits are filled with 0.
2.The input port "conf_ration_i" indicates the relationship between clk_i and i2s_sck_o . In the equation
below, the Ration is the value of conf_ration_i
Fi2s_sck_o= 𝐹clk _i
2∗(Ration +2)
3.The input port"conf_swap_i " indicates which data will be chosen when i2s_ws_o is low and high. The
relationship is as the table 2-2 below.
Table 2-2 conf_swap_i pin description
Mode Value
Description
conf_swap_i i2s_ws_o
Transmitter
1 1 Data read from the sample buffer's even addresses is
transferred
1 0 Data read from the sample buffer's odd addresses is
transferred
0 1 Data read from the sample buffer's odd addresses is
transferred
0 0 Data read from the sample buffer's even addresses is
transferred
Receiver
1 1 Data write to the sample buffer's even addresses is
transferred
1 0 Data write to the sample buffer's odd addresses is
transferred
0 1 Data write to the sample buffer's odd addresses is
transferred
0 0 Data write to the sample buffer's even addresses is
transferred
2.2 Block Diagram
Parallel-to-Serial Converter
Transmitter(master)
control signals
parallel data
sd
sck
ws
User Guide of I2S
http://www.capital-micro.com 6
Parallel-to-Serial Converter
Transmitter(slave)
control signals
Seriall-to-Parallel Converter
receiver(master)
sd
control signals
sd
sck
ws
ws
sclk
parallel data
parallel data
Seriall-to-Parallel Converter
Receiver(slave)
parallel data
control signals
sd
sck
ws
Figure2-1 I2S block diagram
The I2S interface consists of two parts, a transmitter and a receiver which both works as ether master or slave.
So, each work mode has different input and output ports. If it works as a master, it will generate the sck and
ws signals. Otherwise, the sck and ws are the input signals when it is works as a receiver.
When it works as transmitter, the parallel to serial converter will convert the parallel audio data to serial data
and output them on the SD line.
When it works as receiver, the serial to parallel converter will convert the data from SD line to parallel data.
User Guide of I2S
http://www.capital-micro.com 7
3 I2S IP Usage
3.1 I2S operation timing diagram
The I2S bus has 3 signals:
sck–serial clock
ws–word select
sd–serial data
The timing diagram is as Figure 3-1.
Figure3-1 I2S timing diagram
3.2 Wizard usage introduction
User can instantiate the I2S IP through IP Wizard on Primace software as the figure3-2(a),figure3-2(b) and
figure3-2(c).
Figure 3-2(a) select I2S IP in interface list
1 2 3 4 5 6 7 8 9 10 11 12
MSB
WORDn+1WORDn+1
WORDn
LSB MSB LSB
TimeGen
sck
ws
sd
User Guide of I2S
http://www.capital-micro.com 8
Figure 3-2(b) custom module name
Figure 3-2(c) configure parameters
User Guide of I2S
http://www.capital-micro.com 9
4 Resource usage
Resource usage of the I2S IP on Primace.
Table 4-1 I2S IP resource usage
Resource LUTs Regs
Data Width Mode
16 Tx, Slave 90 44
Tx, Master 154 53
Rx, Slave 115 43
Rx, Master 154 52
32
Tx, Slave 123 60
Tx, Master 189 69
Rx, Slave 123 59
Rx, Master 186 68
User Guide of I2S
http://www.capital-micro.com 10
5 Generate File Directory Structure
The I2S IP wizard generated file includes: source files (src), simulation files(sim) and example design files and
related document. The detailed design directory structure is as below.
Project
src outputs ip_core
ip_top.v(define by user)
i2s_codec.v
simsrc doc example
i2s_tx_rx_top_tb_modelsim.f
i2s_tx_rx_top_tb.v
CME_I2S_user_guide_EN01.pdf
I2S_m5.zip
CME_I2S_example_user_guide_EN01.pdf= directory
= source RTL code
= simulation related files
= documentation
i2s_v1
tx_buffer.v
m7_sim.v
M7S_SOC.v
I2s_tx_rx_top.v
*.vp(protected files)
src_vp
rx_buffer.v
fifo_ahb.v
syn_fifo.v
armcm3_v1.v
i2s_tx_rx_top_tb.do
I2S_m7.zip
Figure 5-1 IP wizard generated file directory structure
User Guide of I2S
http://www.capital-micro.com 11
Table 5-1 Generated File Directory structure
Directory Description
src\ Directory for project source code,
including IP wizard generate code
ip_core\ The directory specially for all IPs
\i2s_v1 Directory for I2SIP
\doc\CME_I2S_user_guide_EN01.doc User guide for I2S IP
\src IP Design RTL
\src\i2s_codec.v The src of I2S IP
\sim
\i2s_tx_rx_top_tb.v Testbenchfile
\ i2s_tx_rx_top_tb.do Modelsim simulation related files
\ i2s_tx_rx_top_tb_modelsim.f
\rx_buffer.v Other RTL design files for simulation
\tx_buffer.v
\m7s_sim.v
\M7S_SOC.v
\i2s_tx_rx_top.v
\fifo_ahb.v
\syn_fifo.v
\armcm3_v1.v
\src_vp
\*.vp Encrypted src files
\example
i2s_m5.zip I2S example
i2s_m7.zip
CME_I2S_example_user_guide_EN01.pdf The guide of I2S example
User Guide of I2S
http://www.capital-micro.com 12
Revision History
Revision Date Comments
1.0 2015-02-10 Initial release
top related