ia-64 architecture presentation
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8/3/2019 IA-64 Architecture Presentation
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5/4/12
Zakiya GaillardFlorida A&M University CET4542- Computer ArchitectureInstructor: Salman SiddiquiNovember 29, 2011
IA-64 Architecture
8/3/2019 IA-64 Architecture Presentation
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5/4/12
Overview
Introduction
Register Model
Register Specifications
Instruction Encoding
Software Pipelining
Intel® Intanium ™ Processor Block Diagram
Conclusion
Questions
8/3/2019 IA-64 Architecture Presentation
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Introduction
What is IA-64?
Joint Intel and HP Project
Explicitly Parallel Instruction Computer (EPIC)
Why it is introduced?
Need for high speed computing and Architecture
More complex compilers (JAVA)
Large Database Systems
Distributed Computing on Internet
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Register Model
• Register Stack Engine (RSE) automatically saves/restoresstack to memory when needed
• RSE may be designed to utilize unused memory bandwidthto perform register spill and fill operations in the background
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Register Specifications
• 128, 82-bit Floating Point Registers
• 128, 64-bit Application Registers
• 128, 65-bit General Purpose Registers
• 8, 64-bit Branch Registers
• 64, 1-bit Predicate Registers
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Instruction EncodingØ Each instruction
includes the opcode and threeoperands
Ø Each instructionsholds the identifierfor a correspondingPredicate Register
Ø Each bundlecontains 3independentinstructions
Ø Each instruction is41 bits wide
Ø Each bundle alsoholds a 5 bittemplate field
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Software Pipelining
Ø loops generally encompass alarge portion of aprogram’sexecution time,so it’s importantto expose as
much loop-levelparallelism aspossible.
Ø Overlapping oneloop iteration
with the next canoften increasethe parallelism.
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Software Pipelining
We can implement loops in parallel by resolve some problems.
• Managing the loop count,
•
Handling the renaming of registers for the pipeline,• Finishing the work in progress when the loop ends,
• Starting the pipeline when the loop is entered, and
• Unrolling to expose cross-iteration parallelism.
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Software Pipelining
IA-64 gives hardware support to compilers managing asoftware pipeline
Facilities for managing loop count, loop termination, and
rotating registers
The combination of these loop features and
predication enables the compiler to generate
compact code, which performs the essential work of
the loop in a highly parallel form.
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Intel® Intanium ™ Processor Block Diagram
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Conclusion
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