[ieee 2013 13th non-volatile memory technology symposium (nvmts) - minneapolis, mn, usa...

Recent Progress and Future Directions in

NAND Flash Scaling

Akira Goda

Micron Technology 8000 S. Federal Way, Boise, ID 83707

Email: agoda@micron.com

ABSTRACT

This paper discusses challenges and opportunities of

NAND cell scaling. The conventional wrap floating gate

(FG) cell has many scaling challenges including high

aspect ratio, cell-to-cell interference and increase in

E-field. Various planar cell technologies have been

suggested. Among them, a planar FG cell has

demonstrated the best performance and reliability at the

middle 10nm node. Key requirements for the 3D NAND

as a 10nm equivalent NAND have been discussed.

INTRODUCTION

NAND Flash scaling has been successful and the leader

in pitch scaling. At 20nm technology node and below,

the conventional wrap FG cell faces multiple scaling

issues such as structure scaling, cell-to-cell interference

and parasitic E-field [1-4]. A planar FG cell with High-K

IPD and metal gate has been introduced recently [5]. The

planar cell resolved many scaling issues and extends

NAND cell scaling to the middle 10nm node and below.

3D NAND cells have been suggested as a future scaling

direction [6-8]. In the 3D NAND, effective cell size

scaling is achieved by stacking multiple tiers. The

physical cell size is large and this contributes to

enhanced cell performance and reliability.

In this paper, recent progress of 2D NAND scaling and

technology requirements for the 3D NAND will be

reviewed.

NAND CELL SCALING

Physical scaling of wrap FG cell

In the conventional wrap FG cell, inter-poly-dielectrics

(IPD) and the control gate (CG) wrap around the floating

gate in order to achieve good gate coupling ratio (GCR)

(Fig.1). At sub-20nm node, CG and FG widths become

~10nm or less (Fig.1). Aspect ratio (A.R.) becomes >10

in both the bit line (BL) and the word line (WL)

directions [9].

Cell-to-cell interference and reliability scaling of

wrap FG cell

FG height of the wrap FG cell is as tall as >50nm.

Cell-to-cell interference increases significantly in a

scaled cell [10]. This widens MLC Vt distribution width.

WL air gap and STI air gap cell structures have been

proposed to reduce the interference [2-3]. E-field at the

top of FG and at the bottom of CG increases as cell is

scaled down [9, 11]. E-field between FG and the adjacent

CG is another problem [12]. These high E-field effects

degrade cycling reliability and data retention of the wrap

FG cell.

Planar FG cell as a 2D NAND cell scaling solution

Various planar cell approaches have been suggested to

overcome the scaling challenges of the wrap FG cell [5].

Those planar cells have thin charge storage layer for

physical scalability and low cell-to-cell interference.

High-K dielectric film is used as a blocking dielectric to

maintain good gate coupling ratio.

Program/Erase (P/E) Vt window and programming

slope are key requirements which the planar cells need to

meet [9]. MLC NAND needs >12V P/E window and ~1

programming slope (Figs. 2-3).

Fig. 1: Physical scaling of wrap FG cell.

978-1-4799-4110-0/13/$31.00 ©2013 IEEE

Among the various planar cell technologies, the planar

FG cell has demonstrated the best cell characteristics

(Fig. 4) and has been introduced successfully in industry

[5]. Excellent P/E properties and cycling reliability have

demonstrated in the middle 10nm cell (Figs. 5-6).

Transition to 3D NAND

When the 2D NAND is scaled down further, the

increase in cell noise (electron injection spread, random

telegraph signal and data retention) will widen MLC Vt

distribution [24-26]. Also, WL-to-WL E-field increases

with WL pitch scaling. These effects will eventually limit

2D NAND scaling in the future.

3D NAND is introduced in order to continue NAND

cost scaling without scaling the process feature size [6-8].

In the 3D NAND, effective cell size scaling is achieved

by stacking multiple tiers. The physical cell size can be

kept large (Fig. 7). This large physical cell size can

enhance cell performance and reliability.

There are two types of string architectures in 3D

Fig. 2: Program/erase Vt window

requirement for MLC NAND.

Fig. 3: Programming slope

requirement for program disturb

window.

Fig. 5: P/E characteristics of planar FG cell [5].

Fig. 6: Endurance characteristics of

a middle 10nm planar FG cell [5].

Fig. 4: P/E window and programming slope for

various NAND cells [9, 11, 13-23].

NAND (Fig. 8). One is a vertical string NAND [6] and

the other is a horizontal string NAND [7]. The vertical

string architecture is advantageous in electrical

performance and reliability due to the gate-all-around

(GAA) structure. The horizontal string architecture can

have smaller effective cell size due to the smaller

physical cell size.

Technology requirements for10nm 3D NAND

Key technology requirements to realize the 10nm 3D

NAND are summarized in table I.

Good P/E window and programming slope are key

requirements for the 3D NAND, too. A near vertical etch

profile is a key to maximizing the benefit of tier

stacking.

Most of the 3D NAND technologies use the poly Si

channel. This raises multiple technology challenges. The

mobility degradation needs to be minimized to obtain

enough sense current. Cell current enhancement was

recently demonstrated by engineering the poly Si process

[28-29]. Vt distribution has to be well controlled. A

significant Vt distribution improvement has been

achieved by optimizing the channel thickness [30].

Random Telegraph Signal (RTS) is another key area in

the poly Si channel [31-32].

These challenges warrant further investigation and

engineering in order to realize the 3D NAND

successfully.

SUMMARY

NAND cell scaling has been successful. The planar FG

cell has been introduced at the 20nm node and

demonstrated excellent performance and reliability at the

middle 10nm node. The planar FG cell extends 2D

NAND scaling. For the 10nm NAND and beyond, the

3D NAND can be an attractive solution.

REFERENCES

[1] K. Parat, VLSI-TSA, pp. 101-102, 2009

[2] K. Prall and K. Parat, IEDM Tech. Digest, pp. 5.2.1-5.2.4,

2010

[3] S. Lee, IMW Tech. Digest, pp.1-4, 2012

[4] Y. Park and J. Lee, IMW Tech. Digest, pp. 1-4, 2013

[5] N. Ramaswamy, et al., IMW, pp. 5-8, 2013

Fig. 8: 3D NAND string architectures [27].

Fig. 7: Physical and effective cell feature sizes scaling.

Table I: Key requirements for 10nm 3D NAND [9, 27].

[6] H. Tanaka, et al., VLSI Tech. Symp. Digest, pp.14-15,

2007

[7] W. Kim, et al., VLSI Tech. Symp. Digest, pp. 188-189,

2009

[8] J.H. Jang, et al., VLSI Tech. Symp. Digest, pp. 192-193,

2009

[9] A. Goda and K. Parat, IEDM Tech. Digest, pp. 2.1.1-2.1.4,

2012

[10] J.D. Lee, et al., IEEE Electron Device Letters, pp.

264-266, 2002

[11] K. S. Seol, et al., VLSI Tech. Symp. Digest, pp. 127-128,

2010

[12] Y. S. Kim, et al., IRPS, pp. 599-603, 2010

[13] T. Kamigaichi, et al., IEDM Tech. Digest, pp.

34.1.1-34.4.4, 2008

[14] M. Noguchi, et al., IEDM Tech. Digest, pp. 445-448,

2007

[15] S. Jayanti, et al., IEDM Tech. Digest, pp. 5.3.1-5.3.4,

2010

[16] W. Sakamoto, et al., IEDM Tech. Digest, pp.

34.1.1.-34.1.4, 2009

[17] S. H. Lin, et al., IEDM Tech. Digest, pp. 843-846, 2008

[18] Y. Park, et al., IEDM The. Digest, pp. 2.1.1-2.1.4, 2006

[19] H. T. Lue, et al., VLSI Tech. Symp. Digest, pp. 116-117,

2008

[20] D. Kwak et al., VLSI Tech. Symp. Digest, pp. 12-13,

2007

[21] H. T. Lue, et al., VLSI Tech. Symp. Digest, pp. 140-141,

2007

[22] C.H. Lee, et al., VLSI Tech. Symp. Digest, pp. 21-22,

2006

[23] G. Molas, et al., IEDM Tech. Digest, pp. 453-456, 2007

[24] C. Monzio Campagnoni, et al., IEEE Electron Device

Letters, pp. 2695-2702, 2008

[25] C. Miccoli, et al., IRPS, pp. 3B.1.1-3B.1.6, 2013

[26] H. Kurata, VLSI Circuits Symp., Digest, pp.140-141,

2006

[27] A. Goda, VLSI-TSA, pp. 1-2, 2013

[28] M. Toledano-Luque, et al., IEDM Tech. Digest., pp.

9.2.1-9.2.4, 2012

[29] A. Nitayama and H. Aochi, VLSI Tech. Symp. Digest, pp.

T60-T61, 2013

[30] Y. Fukuzumi, et al., , IEDM Tech. Digest, pp. 449-452,

2007

[31] E. Nowak et al., VLSI Tech. Symp. Digest, pp. 21-22,

2012

[32] M-K. Jeong et al., VLSI Tech. Symp. Digest, pp. 55-56,

2012