ieee 2014 15 vlsi titles list
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TECHNOS INC VLSI TITLES
VLSI TITLES
1. High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 Using
Common Sharing Distributed Arithmetic
2. Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only
14 Additions
3. Area-Delay Efficient Binary Adders in QCA
4. Area–Delay–Power Efficient Carry-Select Adder
5. Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells
6. Simplifying clock gating logic by matching Factored forms
7. Data encoding techniques for reducing energy Consumption in network-on-chip
8. Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-
Delay
9. Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect
Faults
10. Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}
11. Efficient Integer DCT Architectures for HEVC
12. Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for
Efficient FIR Filter Implementation
13. Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
14. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology,
and Implementations
15. Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard
Systematic Error-Correcting Codes
16. Multifunction Residue Architectures for Cryptography
17. Defense Against Primary User Emulation Attacks in Cognitive Radio Networks Using
Advanced Encryption Standard
18. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
CHACKO TOWERS, ANNA NAGAR MAIN ROAD, ANNA NAGAR, (NEXT TO SRI ANNAI XEROX), PUDUCHERRY CT: +91 9566492473, +91 9585338678. E-MAIL: contact.technos@gmail.com , technosprojects@gmail.com
TECHNOS INC VLSI TITLES
19. Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive
Algorithm
20. Eliminating Synchronization Latency Using Sequenced Latching
21. Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With
Low Adder-Count
22. Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
23. Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filter
24. Non binary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping
Algorithm
25. Efficient Algorithm and Architecture for Elliptic Curve Cryptography for Extremely
Constrained Secure Applications
26. An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply
Operator
27. Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation
Function
28. Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool
29. Parallel AES Encryption Engines for Many-Core Processor Arrays
30. Design of Testable Reversible Sequential Circuits
31. Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
32. A Novel Modulo Adder for 2n-2k- 1Residue Number System
33. Improvement of the Security of ZigBee by a New Chaotic Algorithm
34. CORDIC Based Fast Radix-2 DCT Algorithm
35. Split Radix Algorithm for Length 6mDFT
36. Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials
37. Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed
Arithmetic
38. Multicarrier Systems Based on Multistage Layered IFFT Structure
39. Design of an Error Detection and Data Recovery Architecture for Motion Estimation
Testing Applications
CHACKO TOWERS, ANNA NAGAR MAIN ROAD, ANNA NAGAR, (NEXT TO SRI ANNAI XEROX), PUDUCHERRY CT: +91 9566492473, +91 9585338678. E-MAIL: contact.technos@gmail.com , technosprojects@gmail.com
TECHNOS INC VLSI TITLES
40. Period Extension and Randomness Enhancement Using High-Throughput Reseeding-
Mixing PRNG
41. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based
on Fast FIR Algorithm
42. Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-Box
43. Low-Power and Area-Efficient Carry Select Adder
CHACKO TOWERS, ANNA NAGAR MAIN ROAD, ANNA NAGAR, (NEXT TO SRI ANNAI XEROX), PUDUCHERRY CT: +91 9566492473, +91 9585338678. E-MAIL: contact.technos@gmail.com , technosprojects@gmail.com
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