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INF4420Analog to digital converters

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Comparators Circuit topologies for analog to digital

FlashInterleavedFoldingInterpolationTwo-stepPipelinedAlgorithmicSARIntegrating

IntroductionADCs are used in numerous applications with differing requirements on speed, accuracy, and energy efficiency. ADC architectures have different strengths and weaknesses with respect to these trade offs. It is therefore important to understand not only how each converter works, but also its limitations and key aspects for performance.

ComparatorsBasic quantization element. Propagation delayMetastabilityResolution limited by offset and noiseKickback noiseMemory, hysteresis

Comparators

Improve resolution/ sensitivity of the comparator

Amplify the decision of the comparator

Buffer result to digital levels

ComparatorsComparator

example

Decision circuit

Pre-amplifier

Buffer not shown

ComparatorsClocked (latched) comparator

example

Van Elzakker, ISSCC, 2008

Pos. output

Flash ADC The Kelvin divider is used to generate 2N reference voltages, and comparators are used for quantizationVsh is Vin sampled and held

Flash ADCResistive divider string imposes the same limitations as for the DAC case. Linear gradient results in a parabolic shape of the INL curve.

Additionally, the comparators (preamplifiers) have offset, which must be less than ½ LSB. Auto-zero and fully differential (also 1/f-noise).

Flash ADC

● Bandgap stability and loading● Dynamic gain (not full settling in the

comparator preamplifier)● Sample and hold loading from an

exponential number of comparators

Time interleaved ADCRun N ADCs in parallel to increase conversion rate. Offset and gain mismatch between channels. Clock misalignment (fixed).

Time interleaved ADCExample: Monolithic 40 Gs/s ADC in anSiGeprocess

http://www.lecroy.com/tm/Library/WhitePapers/PDF/DBI_Explained.pdf

FoldingFold the input signalinto regions. Folderdetermines MSBs. Need fewer comparators.

Interpolation

Reducing number of comparator preamplifiers.

Reduced loading of the sample and hold.

Two-step ADC

Combine output from the MSB ADC (M bits) and the LSB ADC (N bits) for the full output.The MSB ADC must be linear to M + N bits (< ½ LSB for INL and DNL)

Two-step ADCPerformance constraints for the opamp used for gain and summing:

● Open loop gain, AOL, to achieve the desired closed loop gain, ACL.

● GBW to settle fast enough to the desired accuracy.

● Amplifier linearity

Again, errors must be less than ½ LSB.

Pipelined ADC

More than 1 bit per stage is possible.

Error correction

Algorithmic ADC

A variation of the pipeline ADC is the algorithmic ADC, which reuses a single stage for all bits. Each conversion now takes N (number of bits) clock cycles.

SAR ADCThe successive approximation register (SAR) tests each bit sequentially (MSB first, one clock period per bit), and decides whether too keep the bit or not based on the comparator's output.

Charge redistribution SARhttp://dx.doi.org/10.1109/JSSC.2010.2075310

http://dx.doi.org/10.1109/JSSC.2010.2043893

Examples of energy efficient (FoM) ADCs

http://converterpassion.wordpress.com/2011/05/05/adc-survey-spring-2011-update-on-fom-state-of-the-art/

Charge redistribution SARRef. capacitive divider DAC

Inherent sample and hold function

SAR not shown

Charge redistribution SARReset and sampling: In the first clock phase, Vin and Vos are sampled.

Next, the bottom plates are switched to ground, and Vx = -Vin. Then, each bit is tested (MSB first) by switching each capacitor between ground and Vref. Vx is compared for each bit (SAR).

Charge redistribution SARSuitable for low-power. No amplifiers needed (except for the comparator).

Comparator and charging of the capacitive array decides power consumption.

Capacitor mismatch limits resolution.

Speed limited by τ = Rtotal 2N C,

e-t/τ < 1 / 2N+1 (½ LSB), t > τ (N+1) ln 2

Integrating ADCDual slope integrating ADC. c0 and c1 are control signals

Vx

Counter and control logic not shown.

Integrating ADCIn phase 1, -Vin is integrated duringa fixed interval (T1). In phase 2, Vx isintegrated (discharged) by Vref. A digital counter is running from the start of phase 2 while Vx > 0. The counter value is the digital output.

Integrating ADC

Need many clock cycles to complete the conversion (slow), but can achieve high accuracy. A simpler alternative is the single slope ADC, which counts how long it takes to integrate Vref to Vin. (Less accurate).

Resources

B. Murmann, “ADC performance survey 1997–2012,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html

“IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters,” IEEE Std 1241-2010 (Revision of IEEE Std 1241-2000). http://dx.doi.org/10.1109/IEEESTD.2011.5692956

References

Baker, CMOS: Circuit Design, Layout, and Simulation, IEEE Wiley, 2010 Johns and Martin, Analog Integrated Circuit Design, Wiley, 1997 Sansen, Analog Design Essentials, Springer, 2006, Ch. 20