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Input/OutputTermination Techniques
Application NoteTS83 ADC Family
TS81 DMUX Family
Rev. 2169A–BDC–07/02
Input/Output TerminationTechniques
IntroductionThis document provides the Atmel ADCs and DMUX users with the different termina-tion techniques to be used with Atmel products. A wide panel of configurations for theanalog and clock inputs as well as for the data outputs are described in detail.
The principles of each technique are also presented so that one can eventuallychoose the proper implementation at the input and output of our products, consideringone’s application.
Finally, this document is not exhaustive. Nevertheless, it covers a wide area in termsof IO termination techniques.
1
Analog Input Termination Techniques
There are many different termination techniques, which can be used to reduce the impact ofthe transmission line effects. An overview of the Standard Input termination methods, whichcan be used for Atmel ADCs analog inputs, is provided in the following sections.
Since Atmel ADCs are both single-ended and differential-compatible, both cases will betreated in the next sections.
Single-ended Configuration
The following figure illustrates two input configurations, when the single-ended mode is cho-sen for the analog input. Here, the common mode of the driving system is assumed to be thesame as the one for the analog input of the ADC (Ground).
Figure 1. Configuration without Additional Termination Resistor
Figure 2. Configuration with 50Ω Termination Resistor
The first configuration may well be used in the case of an ADC device featuring an internal50Ω termination (inside the cavity for the TS83102G0 10-bit 2 Gsps ADC and on package forthe TS8388BG 8-bit 1 Gsps ADC).
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω
50Ω impedance line
50Ω
50ΩINB
IN
50Ω
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω
50Ω impedance line
50Ω
50ΩINB
IN
50Ω
2 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
The second configuration should be used when the differential analog input of the device isnot already 50Ω terminated.
If the system, which is driving the analog input, needs to be terminated externally, the termina-tion techniques are the following.
Figure 3. Configuration without Additional Termination Resistor
Figure 4. Configuration with 50Ω Termination Resistor
ADC InputBuffer
ADC Package
50Ω impedance line
UnterminatedDriving Source
50Ω
50Ω impedance line
50Ω
50ΩINB
IN
50Ω
ADC InputBuffer
ADC Package
50Ω impedance line
UnterminatedDriving Source
50Ω
50Ω impedance line
50Ω
50ΩINB
IN
50Ω
32169A–BDC–07/02
In all the previous configurations, it was assumed that there was no need to adjust the com-mon mode (CM). If the common mode from the driving device is not the same as the onespecified for the analog input of the ADC (GROUND), the user may have to choose betweenthe configurations illustrated below.
Figure 5. Configuration without Additional Termination Resistor and with Coupling Capacitor
Note: The values of the coupling capacitors are given for information only. They may change depend-ing on the input frequency.
Figure 6. Configuration with 50Ω Termination Resistor and with Coupling Capacitor
If the driving system has to be terminated, a 50Ω resistor has to be connected between theoutput of the system and the ground, as already described in the previous sections.
Note: The values of the coupling capacitors are given for information only. They may change depend-ing on the input frequency.
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω
50Ω impedance line
50Ω
50Ω INB
IN10 nF
50Ω
10 nF
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω
50Ω impedance line
50Ω
50ΩINB
IN10 nF
50Ω
10 nF
4 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
Differential Configuration
When the analog input is to be used in differential mode and assuming that the common modeof the driving system is the same as the one for the input of ADC (Ground), the possible con-figurations are the following:
Figure 7. Configuration without Additional Termination Resistor
Figure 8. Configuration with Differential 50Ω Termination Resistors and with GroundedMiddle Point
Figure 9. Configuration with Differential 50Ω Termination Resistors and with DecoupledMiddle Point
Note: The values of the coupling capacitors are given for information only. They may change depend-ing on the input frequency.
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω impedance line
50Ω
50Ω INB
IN
50Ω
50Ω
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω impedance line
50Ω
50ΩINB
IN
50Ω
50Ω
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω impedance line
50Ω 40 pF
50ΩINB
IN
50Ω
50Ω
52169A–BDC–07/02
Figure 10. Configuration with Differential 100Ω Termination Resistors and with FloatingMiddle Point
If the common mode of the driving system is not the same as the one of the input of the ADC,the previous configurations become.
Figure 11. Configuration without Additional Termination Resistor
Note: The values of the coupling capacitors are given for information only. They may change depend-ing on the input frequency.
Figure 12. Configuration with Differential 50Ω Termination Resistors and with CouplingCapacitors
Note: The values of the coupling capacitors are given for information only. They may change depend-ing on the input frequency.
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω impedance line
100Ω
INB
IN
50Ω
50Ω
10 nF
10 nF
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω impedance line INB
IN
50Ω
50Ω
50Ω
50Ω
10 nF
10 nF
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω impedance line INB
IN
50Ω
50Ω
50Ω
50Ω
6 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
Figure 13. Configuration with Differential 100Ω Termination Resistors and with CouplingCapacitors
Note: The values of the coupling capacitors are given for information only. They may change depend-ing on the input frequency.
The same schemes are valid when the driving system is not terminated. In these cases, theuser only has to add the external 50Ω resistors on both outputs of the driving system in theschemes.
The user may only have a single-ended generator to drive the ADC input differentially (pre-ferred way at high sampling rates). In this case, the user still has the opportunity to use abalun. The different configurations in this mode of operation are described in the next section.
10 nF
10 nF
ADC InputBuffer
ADC Package
50Ω impedance line
50Ω Driving Source
50Ω impedance line INB
IN
50Ω
50Ω
100Ω
72169A–BDC–07/02
Configuration with a Balun
The following section only represents the three general cases illustrating the use of a balun toconvert the single-ended signal from the generator into a differential signal for the ADC input.The different cases with an unterminated driving system have not been presented. The user can refer to the schemes given previously for these configurations.
Figure 14. Configuration without Additional Termination Resistor
Figure 15. Configuration with Differential 50Ω Termination Resistors and with Grounded Middle Point
Figure 16. Configuration with Differential 100Ω Termination Resistors and with Floating Middle Point
ADC InputBuffer
ADC Package
Balun 50Ω impedance line50Ω impedance line
50Ω Driving Source
50Ω
50Ω impedance line
50Ω
50ΩINB
IN
Balun
ADC InputBuffer
ADC Package
50Ω impedance line50Ω impedance line
50Ω Driving Source
50Ω
50Ω impedance line
50Ω
50ΩINB
IN
Balun
ADC InputBuffer
ADC Package
50Ω impedance line50Ω impedance line
50Ω Driving Source
50Ω
50Ω impedance line
100Ω
INB
IN
8 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
Clock Input Termination Techniques
In the case when the clock input of the ADC is not used in ECL levels but is centered around0V, the configurations presented for the analog inputs (ground common mode voltage),except the AC coupled cases, can be transferred to the input clock.
ECL Single-ended Configuration
With a clock in ECL level, the main idea to abide by is to connect the negative clock to thecommon mode voltage of the positive clock input: -1.3V (ECL) through a 50Ω terminationresistor (if not already implemented).
Figure 17. Configuration without Additional 50Ω Termination Resistor
Figure 18. Configuration with 50Ω Termination Resistor
ADC InputBuffer
ADC Package
50Ω impedance line
ECL 50Ω Driving Source
50Ω
-1.3V
50Ω impedance line
50Ω
50ΩCLKB
CLK
ADC InputBuffer
ADC Package
50Ω impedance line
ECL 50Ω Driving Source
50Ω
-1.3V
50Ω impedance line
50Ω
50ΩCLKB
CLK
92169A–BDC–07/02
ECL Differential Configuration (ADCs Only)
When the clock is used in differential mode with ECL levels, two cases can be taken intoconsideration:
• the ADC is 50Ω on-package (or internally) terminated;
• the ADC needs an external termination.
Each configuration is described in what follows.
Figure 19. ADC Configuration with External Termination
ECL Differential Open EmitterOutput Buffer
VCC = 0V
ECL DifferentialADC Input Buffer
without Termination
ADC Package
50Ω impedance line
50Ω impedance line
50Ω 50Ω
VTT = VCC - 2V = -2V
CLKB
CLK
10 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
Figure 20. ADC Configuration with 50Ω On-package (or internal) Termination
Note: Since the ADC is already terminated, the standard termination scheme for the ECL driver (VTT =VCC - 2V with Rt = 50Ω) does not apply here. The Figure 20 is an equivalent terminationscheme.
ECL Differential Configuration (DMUX Only)
Figure 21. DMUX Configuration with ECL Differential
Note: Since the ADC is already terminated, the standard termination scheme for the ECL driver (VTT =VCC - 2V with Rt = 50Ω) does not apply here. The Figure 21 is an equivalent terminationscheme.
ECL Differential Open EmitterOutput Buffer
VCC = 0V
ECLDifferentialADC Input
Buffer
ADC Package
50Ω impedance line
50Ω impedance line
274Ω 274Ω
-5V
CLKB
CLK
50Ω
50Ω
40 pF
ECL Differential Open EmitterOutput Buffer
VCC = 0V
ECLDifferential
DMUX InputBuffer
DMUX Package
50Ω impedance line
50Ω impedance line
274Ω
50Ω
50Ω
274Ω
-5V
10 pF
CLKB
CLK
112169A–BDC–07/02
Digital Input Termination Techniques for the DMUX
The termination technique recommended for the DMUX Data inputs is similar to the one usedfor the DMUX input clock, since all the DMUX input buffers have been designed according tothe same architecture.
Figure 22. Digital Input Configuration
Note: Since the ADC is already terminated, the standard termination scheme for the ECL driver (VTT =VCC - 2V with Rt = 50Ω) does not apply here. The Figure 22 is an equivalent terminationscheme.
ECL Differential Open EmitterOutput Buffer
VCC = 0V
ECLDifferential
DMUX InputBuffer
DMUX Package
50Ω impedance line
50Ω impedance line
274Ω
50Ω
50Ω
274Ω
-5V
10 pF
DATA INB
DATA IN
12 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
Data Output Termination Techniques
Open Loaded Termination (ADCs)
Figure 23. TS8388Bx and TS8308500 Open Loaded Output Termination
Figure 24. TS83102G0 Open Loaded Output Termination
In the previous configurations, the output level is determined by VPLUSD: ECL/LVDS modes areavailable (refer to the product data sheets for more information).
75Ω 75Ω
- +
11 mA
DVEE
ADC Output Buffer
75Ω impedance line
75Ω impedance line
Out
OutB
VPLUSD
50Ω 50Ω
- +
10.5 mA
DVEE
ADC Output Buffer
50Ω impedance line
50Ω impedance line
Out
OutB
VPLUSD
132169A–BDC–07/02
75Ω Termination For TS8388Bx and TS8308500 Only
Figure 25. TS8388Bx and TS8308500 75Ω Termination
50Ω Termination For the TS8388BX and TS8308500 ADCs
Figure 26. TS8388Bx and TS8308500 50Ω Termination
75Ω 75Ω
- +
11 mA
DVEE
ADC Output Buffer
75Ω impedance line
75Ω impedance line
Out
OutB
75Ω
75Ω10 nF
VPLUSD
75Ω 75Ω
- +
11 mA
DVEE
ADC Output Buffer
50Ω impedance line
50Ω impedance line
Out
OutB
50Ω
50Ω10 nF
VPLUSD
14 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
For the TS83102G0 ADC
Figure 27. TS83102G0 50Ω Termination
(VTT + R) Termination (DMUX Only)
In the specific case of the Atmel DMUX, the output buffers need to be terminated with a “VTT+ R” termination (see the different schematics) because the DMUX output buffers are in open-emitter configuration.
There are three types of output signals for the DMUX: Data Ready, Digital Output Data andReference Voltage. All of them have the same behavior against VPLUSD and Swing Adjust, andtheir associated buffers are similar.
Figure 28. DMUX Differential Data Ready Output Buffer
50Ω 50Ω
- +
10.5 mA
DVEE
ADC Output Buffer
50Ω impedance line
50Ω impedance line
Out
OutB
50Ω
50Ω10 nF
VPLUSD
I
V+D
600 600
In
Vrefsa
VEE(-5V)
Inb
480
DMUX differential Data Ready Buffer Outside DMUX
I
Ir
IrR RVTT
Out
Outb
152169A–BDC–07/02
Figure 29. DMUX Digital Output Data Buffer
Figure 30. DMUX Reference Buffer
The only care to be taken to terminate these output buffers properly is to make sure that theoutput current Ir never exceeds 36 mA.
The relationship between VTT, R, Ir and Vout (output voltage level) is given here:
I
V+D
600 600
In
Vrefsa
VEE(-5V)
Inb
480
DMUX Data Buffer Outside DMUX
I
Ir
Ir R
VTT
Out
V+D
6k 600
Vrefsa
VEE(-5V)
9606k
DMUX Reference Buffer Outside DMUX
I
Ir
Ir R
VTT
Out
IrVout Vtt–
R--------------------------=
16 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
Block Diagram
TS81102G0 DMUX
Figure 31. TS81102G0 DMUX Block Diagram
B 2
Counter(8 stage
shift register)
DataReadygeneration
Data Path Clock Path
mux
Port Selection Clock
DataOutputClock
A[0
..7/9
]
C[0
..7/9
]
E[0
..7/9
]
G[0
..7/9
]
B[0
..7/9
]
D[0
..7/9
]
F[0
..7/9
]
H[0
..7/9
]
Ref
A
Ref
C
Ref
E
Ref
G
Ref
B
Ref
D
Ref
F
Ref
H
Even Ports Odd Ports
muxC
lkIn
DE
MU
XD
elA
djC
trl
Clk
InT
ype
Asy
ncR
eset
Rat
ioS
el
delay delay
AD
CD
elA
djO
utA
DC
Del
Adj
Ctr
lA
DC
Del
Adj
In
Sw
iAdj
Vpl
usD
Out
VE
EG
ND
BIS
T
I[0..7
/9]
NbB
it
Latc
h S
el E
ven/
Odd
[1..8
/10]
evenmasterlatch
evenslavelatch
oddmasterlatch
oddslavelatch
8/10
8
8
3
Counter
NAP
Rat
ioS
el
8/10
Status
ClkPar
8
8
1
VC
C
DR/DR
FS/8
FS/8
BIST
8/10
Phasecontrol
Syn
cRes
et
RstGen
Reset
DIO
DE
172169A–BDC–07/02
TS8388B ADC
Figure 32. TS8388B ADC Block Diagram
TS83102G0 ADC
Figure 33. TS83102G0 ADC Block Diagram
MASTER/SLAVE TRACK AND HOLD AMPLIFIER
VIN, VINB
CLOCKBUFFER
GAIN
GORB DATA, DATAB OR, ORBDRRB DR, DRB
CLK, CLKB
4
4 5
4 5
8
8
RESISTORCHAIN
ANALOGENCODING
BLOCK
INTERPOLATIONSTAGES
REGENERATIONLATCHES
ERROR CORRECTION ANDDECODE LOGIC
OUTPUT LATCHES ANDBUFFERS
DRDRB
DRRB
B/BG
Logic block
Ana
log
Qua
ntiz
er
PGEB
D0DR0B
D9D9B
ORORB
GA
Clock generation
CLK
CLKB
50
50
VIN
VINB
5050
Sample and Hold
SDA
18 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
Internal Timing Diagram
DMUX Timing Diagram
This diagram corresponds to an established operation of the DMUX with Synchronous Reset.
Figure 34. DMUX Timing Diagram
Data In
DR In = Fs
DR/2 In = Fs/2 = ClkPar
Master Even Latch
Master Odd Latch
Slave Even Latch
Slave Odd Latch
Synchronous reset = Fs/8
Internal reset pulse
Port Select A
Port Select B
Port Select C
Port Select D
Port Select E
Port Select F
Port Select G
Port Select H
Latch Select A
Latch Select B
Latch Select C
Latch Select D
Latch Select E
Latch Select F
Latch Select G
Latch Select H
A to H Port Out
A to H LatchOut
DROut
500 ps min
N N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24
N N+8 N+16 N+24
N+1 N+9 N+17 N+25
N+2 N+10 N+18 N+26
N+3 N+11 N+19 N+27
N+4 N+12 N+20
N+5 N+13 N+21
N+6 N+14 N+22
N+7 N+15 N+23
N to N+7 N+8 to N+15 N+16 to N+23
N+25 N+26 N+27 N+28 N+29 N+30 N+31
N+24 N+26 N+28 N+30N+14 N+16 N+18 N+20 N+22N+6 N+8 N+10 N+12N N+2 N+4
N+3 N+5 N+7 N+9 N+11 N+13 N+15 N+17 N+19 N+21 N+23 N+25 N+27 N+29
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N+10
N+11
N+12
N+13
N+14
N+15
N+16
N+17
N+18
N+19
N+20
N+21
N+22
N+23
N+24
N+25
N+26
N+27
N+28
N+29
N
N+1 N+31
N+30
N+1
192169A–BDC–07/02
ADCs Timing Diagrams
The timing diagrams for the TS8388B and TS83102G0 ADCs are similar. Care should only betaken regarding the values of the specified timings (Refer to the corresponding device datasheets for more details).
Figure 35. Data Ready Reset, Clock Held at LOW Level
Figure 36. Data Ready Reset, Clock Held at HIGH Level
TC1 TC2
TA = 250 ps
XX
N+1X
N+2X
N+3N
DIGITALOUTPUTS
(VIN, VINB)
Data Ready(DR, DRB)
(CLK, CLKB)
XN+5
N-4 N-3 NN-2 N-1
TC = 1000 ps
X X
N+4
TOD = 1360 ps1360 ps
DRRB1ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 720 ps
N-1
TD2 = TC2+TOD-TDR= TC2+40 ps = 540 ps
TDR = 1320 ps
DATA DATA DATA DATA DATADATA DATAN-5 N+1
TD1 = TC1+TDR-TOD= TC1-40 ps = 460 ps
TC1 TC2
TA = 250 ps
N+1 N+2 N+3N
DIGITALOUTPUTS
(VIN, VINB)
Data Ready(DR, DRB)
(CLK, CLKB)
N+5
N-4 N-3 NN-1N-2
TC = 1000 ps
N+4
TOD = 1360 ps1360 ps
DRRB
1ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
TRDR = 720 ps
N-1
TD2 = TC2+TOD-TDR= TC2+40 ps = 540 ps
TDR = 1320 ps
DATA DATA DATA DATA DATADATA DATAN-5 N+1
1000 ps
XX
X
XXX X
TD1 = TC1+TDR-TOD= TC1-40 ps = 460 ps
20 Input/Output Termination Techniques2169A–BDC–07/02
Input/Output Termination Techniques
ADC and DMUX Testbench
Figure 37. Example of ADC and DMUX Testbench
INPUT SIGNALGENERATOR
FILTER
ADC DMUX
TSEV8388BG or TSEV83102G0EVALUATION BOARD
TSEV81102G0EVALUATION BOARD
- HISTOGRAM
- FFT
- RECONSTRUCTED SIGNAL
- ENOB, SFDR, INL, DNL, ...
SCIENTIFIC COMPUTER
LabView
ACQUISITIONSYSTEM
DIGITAL ACQUISITION
SYNCHRONIZATION
CLOCK SIGNALGENERATOR
212169A–BDC–07/02
Printed on recycled paper.
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