inter strip resistance in silicon position-sensitive detectors

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Interstrip resistance in silicon position-sensitive detectors

E. Verbitskaya, V. Eremin, N. Safonova*

Ioffe Physical-Technical Institute of Russian Academy of SciencesSt. Petersburg, Russia

*also Saint-Petersburg Electrotechnical University “LETI”, Russia

N. Egorov, S. Golubkov

Research Institute of Material Science and Technology (RIMST)Zelenograd, Russia

15 RD50 WorkshopCERN, Geneva, November 16-18, 2009

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Outline

• Motivation• Physical model of interstrip resistance• Experimental results on interstrip resistance in as-

processed Si detectors• Influence of nonequilibrium carrier generation• RIS in n-type FZ and CZ Si samples

Conclusions

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

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Motivation

Current subjects:

Development of operational model for voltage terminating structure (VTS) and current terminating structure (CTS, edgeless detectors)

Strip detector performance at SLHC: very high fluences and enhanced bulk generated current

Noise performance of spectroscopic strip detectors (GSI, Darmstadt)

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

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Special design of test structures

FZ n-Si, >5 k d = 300 m Vfd 20 V

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

p+-n-n+ structure - area 1x1 mm2

Strips: two interpenetrating “combs”: - pitch 25 m increased length of interstrip gap

equivalent to 4 cm strips

1

2

5

Physical model

1 = 2

- potentials at the strips

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Distortion of symmetric distributions of potential and electric field may stimulate excess current flow between strips

Components that control interstrip resistance RIS:

- surface leakage- interface current

SiO2p+

n+

Interface current

1 2

Surface leakageSiO2p+

n+

Interface current

1 2

Surface leakage

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Measurements of interstrip gap

characteristics

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

U1 – bias voltage applied to p-n junction

U2 – bias voltage between the strips

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I-V characteristics of interstrip gap

I = Id + Iinst

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

-3

-2

-1

0

1

2

3

-25 -20 -15 -10 -5 0 5 10 15 20 25U 2 (V)

I (

mA

)

V1=0V1=5VV1=10VV1=20VV1=30VV1=50VV1=70VV1=90V

1

Id – strip dark currentIinst – interstrip current

FZ n-Si, # WP 3-6-2

A

U2

I instI d

IA

U2

I instI d

I

8E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Current flow in interstrip gap

U2cr with U1

U2cr - range of bias voltage in which Iinst is small

hole drift

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

-30 -20 -10 0 10 20 30

U 2 (V)

I (m

A)

U1 = 30 V

U2cr

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Interstrip current Iinst

Iinst(U2): dark current is subtracted

Regions with different slopes:

A and A*: R = (dIinst/dU2)-1

- ohmic isolation resistance, independent on U1, related mainly with surface leakage

B: current step Iinst

Iinst and dIinst/dU2 as U1

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Interstrip resistance:

RIS = dU2/dIinstInterstrip current, FZ, # WP 3-6-2

-0.05

0.00

0.05

0.10

0.15

-5 -4 -3 -2 -1 0 1 2 3 4 5U 2 (V)

I ins

t (n

A)

05V10V20V30V50V70V90V

U1 (V):

I inst

A

A*

B

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Origin of interstrip current step Iinst

≠ 2

Current switching – redistribution of strip hole currents

In detector: Switching acts asnegative feedback recovery of potential balance

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Rsw = (dIinst/dU2)-1

in Iinst region

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Interstrip resistance vs bias voltage

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Rsw = dU2/dIis at U2 0

Rsw with U1

R 200 G

irrespective to U1 and at ±U2

0 20 40 60 80 1000

10

20

30

40

50

60

70

Rs

w (

G)

U1 (V)

RRs

w

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

-6 -4 -2 0 2 4 6

U 2 (V)

I inst

(n

A)

U1 = 30 VR

R

Rsw

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Influence of nonequilibrium carrier generation

Carrier generation: - by LED illuminating p+ side - white light on n+ side

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Interstrip current vs. U2

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

-6 -4 -2 0 2 4 6

U 2 (V)

I ins

t (n

A)

50 V

70 V

90 V

U1:

Current vs. U2, p+ illumination

0

2

4

6

8

10

12

-6 -4 -2 0 2 4 6U 2 (V)

I (n

A)

50 V

70 V

90 V

U1:

Current vs. U2, n+ illumination

0

1

2

3

4

-6 -4 -2 0 2 4 6U 2 (V)

I (n

A)

50 V

70 V

90 V

U1:

I = Iph + Iinst

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Influence of nonequilibrium carrier generation on RIS

R and Rsw with carrier generation

R p+ illumination – high n and p under SiO2

Rsw at carrier generation: no dependence on U1

– switching is controlled by photocurrent rather than dark current

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Ratio of Rsw is about one half of current ratio since ½ of a total structure current is switched

40 50 60 70 80 90 100 110 1200.1

1

10

100

R,

, Rs

w (

G)

U1 (V)

R, darkness

R, p+ illumination

R, n+ illumination

Rsw, darkness

Rsw, p+ illumination

Rsw, n+ illumination

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Influence of Si type

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Similar behavior of Iinst vs. U1 and U2

Interstrip current, # CZ 311-2

-0.1

-0.05

0

0.05

0.1

0.15

-4 -3 -2 -1 0 1 2 3 4U 2 (V)

I ins

t (n

A)

05 V10 V20 V30 V50 V70 V90 V

U1:

FZ n-Si CZ n-SiInterstrip current, FZ, # WP 3-6-2

-0.05

0.00

0.05

0.10

0.15

-5 -4 -3 -2 -1 0 1 2 3 4 5U 2 (V)

I ins

t (n

A)

05V10V20V30V50V70V90V

U1 (V):

I inst

A

A*

B

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Comparison of Iinst for different Si types

U2cr is smaller in CZ Si

U2 corresponding to Iinst is smaller in CZ Si

Ris similar

Current vs. U 2

-0.1

-0.05

0

0.05

0.1

-20 -15 -10 -5 0 5 10 15 20U 2 (V)

I (m

A)

FZ, WP 3-6-2

CZ, 311-2

U1 = 90 V

Interstrip current

-0.05

0

0.05

0.1

0.15

-6 -4 -2 0 2 4 6

U 2 (V)

I inst

(nA

)

FZ, WP 3-6-2

CZ, 311-2

U1 = 90 V

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

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Comparison of Rsw for different Si types

0 20 40 60 80 1000

10

20

30

40

50

60

70

Rs

w (

G)

U1 (V)

FZ, WP 3-6-2 CZ, 311-2

Parameterization: Rsw = A - B(U1)0.5

Rsw is smaller in CZ Si

0 2 4 6 8 10 120

10

20

30

40

50

60

70

Rs

w (

G

(U1)0.5 (V)0.5

FZ Si CZ Si

FZ: Rsw = 7.21010 – 5.9 109(U1)0.5 CZ: Rsw = 2.51010 – 2.2109(U1)0.5

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Rsw depends on bulk generation current

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Different wafer orientation

Detectors with different configuration

Study of irradiated Si detectors

Future studies

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

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Conclusions

The factors that define interstrip isolation resistance are: - surface leakage, - interface current, - new mechanism - distortion of symmetric potential distribution at the

strips and switching of strip currents.

Switching of strip currents is a negative effect since it decreases interstrip isolation. This effect may control interstrip resistance rather than ohmic conductance between the strips.

R is about 200 G irrespective to the bias voltage while Rsw is bias dependent and decreases with bias voltage rise down to few G

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

Results are partially published in: V. Eremin et al., Semiconductors 43 (2009) 796.

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This work was made in the framework of RD50 collaboration and supported in part by:• RF President Grant # 2951.2008.2 • Fundamental Program of Russian Academy of Sciences on collaboration with CERN

Acknowledgments

Thank you for attention!

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009