introduction to microfabrication, chapter 1

Introduction to microfabrication,

chapter 1

sami.franssila@aalto.fi

Dimension in microworld

Fig. 1.12

Materials

substrate

thin film 2

surface

interface 2

interface 1

Substrate: thick piece of materials (0.5 mm = 500 µm)

Thin films: 10-1000 nm;SiO2 (insulator)Al (conductor)

Silicon most often

Fig. 1.3: Electron beam lithographydefined gold-palladium nanobridge

Microfabrication vs. Nanofabrication ?

Fig. 24.4: Focussed ion beam patterned Aalto vase

Fig. 1.1: Microtechnology subfield evolution from 1960’s onwards.

Silicon microelectronics

0.5 µm CMOS in SEM micrograph 65 nm CMOS in TEM micrograph

Fig. 1.18: Schematic of a MOS transistor: gate, source (S) and drain (D) in an active area defined by thick isolation oxide.

MOS transistor

Patterning process: optical lithography and etching

Fig. 9.1

Photoresist application

Resist dispensing Acceleration Final spinning 5000 rpm(a few milliliters) (resist expelled) (partial drying via evaporation)

Surface preparation for adhesion improvement

Spin coating

Photoresist exposure

Positive resist: exposed parts become soluble

Negative resist: exposed parts cross-linked and insoluble

Positive AZ resist:

Lithography test structures

Contact/proximity lithography

gap

2

dglinewidth

λ = 436 nmd = 1 µm (standard resist)

Linewidth min ≈ 0.5 µm g = 0 (contact)

Linewidth min ≈2 µm g = 10 µm (proximity)

Contact/proximity resolution

Vacuum contact

Hard contact

Soft contact

20 µm proximity gap

Linewidth and pitch

The goal of lithography is to make lines and spaces small (only this will increase device packing density).

Linewidth on previous slide was actually half-pitch: the resolving power of optical systems was divided half and half for line and space.

In making microprocessor gates, line is smaller than space, e.g. 100 nm pitch results in 30 nm gate and 70 nm space.

After lithography

a b

c

de

f

a) ion implantation (Ch 15) b) wet etching (Ch 11) c) moulding (Ch 18)d) plasma etching (Ch 11) e) electroplating (Ch 29)f) lift-off (Ch 23)

Imprinting/embossing

• Press 3D master into softened polymer

• Remove after cooling below Tg

Apply photofilm Press together Stamp release Residue clearing

Nanoimprinted Photonic Crystal Devices

Silicon stamp:

High lateral resolutionProtrusion height ~ 100 nm

Anders Kristensen

UV nanoimprinting

• Use light to harden the polymer

Apply polymer Stamp+UV Stamp release Residue clearing

Superhydrophobic biomimetic surfaces by UV-NIL

Nanotech 2006, Boston

AlignmentMicrodevices are build layer-by-layer.Alignment is needed to make those structures coincide.

Wafer with first level structures

Mask with second level structrures

Mask and wafer are aligned before exposure

Resistor alignment

#1 resistor

#2 contactsholes

#3 metallization

Resistor material patterned

Insulation deposited

Contach hole lithography & etching

Metal deposition

Silicon wafersscribe lines for chip dicing

wafer flat for orientation checking

alignment marks for lithography

edge exclusion

Fig. 1.20 Real estate allocation on a wafer

Fig. 1.4: 100 mm diameter silicon wafer

Silicon strengths

• silicon is a good mechanical material• silicon is good thermal conductor• silicon is transparent in infrared• silicon is a semiconductor• silicon is optically smooth and flat• silicon is known inside out

consider silicon first, alternatives then

Single crystalline silicon(a.k.a. monocrystalline)

<100> silicon

Polycrystalline and amorphous materials

Fig. 1.6

Other substratesGlass amorphous SiO2 + Na2O + CaO +…Quartz amorphous or crystalline SiO2

Sapphire crystalline Al2O3 Alumina amorphous Al2O3 klkGaAs crystallineGaN crystallineSiC crystallineSteel multicrystallineNickel multicrystallineAlN multicrystallineZnO amorphous (“glass”)PCB polymerLTCC ceramic

High temperature processes

T > ~ 900oC

Thermal oxidation Si + O2 SiO2

Diffusion

Arrhenius processes

3.5eV

2.2 eV

kT

Ea

eTzrate )(

Optoelectronics

Fig. 1.14: Silicon solar cell

Fig. 6.2: GaAs multiple quantum well solar cell

MOEMS (Micro Opto Electro Mechanical Systems)

Fig. 1.2: Micromirror made of silicon, 1 mm diameter, is supported by 1.2 µm wide, 4 µm thick torsion bars (detail figure), from ref. Greywall.

Fig. 21.4: variable optical attenator

Micro-optics

Fig. 1.7: Aluminum oxide and titanium oxide thin films deposited over silicon waveguide ridges, courtesy Tapani Alasaarela.

Fig. 7.13: Refractive index SiO2/SiOxNy/SiO2 waveguide: nf 1.46/1.52/1.46. From ref. Hilleringmann.

MEMS: Micro Electro Mechanical Systems

Fig. 29.21: Microgears, courtsey Sandia National Labs.

Fig. 21.3: comb-drive actuator

Power MEMS

Fig. 1.17: Microturbine

Fabricated by bonding together 5 silicon wafers.

Microfluidics and BioMEMS

Fig. 1.13: silicon microneedle Fig. 1.11: Oxy-hydrogen burner flame ionization detector

Cleanroom

Yield

nYY 0 Yield of a total process is a product of yield of individual process steps

50 step MEMS processY0 = 0.999 95%

500 step DRAM process, Y0 = 0.999 61%

Yield (2)

DAeY Yield depends on chip area (A) and defect density (D)

D = 0.01 mm-2 (= 1/cm2)

A= 10 mm2 Y = 90%

A= 100 mm2 Y = 37%

Industries

Integrated circuits $300 BOther semiconductors $30 BFlat panels displays $100 BHard disks $30 BSolar cells $30 BMEMS $10 B

Equipment $30 BMaterials $10 B