introduction tovlsi programming lecture 4: data handshake circuits
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Introduction toVLSI Programming Lecture 4:
Data handshake circuits
(course 2IN30)
Prof. dr. ir.Kees van Berkel
Dr. Johan Lukkien
04/19/23 Kees van Berkel 2
Time table 2005
date class | lab subject
Aug. 30 2 | 0 hours intro; VLSI
Sep. 6 3 | 0 hours handshake circuits
Sep. 13 3 | 0 hours handshake circuits assignment
Sep. 20 3 | 0 hours Tangram
Sep. 27 no lecture
Oct. 4 no lecture
Oct. 11 1 | 2 hours demo, fifos, registers | deadline assignment
Oct. 18 1 | 2 hours design cases;
Oct. 25 1 | 2 hours DLX introduction
Nov. 1 1 | 2 hours low-cost DLX
Nov. 8 1 | 2 hours high-speed DLX
Nov. 29 deadline final report
04/19/23 Kees van Berkel 3
Lecture 4
Outline:• Recapitulation Lecture 3 • Data encoding; push and pull handshakes • Tangram assignment command • Handshake components: handshake latch,
transferrer, multiplexer, adder• Handshake circuits & Tangram programs: fifo
buffers and shift registers
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Header: handshake circuit
L=0 L=1
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Sequencer realization
Sequencer: area, delay, energy: • Area: 5 gate equivalents• Delay per cycle: 8 gate delays• Energy per cycle: 10 transitions
xar
bk
br
cr
ck ak
04/19/23 Kees van Berkel 6
Handshake signaling and data
request ar
active side
passive side
acknowledge ak
data ad
request ar
active side
passive side
acknowledge ak
data ad
push channel
versus
pull channel
04/19/23 Kees van Berkel 7
Handshake signaling: push channel
ack ak
req ar
time
early ad
broad ad
late ad
04/19/23 Kees van Berkel 8
Data bundling
In order to maintain event ordering at both sides of a channel, the circuit must satisfy data bundling constraint:
• for push channel: delay along request wire must exceed delay of data wire;
• for pull channel: delay along acknowledge wire must exceed delay of data wire.
04/19/23 Kees van Berkel 9
Handshake signaling: pull channel
ack ak
req ar time
early ad
broad ad
late ad
When data wires are invalid: multiple and incomplete transitions allowed.
04/19/23 Kees van Berkel 10
Tangram assignment x:= f(y,z)
yw
zw
y
f
z
xw0
| x xrxw1
Handshake circuit
y
f
z
| x
y
f
z
| x
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Four-phase data transfer
b
c
r / brtime
bd / cd
ba / cr
ca / a
1 2 3 4 5
04/19/23 Kees van Berkel 12
Handshake latch
[ [ w ; [w : rd:= wd] [] r ; r] ]
• 1-bit handshake latch: wd wr rd
wd wr rd wk = wr
rk = rr
x rw
wd
wr
rd
04/19/23 Kees van Berkel 13
N-bit handshake latch
wr
wd1 rd1
wd2
wk
rd2
wdN rdN
...
rr
rk
area, delay, energy • area: 2(N+1) gate eqs.• delay per cycle:
4 gate delays• energy per write cycle:
4 + 0.5*2N transitions, in average
04/19/23 Kees van Berkel 14
Transferrer
[ [ a : (b ; c)] ; [ a : (b ; cd:= bd ; c ; cd:= )] ]
a
b c
ar ak
br
bk
bd
ck
cr
cd
04/19/23 Kees van Berkel 15
Multiplexer
[ [ a : c ; a : (cd:= ad; c ; cd:= ) [] b : c ; b : (cd:= bd; c ; cd:= ) ] ]
Restriction: ar br must hold at all times!
|
a
b
c
04/19/23 Kees van Berkel 16
Multiplexer realization
data circuit
control circuit
04/19/23 Kees van Berkel 17
Logic/arithmetic operator
[ [ a : (b || c) ]; [ a : ((b || c) ; ad:= f(bd , cd ))]]
Cheaper realization (delay sensitive):
[ [ a : (b || c) ]; [ a : ((b || c) ; ad:= f(bd , cd ))]; “delay” ; ad:= ]
fb
ca
04/19/23 Kees van Berkel 18
A one-place fifo buffer
byte = type [0..255]
& BUF1 = main proc(a?chan byte & b!chan byte).begin x: var byte | forever do a?x ; b!x odend
BUF1a b
04/19/23 Kees van Berkel 19
A one-place fifo buffer
byte = type [0..255]
& BUF1 = main proc(a?chan byte & b!chan byte).begin x: var byte| forever do a?x ; b!x odend
;
x ba
;
aa x bb
x
;
xx
04/19/23 Kees van Berkel 20
2-place buffer
byte = type [0..255]
& BUF1 = proc (a?chan byte & b!chan byte).begin x: var byte | forever do a?x ; b!x od end
& BUF2: main proc (a?chan byte & c!chan byte).begin b: chan byte | BUF1(a,b) || BUF1(b,c) end
BUF1a b BUF1 c
04/19/23 Kees van Berkel 21
Two-place ripple buffer
04/19/23 Kees van Berkel 22
Two-place wagging buffer
ba
byte = type [0..255]
& wag2: main proc(a?chan byte & b!chan byte).begin x,y: var byte| a?x ; forever do (a?y || b!x) ; (a?x || b!y) odend
04/19/23 Kees van Berkel 23
Two-place ripple register
…begin x0, x1: var byte| forever do b!x1 ; x1:=x0; a?x0 odend
04/19/23 Kees van Berkel 24
4-place ripple register
byte = type [0..255]
& rip4: main proc (a?chan byte & b!chan byte). begin x0, x1, x2, x3: var byte | forever do b!x3 ; x3:=x2 ; x2:=x1 ; x1:=x0 ; a?x0 od end
04/19/23 Kees van Berkel 25
4-place ripple register
• area : N (Avar + Aseq )
• cycle time : Tc = (N+1) T:=
• cycle energy: Ec = N E:=
x0 x1 x2 x3x3 x0 x3 x2 x3x1 x2x0 x1x0
04/19/23 Kees van Berkel 26
Introducing vacancies
…begin x0, x1, x2, x3, v: var byte| forever do (b!x3 ; x3:=x2 ; x2:=v) || (v:=x1 ; x1:=x0 ; a?x0) odend
• what is wrong?
04/19/23 Kees van Berkel 27
Introducing vacancies
forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0 ; a?x0)) ; x2:=v od
or:
forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0)); (x2:=v || a?x0)od
04/19/23 Kees van Berkel 28
“synchronous” 4-p ripple register
forever do (s0:=m0 || s1:=m1 || s2:=m2 || b!m3 ); ( a?m0 || m1:=s0 || m2:=s1 || m3:=s2)od
m0
s0
m1
s1
m2
s2
m3x0 b
m0
s0
m1
s1
m2
s2
m3x0 b
m0
s0
m1
s1
m2
s2
m3x0 b
m0
s0
m1
s1
m2
s2
m3x0 b
m0
s0
m1
s1
m2
s2
m3x0 b
04/19/23 Kees van Berkel 29
4-place wagging register
forever do b!x1 ; x1:=x0 ; a?x0; b!y1 ; y1:=y0 ; a?y0od
x0 x1
x2 x3y0 y1
a b
x1
x2b
x0 x1
a
x0
ba
y1
bb
y0 y1
a
y0
a
04/19/23 Kees van Berkel 30
8-place register
4-way wagging
forever do b!u1 ; u1:=u0 ; a?u0; b!v1 ; v1:=v0 ; a?v0; b!x1 ; x1:=x0 ; a?x0; b!y1 ; y1:=y0 ; a?y0od
04/19/23 Kees van Berkel 31
Four 88 shift registers compared
type area [gate eq.]
cycle time [nanosec.]
energy/message [nanojoule]
linear 167 43 0.75
pseudo synchronous
264 23 1.46
4-way wagging
238 26 0.29
wagging 201 34 0.48
04/19/23 Kees van Berkel 32
Next session: lecture 5
Outline:• Tangram overview• Compilation: Tangram Handshake Circuits• Tools• Demonstration• Lab work: assignment “fifos and registers”
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