istd 103 computation structures - singapore university of...
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ISTD 103 Computation Structures
Prof. Tomas Lozano-Perez
This file and its contents are provided under license from MIT and the named authors, under the terms of the MIT-SUTD Collaboration.
The following citation should be attached to any portions of this material used in a derivative work, such as excerpts, remixing, and
adaptations:
Lozano-Perez, Tomas, using materials originally developed by Christopher J. Terman and Stephen A Ward. Course materials
for ISTD 103, Computation Structures. MIT-SUTD Collaboration, 2012.
The creator(s) of teaching and course materials used in Singapore University of Technology and Design (“the University”) shall have
his or her name attributed as the creator of the teaching and course materials (“Course Materials”) regardless of whether the creator is
or is not a staff member of the University.
Where the Course Materials have been modified or altered or adapted, the name of the person who modified, altered or adapted the
Course Materials shall also be reflected in the statement of attribution.
Examples:
Original creator: [name of creator]
Modified by: [name]
This Policy does not address the ownership and licensing rights of Course Materials which are dealt with in the University’s Intellectual
Property Policy and/or in specific agreements signed by the University.
This file may contain references to the MIT version of the course that will need to be removed or revised before use in other contexts.
For a list of frequently-occurring references, or more information about this document, please consult the MIT-SUTD Collaboration
Intranet at http://web.mit.edu/sutd
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0 1
ALUA B
“ ”
DataMemory
WD
A
RD
R/W
RegisterFile
(3-port)
RA1 RA2
WA
WE
WD
RD1 RD2
InstructionMemory
A
D
RegisterFile
(3-port)
RA1 RA2
WA
WE
WD
RD1 RD2
5
32
CLK
Write Enable
Write Address
Write Data
(independent Read addresses)
(Independent Read Data)
32 32
5 5
Rc: <25:21>
+4
InstructionMemory
A
D
Rb: <15:11>Ra: <20:16>
ALUA B
ALUFN
Control Logic
WERF
ALUFN
WERF
00
←
Rc: <25:21>
+4
InstructionMemory
A
D
Rb: <15:11>Ra: <20:16>
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
ALUFN
BSEL01
C: SXT(<15:0>)
BSEL
WERF
WERF
00
←
Rc: <25:21>
+4
InstructionMemory
A
D
Rb: <15:11>Ra: <20:16>
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
BSEL01
C: SXT(<15:0>)
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSEL
ALUFN
Wr
WERF
WERF
00
←
Rc: <25:21>
+4
InstructionMemory
A
D
Ra: <20:16>
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
BSEL01
C: SXT(<15:0>)
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSEL
ALUFN
Wr
Rb: <15:11>
RA2SEL
Rc: <25:21>
0 1
RA2SEL
WERF
WERF
00
←
Rc: <25:21>
+4
InstructionMemory
A
D
Ra: <20:16>
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
BSEL01
C: SXT(<15:0>)
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSEL
ALUFN
Wr
Rb: <15:11>
RA2SEL
Rc: <25:21>0 1
RA2SEL
JT
PCSEL 01234
JT
PCSEL
WERF
WERF
00
PC+4
← ←
Data Memory
WDSEL0 1 2
WA
PCSEL 01234
JT
PC
+4
InstructionMemory
A
D
Rb: <15:11>
RA2SEL
Rc: <25:21>0 1
Ra: <20:16>
+Register
File
RA1 RA2
RD1 RD2
BSEL01
C: SXT(<15:0>)
Z
ALUA B
PC+4+4*SXT(C
WA WD
WE4*SXT(<15:0>)
ALUFN
Control Logic
Z
PCSEL
RA2SEL
BSELWDSEL
ALUFNWr
Rc: <25:21>
JT
WERF
WERF
00
PC+4
← ←
← ←
’
“ ” “ ”
’ “ ”
C: X = X * 123456;
BETA:
LD(X, r0)
LDR(c1, r1)
MUL(r0, r1, r0)
ST(r0, X)
...
c1: LONG(123456)
←
Data Memory
WDSEL0 1 2
WA
PCSEL 01234
JT
PCIF
+4
InstructionMemory
A
D
Rb: <15:11>
RA2SEL
Rc: <25:21>0 1
Ra: <20:16>
+Register
File
RA1 RA2
RD1 RD2
BSEL01
C:SXT( <15:0>)Z
ALUA B
WA WD
WE
ALUFN
Control Logic
Z
PCSEL
RA2SEL
BSELWDSEL
ALUFNWr
PC+4
Rc: <25:21>
PC+4+4*SXT(C)
ASEL 01
JT
ASEL
WERF
WERF
00←
PC+4+4*SXT(C)
ASEL 01
Data Memory
WDSEL0 1 2
WARc: <25:21>0
1XP
PC
JT
+4
InstructionMemory
A
D
Rb: <15:11>Ra: <20:16>
RA2SEL
Rc: <25:21>
+Register
File
RA1 RA2
RD1 RD2
BSEL01
C: SXT(<15:0>)
Z
ALUA B
JT
WA WD
WE
ALUFN
Control Logic
Z
ASEL
BSEL
PCSEL
RA2SEL
WDSEL
ALUFNWr
PC+4
0 1
Wr
01234
XAdrILLOP
WASEL
WASEL
IRQ
WERF
WERF
00← ←“ ”← ← “ ”
PCSEL
“ ”
OP
OPC
LD
ST
JMP
BEQ
BN
E
LD
R
Illo
p
IRQ
ALUFN F(op) F(op) "+" "+" -- -- -- "A" -- --
WERF 1 1 1 0 1 1 1 1 1 1
BSEL 0 1 1 1 -- -- -- -- -- --
WDSEL 1 1 2 -- 0 0 0 2 0 0
WR 0 0 0 1 0 0 0 0 0 0
RA2SEL 0 -- -- 1 -- -- -- -- -- --
PCSEL 0 0 0 0 2 Z ? 1 : 0 Z ? 0 : 1 0 3 4
ASEL 0 0 0 0 -- -- -- 1 -- --
WASEL 0 0 0 -- 0 0 0 0 1 1
“ ”
PC+4+4*SXT(C)
ASEL 01
Data Memory
WDSEL0 1 2
WARc: <25:21>0
1XP
PC
JT
+4
InstructionMemory
A
D
Rb: <15:11>Ra: <20:16>
RA2SEL
Rc: <25:21>
+Register
File
RA1 RA2
RD1 RD2
BSEL01
C: SXT(<15:0>)
Z
ALUA B
JT
WA WD
WE
ALUFN
Control Logic
Z
ASEL
BSEL
PCSEL
RA2SEL
WDSEL
ALUFNWr
PC+4
0 1
Wr
01234
XAdrILLOP
WASEL
WASEL
IRQ
WERF
WERF
00
PCSEL
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