itu-t g.8262 compliance test results for: si5347/46 19 … · 2017-01-17 · itu-t g.8262...
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Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 1 of 49
ITU-T G.8262 Compliance Test Results for: Si5347/46 Rev 1.0 19-November- 2014
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 2 of 49
Contents
1 Wander Generation .............................................................................................................................. 8
1.1 Wander Generation MTIE Option 1, G.8262 EEC Option 1 ...................................................................... 9
1.1.1 Input and Output Parameters .......................................................................................................... 9
1.1.2 Requirement Compliance ................................................................................................................. 9
1.1.3 RESULTS Si5347: PASS .................................................................................................................... 10
1.2 Wander Generation TDEV G.8262 EEC Option1 (Done with 1.1) ........................................................... 11
1.2.1 Requirement Compliance ............................................................................................................... 11
1.2.2 RESULTS Si5347: PASS .................................................................................................................... 11
1.3 Wander Generation MTIE Stratum ITU-T G.8262 EEC Option 2 ............................................................. 12
1.3.1 Input and Output Parameters ........................................................................................................ 12
1.3.2 Requirement Compliance ............................................................................................................... 12
1.3.3 RESULTS Si5347: PASS .................................................................................................................... 13
1.4 Wander Generation TDEV G.8262 EEC Option2 (Done with 1.3) ........................................................... 14
1.4.1 Requirement Compliance ............................................................................................................... 14
1.4.2 RESULTS Si5347: PASS .................................................................................................................... 14
2 Wander Transfer ................................................................................................................................. 15
2.1 Transfer Function of the PLL for Option 1 and Option 2 ........................................................................ 16
2.1.1 Input and Output Parameters ........................................................................................................ 16
2.1.2 Requirement Compliance ............................................................................................................... 16
2.1.3 RESULTS Si5347 EEC Option 1: PASS .............................................................................................. 17
2.1.4 RESULTS Si5347 EEC Option 2: PASS .............................................................................................. 18
2.2 Wander Transfer TDEV Stratum-3 G.8262 Option 2 .............................................................................. 19
2.2.1 Input and Output Parameters ........................................................................................................ 19
2.2.2 Requirement Compliance ............................................................................................................... 19
2.2.3 RESULTS Si5347: PASS .................................................................................................................... 20
3 Wander Tolerance .............................................................................................................................. 21
3.1 Wander Tolerance G.8262 Option 1 ....................................................................................................... 22
3.1.1 Input and Output Parameters ........................................................................................................ 22
3.1.2 Requirement Compliance ............................................................................................................... 22
3.1.3 RESULTS Si5347: PASS .................................................................................................................... 22
3.2 Wander Tolerance G.8262 Option 2 (Done with 2.2) ............................................................................. 23
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 3 of 49
3.2.1 Input and Output Parameters ........................................................................................................ 23
3.2.2 Requirement Compliance ............................................................................................................... 23
3.2.3 RESULTS Si5347: PASS .................................................................................................................... 23
4 Jitter Tolerance ................................................................................................................................... 24
4.1 Jitter Tolerance G.8262 Option 1 and Option 2 ..................................................................................... 24
4.1.1 Input and Output Parameters ........................................................................................................ 24
4.1.2 Requirement Compliance ............................................................................................................... 25
4.1.3 RESULTS Si5347 EEC Option 1: PASS .............................................................................................. 26
4.1.4 RESULTS Si5347 EEC Option 2: PASS .............................................................................................. 27
5 Phase Transient Generation ............................................................................................................... 28
5.1 Short Term Phase Transient Response G.8262 Option 1 ....................................................................... 28
5.1.1 Input and Output Parameters ........................................................................................................ 29
5.1.2 Requirement Compliance ............................................................................................................... 29
5.1.3 RESULTS Si5347: PASS .................................................................................................................... 30
5.2 Short Term Phase Transient Response G.8262 Option 2 ....................................................................... 31
5.2.1 Input and Output Parameters ........................................................................................................ 31
5.2.2 Requirement Compliance ............................................................................................................... 31
5.2.3 RESULTS Si5347: PASS .................................................................................................................... 32
5.3 Phase Transient Generation w/ Signal Interruptions G.8262 EEC Option1............................................ 33
5.3.1 Input and Output Parameters ........................................................................................................ 33
5.3.2 Requirement Compliance ............................................................................................................... 34
5.3.3 RESULTS Si5347: PASS .................................................................................................................... 34
5.4 Phase Discontinuity G.8262 Option 1 ..................................................................................................... 35
5.4.1 Input and Output Parameters ........................................................................................................ 36
5.4.2 Requirement Compliance ............................................................................................................... 36
5.4.3 RESULTS Si5347: PASS .................................................................................................................... 36
5.5 Phase Discontinuity G.8262 Option 2 ..................................................................................................... 37
5.5.1 Input and Output Parameters ........................................................................................................ 37
5.5.2 Requirement Compliance ............................................................................................................... 37
5.5.3 RESULTS Si5347: PASS .................................................................................................................... 38
6 Holdover ............................................................................................................................................. 39
6.1 Holdover G.8262 Option 1 ...................................................................................................................... 40
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 4 of 49
6.1.1 Input and Output Parameters ........................................................................................................ 40
6.1.2 Requirement Compliance ............................................................................................................... 40
6.1.3 RESULTS Si5347: PASS .................................................................................................................... 41
6.2 Holdover G.8262 Option 2 ...................................................................................................................... 42
6.2.1 Input and Output Parameters ........................................................................................................ 42
6.2.2 Requirement Compliance ............................................................................................................... 42
6.2.3 RESULTS Si5347: PASS .................................................................................................................... 43
7 Free-run Accuracy ............................................................................................................................... 44
7.1 Free-run Accuracy G.8262 Option 1 and Option 2 ................................................................................. 45
7.1.1 Input and Output Parameters ........................................................................................................ 45
7.1.2 Requirement Compliance ............................................................................................................... 45
7.1.3 RESULTS Si5347: PASS .................................................................................................................... 45
8 Pull-in/Hold-in .................................................................................................................................... 46
8.1 Pull-in Range G.8262 Option 1 and Option 2 ......................................................................................... 46
8.1.1 Input and Output Parameters ........................................................................................................ 46
8.1.2 Requirement Compliance ............................................................................................................... 47
8.1.3 RESULTS Si5347: PASS .................................................................................................................... 47
9 Conclusion .......................................................................................................................................... 48
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 5 of 49
Introduction
This report reviews and explains the results of the G.8262 compliance testing that has been verified for the
devices listed in the table below. This document will give a summary of the test set-ups, as well as the
compliance criteria while showing the results from each test. Testing was done using the ANUE 3500, and in
some cases other test equipment.
The devices-under-test (Si5347/46) were configured and controlled using Silicon Lab’s ClockBuilder Pro
Software. Each of the tests includes references to the CBPro project files used to enable the Si543x device to
pass each test. The project files (attached to this PDF document) should be used by designers as guidelines to
follow when configuring a specific design for G.8262 compliance. All CBPro project files are accessible
attachments in this report file.
Option 2 EEC compliance was tested at 0.1 Hz target loop bandwidth and Option 1 was tested with a target of 4
Hz loop bandwidth.
Product G.8262 EEC Option 1
Compliance G.8262 EEC Option 2 Compliance
Si5346A-A-GM
Si5346B-A-GM
Si5347A-A-GM
Si5347B-A-GM
*The Si5346 device is compliant with ITU-T G.8262 by functional similarity to the Si5347 device.
SyncE Free-run
Accuracy Holdover Wander Filtering Phase Transient
G.8262 EEC
Option 1 +/- 4.6 ppm
+/- 2
ppm/day
1 – 10 Hz
Si5347 4Hz* MTIE < 1 ns
G.8262 EEC
Option 2 +/- 4.6 ppm
+/- 0.39
ppm/day
0.1 Hz
Si5347 0.1Hz*
MTIE < 1 ns
Phase slope < 61,000 ns/s
*Actual bandwidth may differ slightly. The actual bandwidth will be provided by ClockBuilder Pro.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 6 of 49
ITU-T G.8262 Standards Matrix
Test G.8262 Description Opt 1 Opt 2 Compliance Board
1. Wander Generation
1.1 MTIE, TDEV EEC Option 1, Must not exceed MTIE
TDEV masks
8.1.1 Si5347
1.2 8.1.1 Si5347
1.3 MTIE, TDEV EEC Option 2, must not exceed MTIE
TDEV masks
8.1.2 Si5347
1.4 8.1.2 Si5347
2. Wander Transfer
2.1 Transfer Function of the PLL Option 1 and Option 2:
Look for peaking 10.1 10.2 Si5347
2.2 TDEV Wander Transfer Option 2: File Playback 10.2 Si5347
3. Wander Tolerance
3.1 Wander Tolerance Option 1: File Playback 9.1.1 Si5347
3.2 Wander Tolerance Option 2: File Playback 9.1.2 Si5347
4. Jitter Tolerance
4.1 Automated way of injecting noise and monitoring LOL 9.2.1 9.2.1 Si5347
5. Phase Transient Generation
5.1 Short Term Phase Transient Option 1 11.1.1 Si5347
5.2 Short Term Phase Transient Option 2
11.1.2
11.4.2 Si5347
5.3 Phase Transient Generation w/ Signal Interruptions
Option 1 11.3.1 - Si5347
5.4 Phase Discontinuity Option 1 11.4.1 Si5347
5.5 Phase Discontinuity Option 2 11.4.2 Si5347
6. Holdover Performance
6.1 Option 1 11.2.1 Si5347
6.2 Option 2 11.2.2 Si5347
7. Freerun Accuracy
7.1 Accuracy Option 1 and Option 2 6.1 6.2 Si5347
8. Pull-in/Hold-in
8.1 Pull-In and Hold-In Option 1 and Option 2 7.1.1 7.1.2 Si5347
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 7 of 49
TCXO Input
A Rakon 513872 RTX Series TCXO with CMOS outputs and capacitive terminations was used for all of the
compliance testing done in this report. Choosing a low jitter TCXO with proper terminations is critical for
passing the compliance tests. Figure 1 is a diagram showing the proper terminations for the Rakon 513872 RTX
Series TCXO.
Figure 1: TCXO Recommended configuration
This is the recommended configuration for driving a 3.3V CMOS clock into the XA/XB inputs. Note the
following:
1. The CMOS output buffers are designed and verified to drive capacitive loads, not resistors. Therefore a
capacitor divider should be used as shown.
2. Capacitive dividers typically have lower noise than resistive dividers.
3. The capacitive divider must be placed as close as possible to the XA input to minimize reflections. The
divider should not be placed on the TCXO board.
4. Ideally the TCXO should be placed as close as possible to the Si5347 to minimize reflections.
5. If the TCXO has to be far from the Si5347, then the output impedance of the CMOS driver +Rs should
be equal to the transmission line impedance to minimize reflections.
TCXO
Si534x
IN0 XA/XB
IN1 OUT0
IN2 OUT1
IN3 OUT1B
15pF Rs
10pF 0.1uF
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 8 of 49
1 Wander Generation
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
Buffer
Agilent Digital Oscilloscope: DSO9104A
Power Supply for Buffer: Agilent E3620A (3.3V input)
DUT: Si5347
TCXO: Rakon 513872 RTX Series
Si534x
GPS/BITS
3
IN0
ANUE 3500 BOX
25MHz
XA/XB
TCXO
2 1 LCD Screen S
S 4
BNC Connect
IN1 . .
Buffer
OUT0 OUT0B
IN2 IN3
Agilent Scope
Ethernet Connection
PC
100 MHz/4 = 25MHz
25MHz
25MHz
25MHz
10MHz
Figure 2: Wander Generation Test Set-up
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 9 of 49
1.1 Wander Generation MTIE Option 1, G.8262 EEC Option 1 While the PLL is locked to an input clock signal that is wander free, it will not generate wander that exceeds the
MTIE mask shown in figure 1/G.8262. There is no noise modulation added into the input.
1.1.1 Input and Output Parameters 10 MHz GPS Reference Locked to Anue Box
25 MHz Input to DUT Generated from Anue Box
25 MHz Output from DUT Measured into BNC3 on Anue Box
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
1.1.2 Requirement Compliance
ITU-T G.8262 Section 8.1.1 Option 1
Si5347-WanderGenerationOption1.slabtimeproj
Si5346-WanderGenerationOption1.slabtimeproj
Figure 3: Output G.8262 Requirement Mask for Wander Generation MTIE Option 1.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 10 of 49
1.1.3 RESULTS Si5347: PASS
Figure 4: Si5347 Option 1 Wander Generation TDEV and MTIE Results.
- - - - MTIE LIMIT
MTIE Result
- - - - TDEV LIMIT
TDEV Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 11 of 49
1.2 Wander Generation TDEV G.8262 EEC Option1 (Done with 1.1) While the PLL is locked to an input clock signal that is wander free, it will not generate wander that exceeds the
TDEV mask shown in 8.1.1 Figure 2. The wander free clock signal must include band-limited (10 Hz single-poll
rolloffs). Use test data from above having collected both MTIE and TDEV at the same.
1.2.1 Requirement Compliance ITU-T G.8262 Section 8.1.1 Option 1
Si5347-WanderGenerationOption1.slabtimeproj
Si5346-WanderGenerationOption1.slabtimeproj
Figure 5: Output Requirement Mask for Wander Generation TDEV Option 1
1.2.2 RESULTS Si5347: PASS Note: Results for the Si5347 are shown in graph above in section 1.1.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 12 of 49
1.3 Wander Generation MTIE Stratum ITU-T G.8262 EEC Option 2 While the PLL is locked to an input clock signal that is wander free, it will not generate wander that exceeds the
MTIE mask shown in figure 3 Section 8.1.2 of the G.8262 standard. The wander free clock signal must include
band-limited (10 Hz single-poll rolloffs). This is set in the Wander Measurement. Use a board with the TCXO
0.1Hz filtering (CBPro) for G.8262 Option 2.
1.3.1 Input and Output Parameters 10 MHz GPS Reference Locked to Anue Box
25 MHz Input to DUT Generated from Anue Box
25 MHz Output from DUT Measured into BNC3 on Anue Box
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 2: 0.1Hz Loop Bandwidth Setting on the DUT
1.3.2 Requirement Compliance
ITU-T G.8262 Section 8.1.2 Option 2
Si5347-WanderGenerationOption2.slabtimeproj
Si5346-WanderGenerationOption2.slabtimeproj
Figure 6: Output G.8262 Requirement Limit Mask for Wander Generation MTIE Option 2
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 13 of 49
1.3.3 RESULTS Si5347: PASS
Figure 7:Si5347 MTIE and TDEV Results Wander Generation Option 2
- - - - MTIE LIMIT
MTIE Result
- - - - TDEV LIMIT
TDEV Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 14 of 49
1.4 Wander Generation TDEV G.8262 EEC Option2 (Done with 1.3) While the PLL is locked to an input clock signal that is wander free, it will not generate wander that exceeds the
TDEV mask shown in 8.1.2 Figure 4. The wander free clock signal must include band-limited (10 Hz single-poll
rolloffs). Use test data from above having collected both MTIE and TDEV together.
1.4.1 Requirement Compliance ITU-T G.8262 Section 8.1.2 Option 2
Si5347-WanderGenerationOption2.slabtimeproj
Si5346-WanderGenerationOption2.slabtimeproj
Figure 8: Output G.8262 Requirement Limit Mask for Wander Generation TDEV Option 2.
1.4.2 RESULTS Si5347: PASS Note: Results for the Si5347 are shown in graph above in section 1.3.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 15 of 49
2 Wander Transfer
Figure 9: Wander Transfer Test Set-up
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
Buffer
Agilent Digital Oscilloscope: DSO9104A
Power Supply for Buffer: Agilent E3620A (3.3V input)
DUT: Si5347
TCXO: Rakon 513872 RTX Series
Si534x
2 GPS/BITS
3
IN0
ANUE 3500 BOX
25MHz
XA/XB
TCXO
2 1 LCD Screen S
S 4
BNC Connect
IN1 . .
Buffer
OUT0 OUT0B
IN2 IN3
Agilent Scope Ethernet Connection
PC
100 MHz/4 = 25MHz
25MHz
25MHz
25MHz
10MHz
Figure 9: Wander Transfer Test Set-up
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 16 of 49
2.1 Transfer Function of the PLL for Option 1 and Option 2 Wander transfer is determined by the PLL loop BW and peaking. Option 1 has a 1 Hz to 10Hz BW. Option 2 has
a 0.1Hz BW. Both Option 1 and Option 2 require <0.2dB of peaking.
2.1.1 Input and Output Parameters 10 MHz GPS Reference Locked to Anue Box
25 MHz Input to DUT Generated from Anue Box
25 MHz Output from DUT Measured into BNC3 on Anue Box
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
2.1.2 Requirement Compliance ITU-T G.8262 EEC Section 10.1 Option 1 and Option 2
Si5347-WanderTransferOption1.slabtimeproj
Si5347-WanderTransferOption2.slabtimeproj
Si5346-WanderTransferOption1.slabtimeproj
Si5346-WanderTransferOption2.slabtimeproj
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 17 of 49
2.1.3 RESULTS Si5347 EEC Option 1: PASS Peaking is less than 0.02 dB from results. The device has an actual loop bandwidth of 4.46 Hz.
Figure 10: Results of the Si5347 Transfer Function Loop Bandwidth Option 1
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 18 of 49
2.1.4 RESULTS Si5347 EEC Option 2: PASS Peaking is less than 0.04 dB from results. The device has an actual loop bandwidth of 62 mHz.
Figure 11: Results of the Si5347 Transfer Function Loop Bandwidth Option 2
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 19 of 49
2.2 Wander Transfer TDEV Stratum-3 G.8262 Option 2 Measure the output wander (TDEV) when the device is locked to a clock that has wander defined by the TDEV
mask shown in figure 8 Table 10 Option2 G.8262. Make sure that the TDEV output is below the mask shown in
the requirement compliance (Figure 11).
2.2.1 Input and Output Parameters 10 MHz GPS Reference Locked to Anue Box
25 MHz Input to DUT Generated from Anue Box
Input File: G.8262_Table10_TDEV_Opt2.1c.txt (Input from Figure 8 of the G.8262 spec)
25 MHz Output from DUT Measured into BNC3 on Anue Box
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
2.2.2 Requirement Compliance ITU-T G.8262 EEC Section 10.2 Table 13 Option 2
Si5347-WanderTransferOption2.slabtimeproj
Si5346-WanderTransferOption2.slabtimeproj
Figure 12: Output G.8262 Requirement Mask for Wander Transfer Option 2
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 20 of 49
2.2.3 RESULTS Si5347: PASS The Si5347 tracks the input very closely, as required and expected.
s
Figure 13: Si5347 Wander Transfer Results Option 2
- - - - TDEV LIMIT
TDEV Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 21 of 49
3 Wander Tolerance
Figure 14: Test Set-Up Wander Tolerance
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
Buffer
Agilent Digital Oscilloscope: DSO9104A
Power Supply for Buffer: Agilent E3620A (3.3V input)
DUT: Si5347
TCXO: Rakon 513872 RTX Series
Si534x
GPS/BITS
3
IN0
ANUE 3500 BOX
25MHz
XA/XB
TCXO
2 1 LCD Screen S
S 4
BNC Connect
IN1 . .
Buffer
OUT0 OUT0B
IN2 IN3
Agilent Scope
Ethernet Connection
PC
100 MHz/4 = 25MHz
25MHz
25MHz
25MHz
10MHz
Figure 14: Test Set-Up Wander Tolerance
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 22 of 49
3.1 Wander Tolerance G.8262 Option 1 A PLL that is locked to an input clock must be able to tolerate the wander defined in Figure 5/G.8262 Option 1.
The definition of tolerate is such that the device will not trigger any alarms (LOS, OOF, LOL) while locked to such
an input clock and it will be able to pull-in to such an input clock.
3.1.1 Input and Output Parameters 10 MHz GPS Reference Locked to Anue Box
25 MHz Input to DUT Generated from Anue Box
Input File: G.8262_Table8_TDEV_Opt1.1c.txt (Input from Figure 5 of the G.8262 spec)
25 MHz Output from DUT Measured into BNC3 on Anue Box
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
3.1.2 Requirement Compliance ITU-T G.8262 Section 9.1.1 Option 1
Si5347-WanderToleranceOption1.slabtimeproj
Si5346-WanderToleranceOption1.slabtimeproj
Figure 15: Input Wander Tolerance Profile from Figure 5 G.8262 Table 8 for Option 1
3.1.3 RESULTS Si5347: PASS No alarms (LOL, LOS, or OOF) on the Si5347 were asserted during the file playback process for wander
tolerance for Option1.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 23 of 49
3.2 Wander Tolerance G.8262 Option 2 (Done with 2.2) A PLL that is locked to an input clock must be able to tolerate the wander defined in (Figure 8 Table 10 Option2
G.8262). The definition of tolerate is such that the device will not trigger any alarms (LOS, OOF, LOL) while
locked to such an input clock and it will be able to pull-in to such an input clock.
3.2.1 Input and Output Parameters 10 MHz GPS Reference Locked to Anue Box
25 MHz Input to DUT Generated from Anue Box
Input File: G.8262_Table10_TDEV_Opt2.1c.txt (Input from Figure 8 of the G.8262 spec)
25 MHz Output from DUT Measured into BNC3 on Anue Box
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
3.2.2 Requirement Compliance ITU-T G.8262 Section 9.1.2 Option 2
Si5347-WanderTransferOption2.slabtimeproj
Si5346-WanderTransferOption2.slabtimeproj
Figure 16: Input Wander Tolerance TDEV Mask, which must not trigger any LOL or LOS or OOF Alarms
3.2.3 RESULTS Si5347: PASS No alarms (LOL, LOS, or OOF) on the Si5347 were asserted during the file playback process for wander
tolerance for Option2.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 24 of 49
4 Jitter Tolerance
Equipment
Windows 7 PC, Running ClockBuilder Pro
Agilent Digital Oscilloscope: DSO9104A
Agilent 33250 Signal Generator
Agilent 53131A Frequency Counter
DUT: Si5347
TCXO: Rakon 513872 RTX Series
4.1 Jitter Tolerance G.8262 Option 1 and Option 2 A PLL that is locked to an input clock must be able to tolerate the jitter defined in Figure 9/G.8262 and Figure
10/G.8262. The definition of tolerate is that the device will not trigger any alarms (LOS, OOF, LOL) while locked
to such an input clock and it will be able to pull-in to such an input clock. Option 1 the DUT is set up with 1-10Hz
loop BW. Option 2 the DUT is set up with 0.1 Hz loop BW frequency.
4.1.1 Input and Output Parameters 25 MHz Input to DUT Generated from Agilent Signal Generator with FM modulation
25 MHz Output from DUT Measured on Frequency Counter and Scope
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
Si534x
2
IN0 XA/XB
TCXO
IN1 . .
Agilent 33250 25MHz Generator with
FM modulation
OUT0 OUT0B
IN2 IN3
Agilent Scope
PC
25MHz
25MHz
Agilent 53131A Frequency Counter (Connected to Sym
8040 Ref)
Figure 17: Test Set-up Jitter Tolerance
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 25 of 49
4.1.2 Requirement Compliance ITU-T G.8262 Section 9.2.1 (EEC Option 1 & 2)
Si5347-JitterToleranceOption1.slabtimeproj
Si5347-JitterToleranceOption2.slabtimeproj
Si5346-JitterToleranceOption1.slabtimeproj
Si5346-JitterToleranceOption2.slabtimeproj
Figure 18: Jitter Tolerance 1G limit mask
Figure 19: Jitter Tolerance 10G limit mask.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 26 of 49
4.1.3 RESULTS Si5347 EEC Option 1: PASS
Figure 20:Si5347 1G SyncE EEC Option 1 Jitter Tolerance Results.
Figure 21:Si5347 10G SyncE EEC Option 1 Jitter Tolerance Results
The measured results are shown by the blue trace. They are intended to be above the orange trace
representing the 8262 mask.
The results are the maximum input jitter before failure, however these values are largely limited by test
equipment, NOT by the device.
1
10
100
1000
10000
1 10 100 1000 10000 100000
p-p
Jit
ter
(UI)
Modulation Frequency (Hz)
Si5347 1G SyncE Jitter Tolerance for Option 1
4Hz BW 1G Mask
1
10
100
1000
10000
100000
1 10 100 1000 10000 100000
p-p
Jit
ter
(UI)
Modulation Frequency (Hz)
Si5347 10G SyncE Jitter Tolerance for Option 1
4Hz BW 10G Mask
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 27 of 49
4.1.4 RESULTS Si5347 EEC Option 2: PASS
Figure 22:Si5347 1G SyncE EEC Option 2 Jitter Tolerance Results.
Figure 23:Si5347 10G SyncE EEC Option 2 Jitter Tolerance Results
The measured results are shown by the blue trace. They are intended to be above the orange trace
representing the 8262 mask.
The results are the maximum input jitter before failure, however these values are largely limited by test
equipment, NOT by the device.
1
10
100
1000
10000
1 10 100 1000 10000 100000
p-p
Jit
ter
(UI)
Modulation Frequency (Hz)
Si5347 1G SyncE Jitter Tolerance for Option 2
100mHz BW 1G Mask
1
10
100
1000
10000
100000
1 10 100 1000 10000 100000
p-p
Jit
ter
(UI)
Modulation Frequency (Hz)
Si5347 10G SyncE Jitter Tolerance for Option 2
100mHz BW 10G Mask
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 28 of 49
5 Phase Transient Generation
5.1 Short Term Phase Transient Response G.8262 Option 1 The device is forced into holdover for 15 seconds by performing a manual switch from a valid active clock input
(IN0) to another input with no valid signal (IN1), then the holdover state is exited by manually switching back to
the valid active clock input. The test is completed after an entry into holdover and exit from holdover has taken
place within 15 seconds. The output phase variation, relative to the input reference before it was lost, is
bounded by the following requirements:
The phase error should not exceed ∆t + 5 x 10-8 x S seconds over any period S up to 15 seconds. ∆t represents
two phase jumps that may occur during the transition into and out of the holdover state which both should not
exceed 120 ns with a temporary frequency offset of no more than 7.5 ppm. The resultant overall requirement
is summarized in figure 12/G.8262. This figure is intended to depict the worst case phase movement
attributable to an EEC reference clock switch.
Figure 24: Short Term Phase Transient Test Setup.
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
Buffer
Agilent Digital Oscilloscope: DSO9104A
Power Supply for Buffer: Agilent E3620A (3.3V input)
DUT: Si5347
TCXO: Rakon 513872 RTX Series
Si534x
2
IN0
TCXO
XA/XB
ANUE 3500 BOX
3 2 1 LCD Screen S
IN1 OUT0 OUT0B
IN2
PC
25MHz
OUT1
25MHz Buffer
IN3
Agilent Scope
OUT1B 25MHz
BNC Connect 10MHz Reference 10 MHz
S 4 Ethernet Connection
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 29 of 49
5.1.1 Input and Output Parameters 25 MHz Input to DUT from Buffer into IN0 (IN1 Enabled, but no Input present)
25 MHz Output from DUT Measured on Anue BNC3
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
5.1.2 Requirement Compliance ITU-T G.8262 Section 11.1.1
Si5347-ShortTermPhaseTransientOption1.slabtimeproj
Si5346-ShortTermPhaseTransientOption1.slabtimeproj
Figure 25: Phase Transient Option 1 Limit Mask
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 30 of 49
5.1.3 RESULTS Si5347: PASS
Figure 26: Si5347 Short Term Phase Transient Option 1 Results.
- - - MTIE Option 1 LIMIT
MTIE Option 1 Si5347 Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 31 of 49
5.2 Short Term Phase Transient Response G.8262 Option 2 The device is forced into holdover for 15 seconds by performing a manual switch from a valid active clock input
(IN0) to another input with no valid signal (IN1), then the holdover state is exited by manually switching back to
the valid active clock input. The test is completed after an entry into holdover and exit from holdover has taken
place within 15 seconds. The output will not exceed the MTIE requirement of figure 14/G.8262.
The same equipment set up as 5.1) Short Term Phase Transient Response G.8262 Option 1 is used.
5.2.1 Input and Output Parameters 25 MHz Input to DUT from Buffer into IN0 (IN1 Enabled, but no Input present)
25 MHz Output from DUT Measured on Anue BNC3
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
5.2.2 Requirement Compliance ITU-T G.8262 Section 11.1.2
ITU-T G.8262 Section 11.4.2
Si5347-ShortTermPhaseTransientOption2.slabtimeproj
Si5346-ShortTermPhaseTransientOption2.slabtimeproj
Figure 27: MTIE Output Limit Mask due to Reference Switching Option 2
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 32 of 49
5.2.3 RESULTS Si5347: PASS
Figure 28: Si5347 Short Term Phase Transient Option 2 Results.
- - - MTIE Option 1 LIMIT
MTIE Option 1 Si5347 Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 33 of 49
5.3 Phase Transient Generation w/ Signal Interruptions G.8262 EEC Option1 An input interruption that does not force a switchover will not cause an output phase transient greater than
120ns with a maximum frequency offset of 7.5ppm in a period of 16ms.
There will be only 1 input in this case. An input interruption is created using the “Antritsu MP1632A
digital data analyzer” and will be used to generate delays in the input signal.
The signal will be stretched as far as possible to the limit of the switchover and then the output phase
transient will be measured to ensure that it is not greater than 120ns in length and the frequency offset
is not greater than 7.5ppm over a 16ms period.
Figure 29: Phase Transient Generation w/ Signal Interruptions Option 1 Test Set-Up
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
Balun
Antritsu MP1632A/ or Clock Gapper with Signal Generator (Agilent 33250)
DUT: Si5347
TCXO: Rakon 513872 RTX Series
5.3.1 Input and Output Parameters 24.987792 MHz Input to DUT Generated from BERT or Clock Gapper into IN0
25 MHz Output from DUT Measured on Anue BNC3
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
Si534x
2
3
IN0
ANUE 3500 BOX
XA/XB
TCXO
2 1 LCD Screen S
S 4
BNC Connect
IN1
10MHz Reference
OUT0 OUT0B
IN2 IN3
Ethernet Connection
PC
25MHz
OUT1B OUT1
Balun
25MHz Antritsu
MP1632A
10 MHz
Figure 29: Phase Transient Generation w/ Signal Interruptions Option 1 Test Set-Up.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 34 of 49
5.3.2 Requirement Compliance ITU-T G.8262 Section 11.3.1 Option 1
Si5347-ShortTermPhaseTransientOption1.slabtimeproj
Si5346-ShortTermPhaseTransientOption1.slabtimeproj
5.3.3 RESULTS Si5347: PASS
Figure 30: Si5347 Clock Gap Interruptions MTIE measurement Option 1
For this test, EEC Option 2 does not have requirements as it is listed for further study in the ITU-T
G.8262 standard.
- - - MTIE Option 1 LIMIT
MTIE Option 1 Si5347 Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 35 of 49
5.4 Phase Discontinuity G.8262 Option 1 Switching between two input clocks of the same frequency but with different phase (up to 62.5us) will not
cause an output phase transient greater than what is outlined in section 11.4.1 of G.8262.
There will be two inputs that are 180 degrees out of phase going into the DUT. The idea is to switch
between the two inputs with a phase difference of 62.5us.
The output will be measured to ensure that the objective in Figure 12 is still met.
Automated loop in VB to loop switching the inputs with a 10 second delay.
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
Buffer
Agilent 33250 Signal Generator
DUT: Si5347
TCXO: Rakon 513872 RTX Series
Si534x
2
3
IN0
ANUE 3500 BOX
XA/XB
TCXO
2 1 LCD Screen S
S 4
BNC Connect
IN1
10MHz Reference
OUT0 OUT0B
IN2 IN3
Ethernet Connection
PC
8kHz
OUT1B OUT1
25MHz 8kHz
Agilent 33250 Signal Generator
Buffer
Agilent Scope
Figure 31: Test Set-up Phase Transient Generation
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 36 of 49
5.4.1 Input and Output Parameters 8kHz Input to DUT Generated from Agilent Signal Generator on IN0 and 180° out of phase IN1
Hitless Switching Enabled
25 MHz Output from DUT Measured on Anue BNC3
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
5.4.2 Requirement Compliance ITU-T G.8262 Section 11.4.1
Si5347-PhaseDiscontinuityOption1.slabtimeproj
Si5346-PhaseDiscontinuityOption1.slabtimeproj
5.4.3 RESULTS Si5347: PASS
Figure 32: Si5347 Phase Discontinuity Option 1 Results
- - - MTIE Option 1 LIMIT
MTIE Option 1 Si5347 Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 37 of 49
5.5 Phase Discontinuity G.8262 Option 2 Switching between two input clocks of the same frequency but with different phase (up to 62.5us) will not
exceed the MTIE mask of figure 14/G.8262 (table 15 option 2).
The same equipment set up as 5.4) Phase Discontinuity G.8262 Option 1 is used.
5.5.1 Input and Output Parameters 8kHz Input to DUT Generated from Agilent Signal Generator on IN0 and 180° out of phase IN1
Hitless Switching Enabled
25 MHz Output from DUT Measured on Anue BNC3
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
5.5.2 Requirement Compliance ITU-T G.8262 Section 11.1.2
ITU-T G.8262 Section 11.4.2
Si5347-PhaseDiscontinuityOption2.slabtimeproj
Si5346-PhaseDiscontinuityOption2.slabtimeproj
Figure 33: MTIE Output Limit Mask due to Reference Switching Option 2
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 38 of 49
5.5.3 RESULTS Si5347: PASS
Figure 34: Si5347 Phase Discontinuity Option 2 Results
- - - MTIE Option 2 LIMIT
MTIE Option 2 Si5347 Result
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 39 of 49
6 Holdover
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
Buffer
Agilent Digital Oscilloscope: DSO9104A
Power Supply for Buffer: Agilent E3620A (3.3V input)
DUT: Si5347
TCXO: Rakon 513872 RTX Series
Si534x
2
IN0
TCXO
XA/XB
ANUE 3500 BOX
3 2 1 LCD Screen S
IN1 OUT0 OUT0B
IN2
PC
25MHz
OUT1
25MHz Buffer
IN3
Agilent Scope
OUT1B 25MHz
BNC Connect 10MHz
Reference 10 MHz
S 4 Ethernet Connection
Figure 35: Holdover Test Set-Up
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 40 of 49
6.1 Holdover G.8262 Option 1 A PLL in holdover will meet the requirements in figure 13 G.8262. The DUT obtains lock from IN0, which
contains a valid input clock. Then the input is switched to IN1, which contains no valid input, thus entering
holdover and remains in holdover for the remainder of the test.
6.1.1 Input and Output Parameters 25 MHz Input to DUT from Buffer into IN0 (IN1 Enabled, but no Input present)
25 MHz Output from DUT Measured on Anue BNC3
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 1: 4 Hz Loop Bandwidth Setting on the DUT
6.1.2 Requirement Compliance ITU-T G.8262 Section 11.2.1
Si5347-HoldoverOption1.slabtimeproj
Si5346-HoldoverOption1.slabtimeproj
Figure 36: Holdover Compliance Specification G.8262 Option 1
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 41 of 49
6.1.3 RESULTS Si5347: PASS
Figure 37: Si5347 Option1 Holdover MTIE Results
MTIE Option 1 Si5347 Result
- - -MTIE Option 1 Limit Mask
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 42 of 49
6.2 Holdover G.8262 Option 2 A PLL in holdover will meet the requirements in table 14 G.8262. The DUT obtains lock from IN0, which
contains a valid input clock. Then the input is switched to IN1, which contains no valid input, thus entering
holdover and remains in holdover for the remainder of the test.
6.2.1 Input and Output Parameters 25 MHz Input to DUT from Buffer into IN0 (IN1 Enabled, but no Input present)
25 MHz Output from DUT Measured on Anue BNC3
Rakon 513872 RTX Series Reference Frequency: 40 MHz
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
6.2.2 Requirement Compliance ITU-T G.8262 Section 11.2.2
Si5347-HoldoverOption2.slabtimeproj
Si5346-HoldoverOption2.slabtimeproj
Figure 38: Holdover Requirements Specifications G.8262 Option 2
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 43 of 49
6.2.3 RESULTS Si5347: PASS
Figure 39: Si5347 Option 2 Holdover MTIE Results
MTIE Option 2 Si5347 Result
- - -MTIE Option 2 Limit Mask
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 44 of 49
7 Free-run Accuracy
Figure 40: Frequency Accuracy Test Set-Up
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
DUT: Si5347
Agilent 53132A Universal Counter
Agilent 33250 Signal Generator
Si534x
IN0 XA/XB
IN1 . .
OUT0 OUT0B
IN2 IN3
PC
40MHz
Frequency Generator +/-4.6ppm
10MHz
Frequency Counter
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 45 of 49
7.1 Free-run Accuracy G.8262 Option 1 and Option 2 The free-run frequency will never exceed +/- 4.6ppm with reference to a traceable Stratum-1 reference. This
includes initial power-up or whenever there wasn’t enough holdover history accumulated.
7.1.1 Input and Output Parameters 40 MHz Output from DUT Measured on Frequency Counter
40 MHz Input from Frequency Generator to XA/XB pins
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
G.8262 Option 1: 4Hz Loop Bandwidth Setting on the DUT
7.1.2 Requirement Compliance ITU-T G.8262 Section 6.1 (Option 1)
ITU-T G.8262 Section 6.2 (Option 2)
Si5347-FreerunOption1.slabtimeproj
Si5347-FreerunOption2.slabtimeproj
Si5346-FreerunOption1.slabtimeproj
Si5346-FreerunOption2.slabtimeproj
7.1.3 RESULTS Si5347: PASS
Test Conditions External XO Input Output
Si5347 Option 1 40 MHz +4.6ppm 40.000184 MHz
Si5347 Option 1 40 MHz -4.6ppm 39.999816 MHz
Si5347 Option 2 40 MHz +4.6ppm 40.000184 MHz
Si5347 Option 2 40 MHz -4.6ppm 39.999816 MHz Table 1: Si5347 Free-run Accuracy Results
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 46 of 49
8 Pull-in/Hold-in
Figure 41: Pull-In/Hold-In Test Set-Up
Equipment
Anue 3500 Box
GPS 10 MHz Connection Link
Windows 7 PC, Running ClockBuilder Pro
DUT: Si5347
Agilent 53132A Universal Counter
Agilent 33250 Signal Generator
8.1 Pull-in Range G.8262 Option 1 and Option 2 A PLL which is in free-run or holdover within its +/- 4.6 ppm frequency range (based on its TCXO/OCXO) will be
able to pull-in to a reference that is within +/- 4.6 ppm frequency (traceable to Stratum-1). In other words the
PLL should be able to pull-in a minimum of +/- 9.2 ppm. Confirm no alarms are asserted.
8.1.1 Input and Output Parameters 40 MHz Input to DUT from Frequency Generator
40 MHz input from Frequency Generator to XA/XB pins
40 MHz output from DUT
G.8262 Option 2: 0.1 Hz Loop Bandwidth Setting on the DUT
G.8262 Option 1: 4Hz Loop Bandwidth Setting on the DUT
Si534x
IN0 XA/XB
IN1 . .
Frequency Generator +/-4.6ppm OUT0
OUT0B IN2 IN3
PC
40 MHz
Frequency Generator +/-4.6ppm
10MHz
40 MHz
40 MHz Frequency
Counter
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 47 of 49
8.1.2 Requirement Compliance ITU-T G.8262 Section 7.1.1 (Option 1)
ITU-T G.8262 Section 7.1.2 (Option 2)
Si5347-PullinOption1.slabtimeproj
Si5347-PullinOption2.slabtimeproj
Si5346-PullinOption1.slabtimeproj
Si5346-PullinOption2.slabtimeproj
8.1.3 RESULTS Si5347: PASS
Si5347 Option 1
Input External XO Output
-4.6ppm IN0 +4.6ppm XAXB 39.999816 MHz (-4.6ppm)
+4.6ppm IN0 -4.6ppm XAXB 40.000184 MHz (+4.6ppm)
-4.6ppm IN0 -4.6ppm XAXB 39.999816 MHz (-4.6ppm)
+4.6ppm IN0 +4.6ppm XAXB 40.000184 MHz (+4.6ppm)
Si5347 Option 2
Input External XO Output
-4.6ppm IN0 +4.6ppm XAXB 39.999816 MHz (-4.6ppm)
+4.6ppm IN0 -4.6ppm XAXB 40.000184 MHz (+4.6ppm)
-4.6ppm IN0 -4.6ppm XAXB 39.999816 MHz (-4.6ppm)
+4.6ppm IN0 +4.6ppm XAXB 40.000184 MHz (+4.6ppm) Table 2: Pull-In/Hold-In Results for the Si5347
*For all tests above, no alarms were asserted.
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 48 of 49
9 Conclusion
The Si5346 and Si5347 are high performance jitter attenuating clock multipliers which can generate any output
frequency from any frequency within its input and output frequency range. The Si5346 and Si5347 provide the
entire functionality required for SyncE applications and includes the following key features:
Programmable loop bandwidth, which can be set to EEC Option 1 or EEC Option 2
Hitless Switching
A suite of loss of lock alarms
Full compatibility with the free Silicon Labs ClockBuilder Pro software
Wander filtering
The Si5346 and Si5347, along with a compliant TCXO or OCXO, fully meets the requirements set in ITU-T
G.8262/Y.1362 (07/2010) and Amendment 2 (10/2012).
Rev. 1.0, 19-November-2014 Copyright © 2014 by Silicon Laboratories Page 49 of 49
Revision History
Rev Change Description Date
1.0 Initial External Release November 2014
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