lab 0 design flow
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8/7/2019 LAB 0 Design Flow
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Xi l inx Design Flow
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The IIn tegra ted SSo f t w a r e EEnv i ronment
Advanced Design Advanced Design
TechniquesTechniquesGNU Embedded Tools
Wind River Xilinx Edition
Embedded Development KitIMPACT
System ACE Configuration
Manager
Verif ication TechnologiesVerif ication TechnologiesModelSim XilinxEdition
Static Timing Analyzer
ChipScopePro
XPower power estimation
Formal Verification support3rd Party HDL simulation
ChipViewer
FPGA Editor with Probe
HDL Bencher testbenchgenerator
Design EntryDesign EntryHDL Edit and Entry
System Generator for DSP
CORE IP Generator
Architecture Wizards
ECS Schematic Editor StateCADState Diagram Editor
RTL Checker
SynthesisSynthesisSynplicity Synplify and Synplify Pro
Synplicity Amplify physical synthesis
MentorGraphics LeonardoSpectrum
Mentor Graphics Precision RTLphysical synthesis
SynopsysFPGA Compiler II
Xilinx Synthesis Technology (XST)
ImplementationImplementationFloorplanner and PACE
Constraints Editor
Timing Driven Place & Route
Modular Design
Incremental DesignTiming Improvement Wizard
Board Level IntegrationBoard Level IntegrationIBIS Models
STAMP Models
LMG Smart Models
HSPICE Models
One solution for all your logic design needs
3rd party partner tools
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Translate
Map
Place & Route
Xil inx Design Flow
Plan & Budget HDL RTL
Simulation
Synthesize
to create netlist
Functional
Simulation
Create
Bit File
Attain Timing
Closure
Timing
Simulation
Implement
Create Code/
Schematic
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Creat ing a Pro jec t
Select File New Project
New Project Wizard guides
you through
the processProject name
and location
Target device
Software flowCreate or add source
files
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Creat ing and Adding
Sourc e Fi les
To include an exist ing source file,
double-click Add Existing Source
To create a new source fi le,
double-click Create New Sourceand choose the type of file
HDL fi le
IP
SchematicState diagram
Testbench
Constraints file
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Text Entry
Color coding helps you quickly
understand and enter the design
Blue = Reserved w ordsPink = Signal type
G reen = Com m ents
Black = U ser input
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Language Tem plates
Tw o m ethods to open tem plates:Language Icon
Edit -> Language Tem plates
Language Tem plates provide com m on
tem plates for designs:
Com ponent instantiation
Language tem plates
Synthesis tem plates
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Schem atic Source File
Files w ith .sch extension
Selecting this source type
w ill open the ECS (Engineering
Capture System ) schem atic editor
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O ptions and Sym bols
Com ponents are divided into
categories
Exact sym bols are located in the
Sym bol boxSym bol N am e Filter for easier
search
O rientation
Rotate 0, 90,180, 270
M irror and rotate 0, 90, 180,
270
The O ptions tab selections
change, depending on
w hich function is selected
For exam ple, if you areadding a net nam e, the net
nam e options would be
show n
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Files w ith .dia extension
Selecting this surce type
w ill invoke StateCA D
State D iagram Source
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Imp lement a t ion St a tus
ISE will run all of the necessary steps
to implement the design
Synthesize HDL codeTranslate
Map
Place & Route
Progress and status are indicated by iconsGreen check mark ( ) indicates that the process
was completed successfully
Yellow exclamation point ( ! ) indicates warnings
Yellow question mark ( ? ) indicates a file that isout of date
Red “ X” indicates errors
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Sim ulat ing a Design
To simulate a design:
In the Sources in Project window,
select a testbench file
In the Processes for Source window,
expand ModelSim Simulator
Double-click Simulate
Behavioral Model or
Simulate Post-Place & Route
Model• Can also simulate after Translate
or after Map
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Sub-Processes
Each process can be expanded to view
sub-tools and sub-processes
Translate
• Floorplan
• Assign Package Pins
Map
• Analyze timing
Place & Route
• Analyze timing
• Floorplan
• FPGA Editor
• Analyze power
• Create simulation model
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Progr am t he FPGA
There are two ways to program an
FPGA
Through a PROM device
• You will need to generate a file
that the PROM programmer willunderstand
Directly from the computer
• Use the iMPACTconfiguration tool
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ISE 6.1i is designed and tested to run with the leading HDL simulators in the
industry
Cadence NC-Sim
Model Technology ModelSim
Synopsys VCS-MX and Scirocco
All Xilinx libraries and netlists conform to IEEE VHDL-93, VITAL-2000 and Verilog-
2001 standards
Other simulators are available to perform Xilinx CPLD and FPGA verification
3rd Party Simulation Integration
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3rd Par t y Synt hes is In tegrat ion
Synplify/Pro 7.3.1 Ability to use the parity bit in Virtex™-II, Virtex-II Pro™, and Spartan™-3
devices to optimize Block RAM implementations
Improved area optimization for Virtex-II, Virtex-II Pro, and Spartan-3 devices
Precision 2003bSupport Virtex-E/-II/-II Pro, Spartan-II/-IIE/-3
Advanced design analysis
LeonardoSpectrum 2003bSupport Spartan-3 family
FCII v3.8Support for Spartan-3 devices
Support for all Virtex-II Pro devices
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Sim ulation Tool
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Sim ulation in the FPG A Environm ent
Gate Level Simulation
HDL GateTiming
HDL GateTiming
Place & Route
HDL GateFunctional
Synthesis
HDLRTL
Design Entry
VITAL orVerilog
SimulationLibrary
RTLSimulation
FunctionalSimulation
RTL Sim ulation
H ighest perform ance
M any spins
• highest throughput
Functional Sim ulation
• D oes function m atch R TL G olden
m odel
G ate Level Sim ulation
• H ighest im pact on sim ulation run tim e
• Full tim ing
• D oes function m atch R TL G oldenm odel
Source Tem plates andW izards, H D S, IPX ,X ilinx LogiCO RE,
CO RE G enerator
M odelSim
Leonardo Spectrum
X ilinx ISE
M odelSim
M odelSim
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H D L Bencher
Creates tim ing constrained
V H D L and V erilog
self-checking testbenches
N o know ledge of
H D L or scripting required
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Create a N ew Source
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Create a N ew Source
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H D L Bencher
U nit under test is analyzed, w henselected
Port problem s
Syntax violations
Inconsistencies
D esign tim ing selected
Clocked or com binatorial?
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Create W aveform s
D ata values
1, 0 ,X ,Z, U
A ssignm ents
D ouble-click bit signal to toggle value
Pattern w izard assigns a range of cell values
W aveTable assign signals like a spreadsheet
By default, decim al values are show n in the W aveTable
W aveform values are checked as they are enteredV alidation check for non-binary inputs only (for exam ple, hex, or decim al)
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Toggling
Toggling bit values is the easiest w ay to assign bit signals
Sim ply click directly on the signal’s w aveform at the tim e w here changes shouldtake place
Click directly on these boxes, at the tim e
w here signals should toggle
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Pattern W izard
A ids com plex w aveform input
To access, click a signal at the tim e it should be changed to access value cell editor
N ote: light blue background = input assignm ent,light yellow background = output assignm ent
Click in this area Click here for Pattern W izard
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Pattern W izard
A vailable patterns
Pattern description
Changes depending on the
pattern selected
Count unit in clock cycles
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Testbench
W aveform file extensions are TBW
W aveform file can be seen in the Sources in
Project w indow of the Project N avigator
To view testbench:
In Sources in Project W indow , select the TBW file
Then in the Processes for Current Source w indow ,click V iew Behavioral Testbench
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M odelsim In ISE
TestBench type code
Sim ulation process
p A nsw erRecordsH its
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p A nsw er Records H its
#15338: H ow do I com pile sim ulation M odels
#16233: BlockRA M Collision Errors
#10629: W hat are $setup and $hold violations
#15501: H ow do I install Sm artM odels?
#6537: H ow do I use the glbl.v file for V erilog?#15969: U sing the ASY N C_REG constraint
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CORE Generat or
What are Cores?
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What are Cores?
A core is a ready-made function that you can instantiate into your design as a“ black box”
Cores can range in complexity
Simple arithmetic operators, such as adders, accumulators, and multipliers
System-level building blocks, including filters, transforms, and memories
Specialized functions, such as bus interfaces, controllers, and microprocessors
Some cores can be customized
Sam ple Func t ions
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Sam ple Func t ions
LogiCORE solutions
DSP functions
• Time skew buffers, FIR filters,
correlators
Math functions
• Accumulators, adders, multipliers,
integrators, square root
Memories
• Pipelined delay elements, single
and dual-port RAM• Synchronous FIFOs
PCI master and s lave interfaces, PCI
bridge
AllianceCORE solutions
Peripherals
• DMA controllers
• Programmable interrupt controllers• UARTs
Communications and networking
• ATM
• Reed-Solomon encoders / decoders
• T1 framers
Standard bus interfaces
• PCMCIA, USB
I k i t h CORE G t S t
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Invok ing t he CORE Generat or Syst em
From the Project Navigator, selectProject→ New Source
Select IP (CoreGen& Architecture
Wizard) and enter a fi lename
Click Next, then select the type of
core
Xi l inx CORE Generat or Syst em GUI
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Xi l inx CORE Genera t or Sys t em GUI
Cores can be organized by function,vendor, or device family
Core type, version, device
support, vendor, and status
Core Cust om ize Window
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Core Cust om ize Window
Parameters
tab allows you to customize the core
Contact tab provides information about the vendor
Data sheet
access
Web Links tab provides direct access to related
Web pages
Core Overview tab provides version information and a brief functional description
CORE Dat a Sheet s
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CORE Dat a Sheet s
Performance expectations (not
shown)
Features
Functionality
Pinout
Resource utilization
Arch i t ec t ure Wizard
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Architecture Wizard containstwo wizards:
Clocking Wizard
RocketIO Wizard
Double-click Create New
Source
Select IP (CoreGen& Architecture
Wizard),
then click Next• ExpandClocking and
select desired function
• Expand I/O Interfaces
and select RocketIO*
DCM Wizard --Genera l Set up Opt ions
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DCM Wizard --Genera l Set up Opt ions
Select which pins are required
Define attr ibutes:
Input Clock FrequencyCLKIN Source
Divide By Value
Feedback Source
Feedback ValueDuty Cycle Correction
Phase Shift (DPS)
DCM Wizard – DFS set t ing
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g
Frequency synthesizer
Select M / D value
OR
Specify frequency
“ Calculate” button for jitter
Period jit ter is evaluated for CLKFX output
Note: This dialog appears only if the
CLKFX output was selected
Where Can I Learn More?
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Xilinx IP Center http://www.xilinx.com/ipcenter Software updates
Download new cores as they are released
Tech Tips on http://support.xilinx.com
Software manuals: CORE Generator Guide
DCM constraints: Online Software Manuals → Constraints Guide
DCM architecture:
Virtex-II, Virtex-II Pro, Spartan-3 Data Sheets → Detailed Description
Virtex-II, Virtex-II Pro, Spartan-3 User Guides→ Design Considerations→ DCM
DCM timing parameters:Virtex-II, Virtex-II Pro, Spartan-3 Data Sheets → Electrical Characteristics
Virtex-II, Virtex-II Pro, Spartan-3 Interactive Data Sheets →http://support.xilinx.com/applications/web_ds/index_top.htm
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