lab 1 overview and microcode reviewcs152/sp16/sections/...• examples – found 20% of vax...
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Lab1OverviewandMicrocodeReview
Sec3on22/1/2016
Agenda
• Lab1– Whywe’reaskingyou?– Whatwe’vegivenyou?– Whatyou’reaskedtodo?
• MicrocodeReview• Miscellaneous(RISC-V,Chisel,etc.)Ques3ons
ComputerArchitect’sJob• Findthecommoncase(s),andmakesureyoucansupportthemefficiently– Some3mesatthecostofsupporttheuncommoncaseinefficiently
• Examples– Found20%ofVAXinstruc3onsresponsiblefor60%ofmicrocode,butonlyaccountfor0.2%ofexecu3on3me!
– Registerimmediateinstruc3ons• Howdoweknowwhattodo?– Intui3on,Simula3on,Building,Experiments,…
Experimentsaren’teasy
• Althoughthereareproper3esthatyoucanprovemathema3cally,computerarchitectureiso[enbasedonempiricalstudies
• Thismeansthatyourdatawillbeapplica3onspecific– Pickyourapplica3onscarefully!(benchmarks)
• “Itdepends”:Alwaysthinkaboutbothsidesoftheargument– Keepaskingques3onstoyourselftounderstand
Lab1
• Understandhowin-orderpipelinedmicroarchitectureaffectsprocessor
• Guided– CPI– Instruc3onMix
• Open-ended– Bypassing– CISCmicrocode– GeneralDesign– Yourfunidea!
Lab1Given• ProvidedRISC-V32Iprocessors– 1-stage– 2-stage– 3-stage– 5-stage
• Fullybypassed• Interlocked(stalltoresolveallhazards)
– Micro-coded• Only1-stageand5-stageareusedinthedirectedpor3on– 2-stage3-stageandmicro-codearethereforyoutoinves3gateoruseintheopen-endedpor3on
Lab1GivenotherMisc.
• Chisel->C++simulator(emulator)• Benchmarksandtestprograms• Instruc3onTracertogatherstats– CPI,instruc3onmix
• Ques3onsandanalysis– Makerecommenda3ons– Proposenewdesigns
Lab1ChiselProcessor
TileCore
CPath DPath
RAM
Lab1ProcessorEmulator
Emulator.cpp
Target System: Top-0.h Top-0.cc
TileCore
CPath DPath
RAMFESVR
DEMO!
• Addtoolstoyourpath$ source ~cs152/sp13/cs152.bashrc
• CopyLabFiles$ cp –R ~cs152/sp13/lab1 .
• BuildaChiselprocessor,Compilesimulator,runalltests&benchmarks$ make run-emulator
HowisChiselusedinLabChisel(
Lab1Ques3ons
Microcode/Lecture2Review
• Endianness• Combina3onalPath• Cri3calPath• BenefitsofMicrocode• HorizontalvsVeritcal• Nanocoding
DataFormatsandMemoryAddresses
14
Dataformats:8-bBytes,16-bHalfwords,32-bwordsand64-bdoublewords
Someissues• Byteaddressing
• WordalignmentSupposethememoryisorganizedin32-bitwords.Canawordaddressbeginonlyat0,4,8,....?
0 1 2 3 4 5 6 7
MostSignificantByte
LeastSignificantByte
ByteAddresses
3 2 1 0
0 1 2 3BigEndian
Li8leEndian(RISC-V)
PerformanceIssues
15
Microprogrammedcontrol=>mul3plecyclesperinstruc3on
Cycle3me?tC>max(treg-reg,tALU,tμROM)
Suppose10*tμROM<tRAM
Goodperformance,relaDvetoasingle-cyclehardwiredimplementaDon,canbeachievedevenwithaCPIof10
CycleTime,Combina3onalPath,Cri3calPath
1
IR A B
RegWr enReg
MemWr enMem
MA
addr addr
data data
rs rs11 rd 32(PC)
RegSel
busy? zero?
ALUOp
Opcode
ldIR ldA ldB ldMA
IntRq
Memory 32 GPRs +
PC + IRA + ...
(32-bit regs) ALU
enALU
Immed Select
enImm
ImmSel
Bus
HorizontalvsVer3calµCode
• Horizontalµcodehaswiderµinstruc3ons– Mul3pleparallelopera3onsperµinstruc3on– Fewermicrocodestepspermacroinstruc3on– Sparserencoding⇒morebits
• Ver3calµcodehasnarrowerµinstruc3ons– Typicallyasingledatapathopera3onperµinstruc3on
– separateµinstruc3onforbranches– Moremicrocodestepspermacroinstruc3on– Morecompact⇒lessbits
• Nanocoding– Triestocombinebestofhorizontalandver3calµcode
17
#µInstruc3ons
BitsperµInstruc3on
Nanocoding
18
• MC68000had17-bitµcodecontainingeither10-bitµjumpor9-bitnanoinstruc3onpointer– Nanoinstruc3onswere68bitswide,decodedtogive196controlsignals
µcodeROM
nanoaddress
µcodenext-state
µaddress
μPC(state)
nanoinstruc3onROMdata
Exploitsrecurringcontrolsignalpa}ernsinµcode,e.g.,ALU0 A<=Reg[rs1]...ALUi0 A<=Reg[rs1]...
Ques3ons
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