lascas 2020 – 11th ieee latin american symposium on circuits … · 2020-01-29 · where the cas...
Post on 30-May-2020
5 Views
Preview:
TRANSCRIPT
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
1
http://www.ieee-lascas.org
LASCAS 2020 11th IEEE Latin American Symposium on Circuits and Systems
San José, Costa Rica
February 25-28, 2020
Preliminary Program: LASCAS, LAEDC, PRIME-LA, & Iberchip http://www.ieee-lascas.org
|
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
2
http://www.ieee-lascas.org
About LASCAS
The Latin America Symposium on Circuits and Systems is the flagship conference of the IEEE Circuits and Systems Society in Latin America. Since its first edition in 2010, LASCAS provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. This event is a space where the CAS community can present new concepts and innovative approaches, learn about new trends and solutions, and receive feedback from specialists in diverse fields. The 11th edition will take place in San José, the capital of Costa Rica. This time, the venue is the Hotel Holiday in Plaza Tempo, Escazú. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.
Co-Hosted Events
The Latin America Electron Device Conference (LAEDC), in its second edition, is an event cosponsored by
the IEEE Electron Device society. Its main goal is to bring together specialists from all Electron
Device related fields.
The PhD Research in Microelectronics and Electronics Conference in Latin America (PRIME-LA) is
a conference where PhD students and post-docs with less than one-year post-PhD experience can
present their research results and network with experts from industry, academia and research.
The Iberchip workshop provides an annual forum to academic and industrial researchers from
Iberoamerican countries in which to exchange experiences, share knowledge, and establish
relations to foster the development of activities related to the field of microelectronics. Special
emphasis is put in the improvement of education and training, and in the promotion of joint
cooperative projects.
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
3
http://www.ieee-lascas.org
Preliminary Program: LASCAS, LAEDC, PRIME-LA, & Iberchip
Day I – Tuesday, 25th February, 2020
13:00 – 17:00 Registration
8:30 –
10:00
Tutorial 1:
Open
Hardware
SiFive Tech
Symposium
CASS Student
Activity
LASCAS
Committee
Meeting
LAEDC: EDS
Minicolloquium
10:00 –
10:30 Coffee Break
10:30 –
13:00
Tutorial 2:
Reliability
SiFive Tech
Symposium
CASS Student
Activity
LASCAS
Committee
Meeting
LAEDC: EDS
Minicolloquium
13:00 –
14:30 Lunch
14:30 –
16:30
Tutorial 3: Bio-
Fuel-Cell
SiFive Tech
Symposium
CASS Student
Activity
Steering
Committee
Meeting
LAEDC:
MOS-AK on
Compact
Modeling
16:30 –
17:00 Coffee Break
17:00 –
18:30
Workshop:
Aruba CX
CASS Student
Activity
Steering
Committee
Meeting
LAEDC: MOS-
AK on Compact
Modeling
19:00 –
21:00
Welcome Cocktail
Tutorial 1: An Introduction to Open Source Hardware Development Leveraging Open Source Software
Workflows. Diego Dompe, Laura Salazar, and José Walter Orozco. Aruba Networks. Costa Rica.
In this tutorial will review the current state of the art in Open Source Hardware development, as well as
discuss the challenges and potential benefits of it in academic and commercial environments. We will map
learnings and methodologies from Open Source Software development into the Open Source Hardware
development while providing practical examples of how to apply this knowledge.
Aqcua 1 Aqcua 2 Aqcua 3 Terra 3
Terra 2 Terra 1
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
4
http://www.ieee-lascas.org
Tutorial 2: Reliability of Nanoscale Semiconductor Devices, focusing on but not limited to Noise and
Bias Temperature Instability. Gilson Wirth, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil.
Effects that play a major role on the reliability of today digital and analog designs are discussed, as well as
effects that are expected to become relevant in future technologies. Modeling techniques to abstract the
physical level effects into the design flow are studied. The main focus of the tutorial will be charge capture
and emission by defects (traps) close to the Dielectric-Semiconductor interface is known to be the major
source of low-frequency noise in modern MOS devices. It is also known to play a role in Bias Temperature
Instability (BTI). The basics mechanisms involved in charge trapping and de-trapping will be presented,
including a critical discussion of key parameters such as trapping/de-trapping time constants and the
amplitude of the fluctuations induced by single traps. We introduced a new variability-based analysis,
employing the autocorrelation of multiple LF-Noise spectra in terms of parameters such as frequency, bias
and temperature. This technique reveals information about the mechanisms responsible for the LF-noise
(and BTI) that is difficult to obtain otherwise. The talk is focused on nano scale MOS devices, but novel
devices such as Resistive Switching Memory (RRAM/ReRAM) are also addressed.
Tutorial 3: Bio-Fuel-Cell-Operated Biosensing System: Fundamental and Forecast. Kiichi Niitsu, Nagoya
University, Japan.
Ensuring stable energy is one of the most important current challenges in wearable and implantable biomedical IoT systems. For addressing this issue, many developments with respect to batteries, wireless power delivery, and energy harvesting have been reported. Among them, one of the promising candidates is an introduction of bio fuel cells because it can be used as both power sources and sensing transducer. In this tutorial, the fundamental and forecast of the bio-fuel-cell-operated biosensing systems will be presented.
Workshop: ArubaCX & Network Analytics Engine: A real automated network. José Luis Uribe, Aruba
Networks.
Network engineers face challenges when managing and maintaining the networks they operate. These
challenges range from delivering new capabilities to ensuring the network is always available to support
their business. Addressing the demands of high availability requires better visibility and tools for
troubleshooting, root cause analysis and diagnostics. To meet these needs, Aruba has an industry-leading
portfolio of switches for the campus network. In particular, Aruba developed the Network Analytics Engine
(NAE) as part of the ArubaOS-CX network operating system. With a fully programmable and database-
driven design, only ArubaOS-CX is capable of supporting the advanced visibility enabled by the NAE.
SiFive Tech Symposium
Attendees will learn about the RISC-V ecosystem, and the SaaS-based approach that is enabling fast access
to the custom cores, design platforms, and custom SoC solutions for emerging applications. There will also
be a hands-on workshop where attendees will have the unique opportunity to configure their own RISC-
V core and bring up on an FPGA.
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
5
http://www.ieee-lascas.org
Agenda:
Welcome and Introduction, by Swamy Irrinki, Sr. Director of Marketing, SiFive.
RISC-V History and State of the Union Video, by Krste Asanovic, Chairman of the RISC-V Foundation
& Chief Architect at SiFive.
Keynote: How the RISC-V ISA is Opening Exciting Opportunities, by Gerardo Bertero, CTO, Western
Digital.
Keynote: Leading the Semiconductor Design Revolution, by Swamy Irrinki, Sr. Director of
Marketing, SiFive.
RISC-V Core IP for Target Vertical Markets, by John Min, Director, FAE/CX, SiFive.
RISC-V Software Ecosystem, by John Min, Director, FAE/CX, SiFive.
RISC-V Core IP Debug & Bare Metal Software, by Kevin Mills, Debug & Trace Engineer, SiFive.
SiFive University Platform, by Swamy Irrinki, Sr. Director of Marketing, SiFive.
Workshop (Laptop Required): Configure Custom RISC-V Core and Bring up on FPGA, by John Min
& Kevin Mills, SiFive.
Closing Remarks, by Swamy Irrinki, Sr. Director of Marketing, SiFive.
Attendance to this event is free, but the number of seats is limited.
Welcome Cocktail
Join us for this welcome activity at the lobby of the Hotel Holiday Inn.
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
6
http://www.ieee-lascas.org
Preliminary Program: LASCAS, LAEDC, PRIME-LA, & Iberchip
Day II – Wednesday, 26th February, 2020
7:00 – 8:00 Registration
8:00 – 8:30 Opening Ceremony
8:30 – 10:00
Special Session I:
Power and Signal
Integrity
Analog and
Mixed Signal
Circuit Design I
Imaging
Techniques Iberchip
Session I
(LAEDC)
10:00 – 10:30 Coffee Break Demo 1
10:30 – 11:30
Keynote: Dr. Vida Ilderem
Director of Integrated Platform Research, VP Intel Labs.
“Integrated Platform Research”
11:30 – 13:00 Lunch Break
13:00 – 14:00
Keynote: Dr. Shihab Shamma
Professor, University of Maryland.
“Cognitive and Computational Neuroscience”
14:00– 15:00
Keynote: Jesus A. del Alamo
Massachusetts Institute of Technology.
“Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs”
15:00 – 16:00 Coffee Break IP 1 IP 2 (LAEDC)
16:00 – 17:30
Analog and Mixed
Signal Circuit
Design II
Digital Circuits
and Systems I Sensors
Digital Signal
Processing
Session II
(LAEDC)
17:30 – 19:00
WiCAS Event, invited Speakers:
Rahima Mohammed, SPE Intel
Michelle Johnson, U. Pennsylvania
Session III
(LAEDC) PRIME –LA
Session IV
(LAEDC)
19:00 – 21:00 WiCAS Dinner
Vento Aqcua 1 Aqcua 2 Aqcua 3
Terra 5 Terra 1
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
7
http://www.ieee-lascas.org
LASCAS Special Session I: Signal and Power Integrity
Chair: Dr. Ram Achar, Carleton University, Canada.
SS1-1 Majid Ahadi Dolatsara and Madhavan
Swaminathan
Determining worst-case eye height in low BER channels using Bayesian
optimization
SS1-2 Srinidhi Ganeshan, Naveen Kumar
Elumalai, and Ramachandra Achar
A Comparative Study of MAGMA and cuBLAS Libraries for GPU based
Vector Fitting
SS1-3 Xinying Wang, Thong Nguyen, and Jose
E. Schutt-Aine
PAM-4 Behavioral Modeling using Machine Learning via Laguerre-
Volterra Expansion
SS1-4 José E. Rayas-Sánchez, Francisco E.
Rangel-Patiño, Benjamin Mercado-
Casillas, Felipe Leal-Romo, and José L.
Chávez-Hurtado
Machine Learning Techniques and Space Mapping Approaches to
Enhance Signal and Power Integrity in High-Speed Links and Power
Delivery Networks
LASCAS Session: Analog and Mixed Signal Design I
AMS1-1 Daniel Schrögendorfer, Thomas
Leitner, and Harald Pretl
A 1.2V, 1.1-dB NF, CMOS Low-Noise Amplifier using an Active-Tank
Broadband Output Stage
AMS1-2 Arnaldo del Risco Sánchez, Robson
Luiz Moreno, Luís Henrique de
Carvalho Ferreira, Paulo César
Crepaldi, and Tales Cleber Pimenta
A minimum supply voltage Operational Transconductance Amplifier
for wireless biomedical acquisition systems
AMS1-3 Mahmood Mohammed and Gordon
Roberts
The Impact of the Scaled-Down CMOS Technologies on the Step
Response Degradation Caused by the Pole-Zero Doublets in the OTAs
AMS1-4 David Rivadeneira, Marco Villegas,
Luis Procel and Lionel Trojman
Optimization of active voltage rectifier/Doubler designed in 90nm
technology
AMS1-5 Leonardo Agis, Denisse Hardy, Kenji
Nakasone, Joel Gak, Matias Miguez,
Ronny García-Ramírez, Alfonso
Chacon-Rodriguez, Renato Rimolo-
Donadio, and Alfredo Arnaud
Integrated Programmable Current Source for Implantable Medical
Devices
LASCAS Session: Imaging Techniques
IT1-1 Ícaro Siqueira, Guilherme Corrêa, and
Mateus Grellert
Rate-Distortion and Complexity Comparison of HEVC and VVC Video
Encoders
IT1-2 Jan-Harm Betting, Vincenzo Romano,
Laurens Bosman, Zaid Al-Ars, Chris De
Zeeuw, and Christos Strydis
Stairway to Abstraction: an Iterative Algorithm for Whisker Detection
in Video Frames
IT1-3 Vinicius Borges, Murilo Perleberg,
Vladimir Afonso, Marcelo Porto, and
Luciano Agostini
A Low-Complexity Algorithm and Its Low-Power and High-Throughput
Architecture for 3D-HEVC DMM-1 Encoding Tool
IT1-4 Ryota Ishikawa, Masashi Tawada,
Masao Yanagisawa, and Nozomu
Togawa
Multi-Resolutional Image Format Using Stochastic Numbers and Its
Hardware Implementation
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
8
http://www.ieee-lascas.org
IT1-5 Eduardo Zummach, Roberta Palau,
Jones Goebel, Luciano Agostini, and
Marcelo Porto
High Throughput CDEF Architecture for the AV1 Decoder Targeting
4K@60fps Videos
Iberchip Workshop
IB-1 Anibal Fukamati and Eduardo Lima. Modelagem Comportamental de Amplificadores de Potência
Utilizando Cascata de Dois Polinômios com Memória
IB-2
Gracieth Batista, Duarte Oliveira,
Diego Silva, Osamu Saotome, and
Leonardo Romano
FPGA Implementation of Support Vector Machine Classifier in
Automatic Speech Recognition System
IB-3
Duarte Oliveira, Nicolly Cardoso,
Gracieth Batista, Diego Silva, and
Leonardo Romano
Asynchronous Register Files for Low-Power Digital Systems Based on
FPGA
IB-4 Duarte Oliveira, Diego Silva, Gracieth
Batista, and Leonardo Romano Systematic Approach for Design of Low-Power Robust Flip-Flops
IB-5
Keynote Speaker:
Dr. Vida Ilderem, VP Intel Labs, Director of Integrated Platform Research
Talk: Integrated Platform Research Challenges
More information coming soon…
Keynote Speaker:
Prof. Shihab Shamma, University of Maryland. Cognitive and Computational Neuroscience
Talk: How Auditory Cortical Representations Inspire Speech and Music Processing Systems
The brain is a complex information processing system that is difficult to comprehend following any one experimental
and theoretical approach. Instead, it has yielded fascinating insights only when diverse techniques were applied to
its study. The remarkable capabilities of the brain has also inspired enormous interest in replicating them in
Neuromorphic hardware and software so as both to derive insights into and also benefit from replicating its
functionality. In this talk, I will address these topics focusing on the case of the auditory system and its applications
to audio processing and recognition of speech, music, and the relevance of these applications to the understanding
of language and music in the brain.
LASCAS Session: Interactive Presentations I
IP1-1 Carlos Sanabria, Mónico Linares-
Aranda, Rogelio Higuera and Francisco
Javier De la Hidalga Wade
Impact and Modeling of Möbius Connection in the Rotary Traveling
Wave Oscillator Performance
IP1-2 Walter Gil, Oscar Danilo Montoya
Giraldo, Alejandro Garces and Andrés
Herrera-Orozco
PI-PBC Approach for Voltage Regulation in Cuk Converters with
Adaptive Load Estimation
IP1-3 Md Adnan Zaman, Rajeev Joshi and
Srinivas Katkoori
Analysis of Radiation Impact on Memristive Crossbar Arrays
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
9
http://www.ieee-lascas.org
IP1-4 Estevan Lima and Sibilla França Hardware Implementation of True Random Number Generators
Based on Oscillator Rings
IP1-5 Wilmer Ramirez, Marco Sarmiento
and Elkim Roa
A Flexible Debugger for a RISC-V Based 32-bit System-on-Chip
1P1-6 Tiago Mallmann Rohde and João
Baptista dos Santos Martins
New Error Correct Code Technique for Multi-Bit-Upset Errors in
Memory
LASCAS Session: Analog and Mixed Signal Design II
AMS2-1 Siamak Delshadpour A 0.7 µw Explicit Bandgap Less POR Circuit With Brownout Detection
AMS2-2 Rolando Torres, Luis Rueda, Nestor
Cuevas and Elkim Roa
On the Design of Reliable and Accurate Current References
AMS2-3 Oscar Jair Cinco Izquierdo, Maria
Teresa Sanz Pascual, Carlos Aristoteles
De la Cruz Blas and Belen Calvo Lopez
Low Power CMOS Chopper Preamplifier Based on a Source-
Degeneration Transconductors
AMS2-4 Sudipta Saha, Shoba Krishnan and
Allen A Sweet
A triple mode wide locking range, low phase noise injection locked
oscillator based phase shifter covering the Sub-6 GHz 5G bands
AMS2-5 Johan Solis Arbustini, Pablo Mendoza
Ponce, Wolfgang H. Krautschneider
and Matthias Kuhl
A 16-bit pressure sensing interface integrating a 460 fJ/conv
Incremental Sigma Delta ADC for medical devices
LASCAS Session: Digital Circuits and Systems I
DCS1-1 Henrique Seidel, Morgana Macedo
Azevedo da Rosa, Guilherme Paim,
Eduardo da Costa, Sergio Almeida and
Sergio Bampi
Energy-Efficient Haar Transform Architectures Using Efficient Addition
Schemes
DCS1-2 Esteban Garzón, Benjamin Zambrano,
Tatiana Moposita, Ramiro Taco, Luis-
Miguel Prócel and Lionel Trojman
Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-
Memory Applications
DCS1-3 Richard Calusdian and Aaron
Stillmaker
Hardware Implementation of HEVC Inverse Transform in 45nm CMOS
DCS1-4 Akhilesh G. Naik, Debarshi Deka and
Dipankar Pal
ASIC Implementation of High-Speed Adaptive Recursive Karatsuba
Multiplier with Square-Root-Carry-Select-Adder
DCS1-5 Duarte Oliveira, Gabriel Duarte,
Gracieth Batista, Diego Silva and
Leonardo Romano
Synthesis of Asynchronous State Machines from Synchronous
Specifications
LASCAS Session: Sensors
S1-1
Roman Fragasse, Ramy Tantawy,
Shane Smith, Teressa Specht, Zahra
Taghipour, Phillip Van Hooser,
Christopher Taylor, Theodore
Ronningen, Earl Fuller, Rudy Fink,
Sanjay Krishna and Waleed Khalil
Advancing Uncooled Infrared Imagers Using An Open-Circuit Voltage
Pixel
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
10
http://www.ieee-lascas.org
S1-2 Kota Mizushima, Satomi Ogawa and
Takahide Sato
A High-Accuracy Capacitance-to-Voltage Converter for Capacitive
Sensors
S1-3
Andry Contreras, Leonardo Steinfeld,
Mariana Siniscalchi, Javier Schandy
and Benigno Rodríguez
A Rectenna as Energy Source for Wireless Sensor Nodes
S1-4
Alexandre de Jesus Aragão, Dionísio
de Carvalho, Bruno Sanches and
Wilhelmus Adrianus Maria Van Noije
An improved confocal algorithm for breast cancer detection using
UWB signals
S1-5 Diego Deotti, Jose Luis Ramirez
Bohorquez and Fabiano Fruett Design and characterization of a Smart Temperature sensor
LASCAS Session: Digital Signal Processing
DSP1-1
Daniel Massicotte, Marwan Jaber,
Chokri Neili and Messaoud Ahmed
Ouameur
FPGA Implementation for the Multiplexed and Pipelined Building
Blocks of Higher Radix-2^k FFT
DSP1-2 Kaya Demir and Salih Ergün Analysis of Random Number Generators Based on Chaos-Modulated
Dual Oscillator Architecture
DSP1-3 Matheus Mitsuo De Almeida Kotaki
and Maximiliam Luppe
FPGA Implementation of a Pseudorandom Number Generator Based
on k – Logistic Map
DSP1-4 Burak Acar and Salih Ergün A Robust Digital Random Number Generator Based on Transient
Effect of Ring Oscillator
DSP1-5
Jakub Podivinsky, Ondrej Cekan,
Martin Krcma, Radek Burget, Tomas
Hruska and Zdenek Kotasek
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection
Determination
DSP1-6 Jai Gopal Pandey, Sanskriti Gupta and
Abhijit Karmakar
A Unified Architecture for AES/PRESENT Ciphers and its Usage in an
SoC Environment
Women in CAS Event (WiCAS)
Invited Speakers:
Dr. Rahima Mohammed, Senior Principal Engineer, Intel.
Dr. Michelle Johnson, U. Pennsylvania.
WiCAS Dinner
More information coming soon…
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
11
http://www.ieee-lascas.org
PRIME-LA
PRIME-1
Carlos Salazar-García, Jefferson
González-Gómez, Ronny García-
Ramírez, Kaleb Alfaro-Badilla, Renato
Rimolo-Donadio, Christos Strydis, and
Alfonso Chacon-Rodriguez
PlasticNet: A low latency flexible network architecture for
interconnected multi-FPGA systems
PRIME-2 Maximiliano Chiossi, and Matíaz
Míguez Low-power activity recognition from triaxial accelerometer data
PRIME-3 William Medeiros, Hamilton Klimach
and Sergio Bampi
Ultra-Low Power Relaxation Oscillation Survey: Design Trends and
Challanges
PRIME-4
Ronny García-Ramírez, Alfonso
Chacon-Rodriguez and Renato Rimolo-
Donadio
Pre-Silicon Evaluation of Digital Bus Micro-Architectures
PRIME-5
Roberto Carlos Molina Robles, Alfonso
Chacon-Rodriguez, Ronny García-
Ramírez, Renato Rimolo-Donadio,
Edgar Solera-Bolanos and Alfredo
Arnaud
A compact functional verification flow for a RISC-V 32I based core
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
12
http://www.ieee-lascas.org
Preliminary Program: LASCAS, LAEDC, PRIME-LA, & Iberchip
Day III – Thursday, 27th February, 2020
8:30 – 10:00
Special Session
2: Affordable
Technology
Systems for
Rehabilitation…
Analog and
Mixed Signal
Circuit
Design III
Digital Circuits
and Systems II
Artificial
Intelligence
Session V
(LAEDC)
10:00 – 10:30 Coffee Break Demo 2
10:30 – 11:30
Keynote: Dr. Sayfe Kiaei
Arizona State University
“Overview of 5G Radio Systems, Requirements, Challenges, and Research Areas”
11:30 – 13:00 Lunch Break
13:00 – 14:00
Keynote: Dr. David Atienza
Professor, Swiss Federal Institute of Technology
“Energy-Scalable Many-Core Servers: Follow Your Brain!”
14:00– 15:30
Invited Speakers:
Kevin Boyum, HPE Silicon Lab
“Memory Driven Computing”
Gerardo A. Bertero, Western Digital
“RISC-V ISA Opportunities for Storage and Memory”
Session VI
(LAEDC)
Session VII
(LAEDC)
15:30 – 16:00 Coffee Break IP 3
16:00 – 17:30 Industrial Forum
Moderator: Victor Grimblatt, Synopsys.
Session VIII
(LAEDC)
Session IX
(LAEDC)
17:30 – 22:00
Gala Dinner
Vento Aqcua 1 Aqcua 2 Aqcua 3
Terra 5 Terra 1
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
13
http://www.ieee-lascas.org
LASCAS Special Session: REHAB-CAS:
Affordable Technology Systems for Rehabilitation in Low and Middle-Income Countries
Chair: Dr. Michelle Johnson. University of Pennsylvania
RH1-1 Beatriz Coto-Solano Challenges in the Translation and Implementation of Rehabilitation
Technology to Public Health in Costa Rica
RH1-2 Samuel Gaardsmoe, Maria Ovando,
Kevin Bui, and Michelle J. Johnson
Development of a low-cost balance assessment system for use in an
affordable robot gym in low and middle income countries
RH1-3 K. Bustamante Valles, D. Comaduran,
R. Galindo, and Michelle J. Johnson
Robotic Rehabilitation Therapy in Chihuahua Mexico, challenges from
translating a clinical research protocol to clinical practice
RH1-4 Verónica Valverde-Arredondo, Arys
Carrasquilla-Batista
Haptic system for upper limb rehabilitation with hand grip strength
measurements and Internet of Things capabilities
RH1-5
Karol Quiros-Espinoza, Carla Gomez-
Carrasquilla, y Arys Carrasquilla-
Batista
Wheelchair control through eye blinking and IoT platform
LASCAS Session: Analog and Mixed Signal Design III
AMS3-1 Pablo Mendoza Ponce, Gayas
Mohiuddin Sayed, Lait Abu Saleh,
Wolfgang Krautschneider and
Matthias Kuhl
A 1.9 nW Timer and Clock Generation Unit for Low Data-Rate
Implantable Medical Devices
AMS3-2 Eduardo Vilela Pinto dos Anjos,
Dominique M. M.-P. Schreurs and Guy
A. E. Vandenbosch
Phase-Control Techniques for Sub-Sampling Phase-Locked Loops
AMS3-3 Nader El-Zarif, Mohamed Ali, Ahmad
Hassan, Morteza Nabavi, Christian
Jesus B. Fayomi and Yvon Savaria
A High Efficiency and Fast Response PLL Based Buck Converter:
Implementation and Simulation
AMS3-4 Juan Andrés Bozzo, Angel Abusleme
and José Silva-Martínez
A blind calibration scheme for switched-capacitor pipeline analog-to-
digital converters
AMS3-5 Yulang Feng, Qingjun Fan, Hao Deng,
Runxi Zhang, Phaneendra Bikkina,
Esko Mikkola and Jinghong Chen
An Automatic Comparator Offset Calibration for High-Speed Flash
ADCs in FDSOI CMOS Technology
LASCAS Session: Digital Circuits and Systems II
DCS2-1 Patrícia Ücker, Miguel Weirich,
Guilherme Paim, Eduardo Antônio
César da Costa and Sergio Bampi
Optimizing Iterative-based Dividers for an Efficient Natural Logarithm
Operator Design
DCS2-2 Rodrigo Wuerdig, Vitor Lima, Filipe
Baumgratz, Rafael Soares and Sergio
Bampi
Evaluating Cell Library Sizing Methodologies for Ultra-Low Power
Near-Threshold Operation in Bulk CMOS
DCS2-3 Furat Alobaidy, Arghavan Asad and
Farah Mohammadi
An Efficient Power Consumption using Hybrid Emerging Memory
Technology for 3D CMPs
DCS2-4 Juliano Cavinato Zanelli, Carolina
Metzler and Ricardo Reis
Gate Sizing for Power-Delay Optimization at Transistor-level
Monolithic 3D-Integrated Circuits
DCS2-5 Jose Somarribas Escalante and Adrian
Loteanu
Using Micro-Processor Vector Instructions to Optimize Unsupervised
Machine Learning K-Means Algorithm
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
14
http://www.ieee-lascas.org
LASCAS Session: Artificial Intelligence
AI1-1 Jorge Castro-Godínez, Deykel
Hernández-Araya, Muhammad
Shafique and Jörg Henkel
Approximate Acceleration for CNN-based Applications on IoT Edge
Devices
AI1-2 Brunno F Goldstein, Sudarshan
Srinivasan, Dipankar Das, Kunal
Banerjee, Leandro Santiago,
Victor C. Ferreira, Alexandre S.
Nery, Sandip Kundu and Felipe
M. G. França
Reliability Evaluation of Compressed Deep Learning Models
AI1-3 Mingxin Zhao, Xuemin Zheng,
Ke Ning, Chunhe Yao, Qian Luo,
Shuangming Yu, Liyuan Liu and
Nanjian Wu
A verification method for array-based vision chip using a fixed-point
neural network simulation tool
AI1-4 Lenin Torres-Valverde, Nevrez
Imamoglu, Antonio González-
Torres, Toru Kouyama and
Atsunori Kanemura
Evaluation of neural networks with data quantization in low power
consumption devices
AI1-5 Mohamed El-Sharkawy and
Sree Bala Bhamidi
3-Level Residual Capsule Network
Keynote Speaker:
Prof. Dr. Sayfe Kiaei, Arizona State University.
Talk: Overview of 5G Radio Systems, Requirements, Challenges, and Research Areas.
As demand grows for wireless connectivity in many applications including autonomous vehicles, artificial intelligence,
telemedicine and virtual reality will have a dominate role in 5G. 5G will be delivering higher data throughput,
extremely low latency and speeds up to 100 times faster than 4G. This talk will give an overview of the 5G
technology, standards, and challenges for RF and wireless transceivers. The talk will focus on the RF architecture and
transceivers for the 5G RF front-end.
Keynote Speaker:
Prof. Dr. David Atienza, Swiss Federal Institute of Technology
Talk: Energy-Scalable Many-Core Servers: Follow your Brain!
Continuous advances in manufacturing technologies are enabling the development of more powerful and compact
high-performance computing (HPC) servers made of many-core processing architectures. However, this soaring
demand for computing power in the last years has grown faster than semiconductor technology evolution can
sustain, and has produced as collateral undesirable effect a surge in power consumption and heat density in these
new HPC servers, which result on significant performance degradation.
In this talk, Prof. Atienza will advocate to completely revise the current practices to design HPC server architectures.
In particular, inspired by the mammalian brain, I propose to design a disruptive three-dimensional (3D) computing
server architecture that overcomes the prevailing worst-case power and cooling provisioning paradigm for servers.
This new 3D server design champions a new system-level thermal modeling and machine learning based task
assignment (developed in cooperation with Facebook), which can be used by novel proactive energy controllers for
detailed heat and energy management in many-core HPC servers, thanks to micro-scale liquid cooling. Then, it will
be shown the impact of new near-threshold computing architectures on many-core server design. Finally, I will
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
15
http://www.ieee-lascas.org
explain how we can integrate new on-chip microfluidic fuel cell networks to enable energy-scalability in future
generations of many-core HPC servers targeting the next-generation of Exascale computing, thanks to the new
PowerCool and Gem5-X open-source multi-core architectural simulators.
LASCAS Session: Interactive Presentations II
IP3-1 David Pollreisz and Nima
Taherinejad
Reliable Respiratory Rate Extraction using PPG
IP3-2 Thomas Fontanari, Guilherme
Paim, Leandro Rocha, Patrícia
Ücker, Eduardo Costa and
Sergio Bampi
An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry
Propagation Delay
IP3-3 William Medeiros, Hamilton
Klimach and Sergio Bampi
A 42 nW 32.5 kHz CMOS Relaxation Oscillator with Comparator Offset
Cancellation for Ultra-Low Power applications
IP3-4 Lesley Ferreira, Mateus
Moreira, Bárbara Souza,
Sandro Ferreira, Filipe
Baumgratz and Sergio Bampi
Review on the Evolution of Low-power and Highly-linear Time-to-
Digital Converters - TDC
IP3-5 Luis D. Murillo-Soto and Carlos
Meza Benavides
Faults detection in a solar array based on an efficiency threshold
Invited Speaker:
Kevin Boyum, HPE Silicon Design Lab, USA
Talk: Memory-Driven Computing.
Big Data is here, growing, and sourcing tremendous unrealized business opportunities! Yet, as the number of data
sources and the amount of data gathered continues to increase exponentially, transistor scaling and the
corresponding increase in compute ability has slowed dramatically, reducing our ability to interact with this mounting
data in a meaningful timeframe. Hewlett Packard Enterprise has met this challenge with an entirely new approach
called Memory-Driven Computing. Designed specifically for Big Data, Memory-Driven Computing turns traditional
computer architecture on its head by making memory central to the system, rather than processors. This
presentation explores the fundamental principles and building blocks of Memory-Driven Computing and how it
differs from conventional design, then highlights examples of the incredible speedups achieved so far on real-world
workloads.
Invited Speaker:
Gerardo Bertero, CTO Western Digital, USA.
Talk: How the RISC-V ISA is Opening Exciting Opportunities for Novel Storage and Memory Architectures.
By Gerardo Bertero, Ted Marena, Celeste Cooper, Richard New.
For many years, digital storage and system memory had few things in common coexisting separately as two necessary
building blocks of traditional compute systems. With the rapid growth of NAND flash as a mass storage device and
the many options available for new non-volatility in memory, while still semantically different, there is less of a clear-
cut differentiation between the two. In this presentation, we will make a case for why a traditionally storage-centric
company sees the need to make incursions into memory, fabrics and CPU logic designs. We will discuss features of
our new family of open source SweRV processors, introduce an open standard for a cache coherent memory over an
Ethernet fabric and time permitting will introduce a recently proposed open standard for block storage products
called Zoned Storage.
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
16
http://www.ieee-lascas.org
Industrial Forum:
Moderator: Victor Grimblatt, Synopsys R&D Director, Chile.
More information coming soon…
Social Event: Gala Dinner.
Gran Hotel Costa Rica, Curio Collection by Hilton
Terrace Restaurant. San José Downtown. Transportation will be provided. Departure from Hotel Holiday Inn at 17:30.
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
17
http://www.ieee-lascas.org
Preliminary Program: LASCAS, LAEDC, PRIME-LA, & Iberchip
Day IV – Friday, 28th February, 2020
8:30 – 10:00
Special Session
3:
Neurotechnology
, …
Computer
Architecture I
Digital
Communications
Embedded
Systems
Session X
(LAEDC)
10:00 – 10:30 Coffee Break Demo 3
10:30 – 11:30
Keynote: Dr. Christian Schuster
Professor, Hamburg University of Technology
“Artificial Neural Networks for EMC Engineering”
11:30 – 13:00 Lunch Break
13:00 – 14:00
Keynote: Dr. Wouter Serdjin
Professor, Delft University of Technology.
“The Medicine of the Future You'll Take Only Once, and it is Bioelectronic”
14:00– 15:30
Naysen Robertson, HPE Silicon Design Labs
“An approach to generational, pre-silicon SoC/ASIC
Prototyping”
Marcelo Barú, Principal EE of Biotronik
“Electrochemistry of Stimulating Electrodes…”
Session XI
(LAEDC)
Session XII
(LAEDC)
15:30 – 16:00 Coffee Break IP (LAEDC)
16:00 – 17:30
Special Session
4: IoT in
Agribusiness
Electronic
Devices Filter Design
System
Simulation and
Test
Session XIII
(LAEDC)
17:30 – 18:00 Closing Ceremony
Vento Aqcua 1 Aqcua 2 Aqcua 3
Terra 5 Terra 1
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
18
http://www.ieee-lascas.org
LASCAS Special Session: Neurotechnology, Circuits and Systems Design Challenges
Chair: Dr. Fernando Silveira. Universidad de la República, Uruguay.
SS3-1 Alfredo Arnaud and Matías
Miguez
Stacking Multiple Differential Pairs for a NEF<1 Amplifier aimed at
Electroneurographic Signal Recording
SS3-2
Rui Guan, Pedro G. Zufiria,
Vasiliki Giagka, and Wouter A.
Serdijn
Circuit Design Considerations for Power-Efficient and Safe Implantable
Electrical Neurostimulators
SS3-3
Dorian Haci, Yan Liu, Sara S.
Ghoreishizadeh, and Timothy
G. Constandinou
Key Considerations for Power Management in Active Implantable
Medical Devices
SS3-4
Renzo Caballero, Gonzalo
Carozo, María C. Costa-
Rauschert, Pablo Aguirre,
Conrado Rossi-Aicardi and
Julián Oreggioni
Biopotential integrated preamplifier
LASCAS Session: Computer Architecture
CA1-1 Ernesto Rivera-Alvarado and
Francisco J. Torres-Rojas
An Efficient Workload Distribution Mechanism for Tightly Coupled
Heterogeneous Hardware
CA1-2
Ronny García-Ramírez, Alfonso
Chacon-Rodriguez, Renato
Rimolo-Donadio, Alfredo
Arnaud, Matias Miguez and
Joel Gak
A RISC-V based medical implantable SoC for high voltage and current
tissue stimulus
CA1-3
Jeferson González-Gómez,
Steven Ávila-Ardón, Jonathan
Rojas-González, Andrés
Stephen-Cantillano, Jorge
Castro-Godínez, Carlos Salazar-
García, Muhammad Shafique
and Jörg Henkel
TailoredCore: Generating Application-Specific RISC-V-based Cores
CA1-4
Ronny García-Ramírez, Alfredo
Arnaud, Joel Gak, Matias
Miguez, Alfonso Chacon-
Rodriguez and Renato Rimolo-
Donadio
SIWA: a RISC-V 32I based Micro-Controller for Medical Implantable
Applications
CA1-5
Jose Somarribas Escalante,
Esteban Meneses and Kimberly
Olivas
Predictive Power Consumption Model for Compute Intensive
Applications in Clustered ARM A53 Embedded Systems
LASCAS Session: Digital Communications
DC1-1
Luiz Claudio Sampaio Ramos,
Felipe Gonçalves Serrenho and
José Antonio Apolinário Junior
Least squares optimized Doppler effect-based DoA estimation
DC1-2 Siamak Delshadpour A PLL Based FSK Demodulator With Auxiliary Path
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
19
http://www.ieee-lascas.org
DC1-3 William De Carvalho Rodrigues
and José Antonio Apolinário Jr. An on-the-Fly FDOA-based Target Localization System
DC1-4
Andres Cornejo, Salvador
Landeros-Ayala, Jose M. Matias
and Ramon Martinez
Applying Learning Methods to Optimize the Ground Segment for HTS
Systems
DC1-5
Tales Pimenta, Samuel Moreira,
Francisco Portelinha Junior and
Romulo Volpato
Coexisting Analysis of 5G Networks with ISDB-T System in TV White
Spaces
LASCAS Session: Embedded Systems
ES1-1
Matheus Stigger, Victor Lima,
Leonardo Soares, Cláudio Diniz
and Sergio Bampi
Approximate SATD Hardware Accelerator Using the 8x8 Hadamard
Transform
ES1-2
Alfonso Chacon-Rodriguez,
Kaleb Alfaro-Badilla, Carlos
Meza Benavides, Ronny Zarate-
Ferreto and Carlos Salazar-
García
SoC-FPGA Implementation of a Temperature-Dependent Parameters
Estimator for Photovoltaic Generators
ES1-3
Andres Quesada-Martinez,
Javier Aparicio-Morales, Jose
Campos-Araya, Alfonso
Chacón-Rodríguez, Ronny
Garcia-Ramirez and Renato
Rimolo-Donadio
Evaluation of 8b/10b FPGA Encoder Implementations for SerDes
Links
ES1-4 Ruiqi Luo, Xiaolei Chen and
Yajun Ha
Optimization of FPGA Routing Networks with Time-Multiplexed
Interconnects
ES1-5
Deykel Hernández-Araya, Jorge
Castro-Godínez, Muhammad
Shafique and Jörg Henkel
AUGER: A Tool for Generating Approximate Arithmetic Circuits
Keynote Speaker:
Prof. Dr. Christian Schuster, Hamburg University of Technology, Germany.
Talk: Artificial Neural Networks for EMC Engineering
Artificial Neural Networks – in short: ANNs – are one of the many methods used nowadays in Machine Learning (ML).
Their fundamental development has spanned many decades and they have found widespread use in such areas as
image and speech recognition as well as autonomous driving. Despite this success, ANNs have not been applied
routinely to complex engineering task such as guaranteeing the Electromagnetic Compatibility (EMC) of electrical
and electronic components and systems. In this talk – a after a short, layman’s introduction into ML and ANNs – we
will look in some detail at the current state of art in the application of ANNs to EMC engineering including an example
from power delivery network design that we worked recently on at TUHH. A personal outlook will conclude the
presentation.
Keynote Speaker:
Prof. Dr. Wouter Serdjin, Delft University of Technology, The Netherlands.
Talk: The Medicine of the Future You'll Take Only Once, and it is Bioelectronic.
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
20
http://www.ieee-lascas.org
The 21st century will be the century in which we will unravel the intricacies of the brain and the rest of our nervous
system and in which we will learn how to interact with our electrochemical mainframe better by means of electricity,
light or ultrasound. Tiny electronic devices will give us back lost senses, lost control, bypass lesions and treat an
unprecedented range of brain disorders, thereby bringing back quality of life to the deaf, the blind, the paralyzed and
the mentally disturbed. This talk will address how these ‘bioelectronic medicines’ do this, what they look like and
which future circuit and system developments are needed to make them a reality. We will discuss their constraints
on size, their energy challenge, their adherence to the body and their security aspects. We will also discuss how to
make them truly personalized, so that they gracefully adapt to your therapeutic needs and you truly will feel better.
Invited Speaker:
Naysen Robertson, HPE Silicon Design Lab, USA.
Talk: An approach to generational, pre-silicon SoC/ASIC Prototyping.
A majority of organizations developing application-specific integrated circuit (ASIC) designs rely upon some form of
pre-silicon hardware to accelerate verification of their solutions beyond software based simulation/emulation.
Software simulation of silicon design is flexible and relatively low-cost, but executing micro-code and long dwell
simulation is time-prohibitive and incapable of capturing the parallel nature of synchronous designs. This leads to
verification misses at synchronization thresholds and other temporal flaws introduced in the register transfer level
(RTL) model. There is a continuum of hardware-based Design Verification solutions that ranges from simple, off-the-
shelf printed circuit assembly (PCA) cards with a programmable device to the high-cost, high-complexity emulation
boxes available from our premier Electronic Design Automation (EDA) vendors. At HPE, our approach to enabling an
ASIC equivalent prototyping solution that is cost, effort, and capability optimized involves the use of generational,
custom, field programmable gate array (FPGA)-based PCAs designed to load our Baseboard Management Controller
(BMC) ASIC design, execute WiP Firmware, and integrate within current generation server platforms that are
modified to detect and seamlessly connect previous or current generation ASIC }add-in cards as well as next-
generation FPGA-based cards to the host system. This presentation gives an overview of this approach to FPGA
accelerated ASIC validation with an analysis of the trade-offs with alternative approaches.
Invited Speaker:
Marcelo Barú, Principal EE of Biotronik.
Talk: “Electrochemistry of Stimulating Electrodes - Implications for Front-End System Design of
Implantable Neurostimulators”
Electrical current in a metal is carried by electron flow while in tissue is carried by ion migration. At the
electrode/electrolyte interface a conversion between charge-carriers occurs during stimulation. Designing safe and
more efficient implantable neurostimulators requires basic understanding and consideration of electrochemical
aspects that take place on a stimulating electrode inside the body. Further, commercial neurostimulators shall meet
tight electrical requirements for market clearance and adoption. Classical circuit design approaches to fulfill some of
these requirements (e.g. minimizing DC leakage) may force electrode potentials into regions where tissue may get
damaged or electrodes dissolved. In addition, traditional “equally” charged biphasic waveforms show that the second
pulse does not typically reverse the surface processes from the first pulse, given asymmetries in the electrochemical
situations under each waveform phase. This may also impact where the electrode potentials sit in steady-state
compromising safety. This talk will walk through key aspects in neurostimulator front-end system design from an
industry perspective, utilizing Spinal Cord Stimulation as use case but without losing generality, covering the
considerations mentioned above.
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
21
http://www.ieee-lascas.org
LASCAS Special Session: IoT in Agribussiness
Chair: Victor Grimblatt. Synopsys, Chile.
SS4-1
Laura Hernández-Alpizar, Arys
Carrasquilla-Batista, and Lilliana
Sancho-Chavarría
IoT application for water quality monitoring: nitrates
SS4-2 Alfredo Arnaud and Guillermo
Costa
Ultra low-cost sensors using RFID standards for data collection, for
IoT systems in food production and logistics.
SS4-3
Carlos Muñoz, Juan Huircan,
Fernando Huenupan, and
Pedro Cachaña
PTZ camera tuning for real time monitoring of cows in grazing fields
SS4-4 Victor Grimblatt IoT for Agribussiness: An Overview
LASCAS Session: Electronic Devices
ES1-1
Maximilian Reuter, Johannes
Pfau, Tillmann Krauss, Mahdi
Moradinasab, Udo Schwalke,
Jürgen Becker and Klaus
Hofmann
Towards Ambipolar Planar Devices: The DeFET Device in Area
Constrained XOR Applications
ES1-2
Oleg Dvornikov, Vladimir
Tchekhovski, Yaroslav Galkin,
Nikolay Prokopenko and Anna
Bugakova
The Research Methodology of Dependence Mode at Parameters
Dispersion of a Differential Pair on Integral JFETs in a Radiation-
Hardened Structured Array MH2XA010
ES1-3 Marina Sparvoli, Mario Gazziro
and Lucas Silvestre
Graphene oxide resistive memories with threshold switching
behavior
ES1-4
Zarin Tasnim Sandhie, Farid
Uddin Ahmed and Masud H.
Chowdhury
GNRFET based Ternary Logic – Prospects and Potential
Implementation
ES1-5 Arturo Sarmiento and Marco A.
Zamudio-Hernández
Image Edge Detection with a Memristive Grid: a Massive Parallel
Approach
LASCAS Session: Filter Design &
FD1-1 Bruno Sanches and Wilhelmus
Van Noije
A Radiation Tolerant Baseline Correction Filter for Readout Front-
ends in High Energy Physics Experiments
FD1-2 Ahmed Elgarewi, Iman Moazzen
and Panajotis Agathoklis
Analysis of Optimization Algorithms for Non-Uniform Filter Bank
Design
FD1-3 Venkata Suresh Rayudu, Heechai
Kang and Ranjit Gharpurey
An N-Path Filter with Multiphase PWM Clocks for Harmonic Response
Suppression
FD1-4 George Antoniou and
Constantine Coutras
A New 4D Lattice FIR Digital Filter
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
22
http://www.ieee-lascas.org
LASCAS Session: System Simulation and Test
SST1-1
Gabriel Madrigal-Boza, Marco
Oviedo-Hernández, Luis A.
Chavarría-Zamora, Allan
Carmona-Cruz, Daniel Leon-
Gamboa, Daniel Kohkemper-
Granados, Ronny Garcia-
Ramírez, Alfonso Chacon-
Rodriguez and Renato Rimolo-
Donadio
An IC Mixed-Signal Framework for Design, Optimization, and
Verification of High-Speed Links
SST1-1 Andres Malavasi Mora and
Renato Rimolo Donadio
Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data
Compensation
SST1-1
Jakub Podivinsky, Jakub Lojda,
Richard Panek, Ondrej Cekan,
Martin Krcma and Zdenek
Kotasek
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of
Smart Electronic Locks
SST1-1 Siamak Delshadpour A Type-C USB Power Delivery Chip Faced Catastrophic Failure
SST1-1
Eduardo Garcia, Enrique
Gonzalez-Garcia, Adolfo
Hernandez-Padilla, Raymundo
Aguillon and Paulo Lopez-Meyer
Thermal debugging tool for servers
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
23
http://www.ieee-lascas.org
11th Latin American Symposium on Circuits and Systems Committee:
IBERCHIP and PRIME-LA Technical Program Chairs
Dr. José Lipovetzky - Universidad Nacional de Río Negro, Argentina.
Dr. Martín Di Federico - Universidad Nacional del Sur, Argentina.
LAEDC Chairs
Mario Alemán (general), Arturo Escobosa (program), Luis Marall and Benjamñin Iñiguez (Technical).
Special Sessions & Tutorials Chairs
Dra. Arys Carrasquilla-Batista- TEC, Costa Rica.
M.Sc. Carlos Salazar-García - TEC, Costa Rica.
Publication Chairs
Dr. Carlos Meza-Benavides- TEC, Costa Rica.
Dr. Juan José Montero - TEC, Costa Rica.
Industry Liaison
Eng. Luis Carlos Rosales - Intel, Costa Rica.
M.S. José Walter Orozco - HPE/Aruba, Costa Rica.
Víctor Grimblatt - Synopsys Chile R&D Center, Chile.
Publicity Chairs
Prof. Dr. Ricardo Reis, UFRGS, Brasil
General Chairs:
Dr. Alfonso Chacón-Rodríguez – TEC, Costa Rica, alchacon@tec.ac.cr
Dr. Renato Rimolo-Donadio – TEC, Costa Rica, rrimolo@tec.ac.cr
Program Chairs:
Dr. Christos Strydis – Erasmus Medical Center, Netherlands
Dr. Alfredo Arnaud – Universidad Católica del Uruguay, Uruguay
LASCAS 2020 – 11th IEEE Latin American Symposium on Circuits and Systems
24
http://www.ieee-lascas.org
Event Sponsors Technical Co-sponsor and Organizer
Industrial Sponsors
Diamond
Platinum
Gold
Silver
top related