layout design analysis of sr flip flop using cmos technology

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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Layout Design Analysis of SR Flip Flop usingCMOS Technology

Avneet KaurDepartment of ECE, National Institute of Technical Teachers’ Training & Research, Chandigarh, India

avneetkaur.ak92@gmail.com

Abstract:- This paper presents an area, delay and powerefficient design of SR flip flop. As the chip manufacturingtechnology is on the threshold of evaluation, which shrinks achip in size and enhances its performance, here the flip flop isimplemented in a layout level which develops an optimizeddesign using recent CMOS layout tools. The proposed SR flipflop has been designed and simulated using 45nm technology.After that, parametric analysis has been done. In this paper,flip flop has been developed using full automatic design flowand semi-custom design flow. The performance of SR flip floplayouts using different design flows has been analyzed andcompared in terms of area, delay and power consumption.The simulation results show that the design of SR flip flopusing semi-custom design flow improved the area occupied by46.9% and power consumption is reduced by 38.4%.

Keywords: Bistable circuits, Latches, Flip flops, CMOSintegrated circuits, Design methodology

1. INTRODUCTIONA flip flop is an electronic circuit that has two stable statesand can be used to store information. The circuit can bemade to change its state by applying signals to one or morecontrol inputs and will have one or two outputs. Flip flopsare often used in computational circuits to operate inselected sequences during recurring clock intervals toreceive and maintain data for a limited period of timesufficient for other circuits within a system to furtherprocess data [1]. Thus, flip flops are the basic storageelements in a sequential logic circuit. Memory elementsplay a vital role in digital world and the basic memoryelements are latches and flip flops. These bistable circuitsare the basic building blocks of a data path structure. Theyallow for the storage of data processed by combinationalcircuits and synchronization of operation at a given clockfrequency [2]. For high performance chip design in VLSI,the choice of the back-end methodology has a significantimpact on the design time and the design cost. Latches andflip flops directly impact the power consumption and speedof VLSI systems [3]. The main improvement in terms offeature size reduction for CMOS integrated circuits isincreased number of metal interconnects to link MOSdevices together within the chip [4]. Also, in synchronoussystems, any violation of the timing constraints of the flipflops can cause the overall system to malfunction.Moreover, the process variations can create a largevariability in flip flop delays impacting the timing yield[5]. Flip flops have a wide area of applications such ascounters, shift registers and level shifters. A binarysynchronous counter is one of the essential building blocksin very large scale integration design. Its operation isusually based on a synchronous timing principle in whichthe data signal is evaluated at each clock cycle andassigned to its associated flip flop [6]. A counter is

designed by using a number of D registers. The D latch is asimple gated SR latch with an inverter connected betweenits S and R inputs [7]. Steady miniaturization of transistorswith each new generation of bulk CMOS technology hasyielded continual improvement in the performance ofdigital circuits. Thus, power efficiency if of increasedimportance, to meet the performance requirements of VLSIdesign [8]. Also, the leakage power increases astechnology is scaled down [9]. A tradeoff between speedand power is always possible. In high-performance andlow-power applications, both features are equallyimportant. The point of minimum power-delay product isthe point of optimal energy utilization at a given clockfrequency [10]. In this paper, area, delay and powerconsumption for an SR flip flop have been compared usingDSCH and Microwind tools. Basically, two types of designmethodologies have been compared, full automatic andsemi-custom. Both the designs are created using 45nmCMOS technology. The SR flip flop or the gated SR latchhaving a second level of AND gates along with a level ofdirect SR latch using NOR gates has been discussed in thepaper.

2. SR LATCHA latch is a circuit that has two stable states. Thus, it is abistable multivibrator. It can be used to store stateinformation. It is made up of several transistors and is usedin the design of static memories and hardware registers.When using static gates as building blocks, the mostcommonly used fundamental latch is the SR latch, where Sstands for set and R stands for reset. It can be constructedfrom a pair of cross-coupled NOR logic gates. The storedbit is represented on the output marked Q.

Figure 1. SR Latch

The truth table for a simple SR latch is shown in Table 1.Table 1. SR latch operation

R S Q Comment0 0 NC No change. Latch remains in

present state.

0 1 1 Set1 0 0 Reset1 1 0 Invalid condition

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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3. GATED SR LATCHA gated SR latch (clocked SR flip-flop) can be made byadding a level of AND gates to the SR latch.

Figure 2. Gated SR Latch

With E high (enable true), the signals can pass through theinput gates to the encapsulated latch, i.e. the latchis transparent. With E low (enable false) the latch is closed(opaque) and remains in the state it was left in when thelast time E was high. The enable input may be a clocksignal, but more often it is a read or write strobe.

Table 2. Gated SR latch operationE/C Action

0 No action (keep state)1 The same as non-clocked SR latch

The circuit shown in Figure 2 is now implemented usingDSCH. Figure 3 shows the schematic of SR flip flop attransistor level.

Figure 3. CMOS SR flip flop

4. LAYOUT DESIGN SIMULATIONSIn complex VLSI design, manual layout designing for avery complex circuit becomes very difficult. So, ascompared to the manual layout design, an automatic layoutgeneration approach is preferred. According to the fullautomatic design flow, the schematic implemented usingDSCH shown in Figure 3 is now compiled usingMicrowind. Compilation is done in 45nm technology.Figure 4 shows the automatically generated layout.

Figure 4. Full Automatic SR Flip Flop Layout

Figure 5 depicts the simulation result of the automaticallygenerated CMOS layout of SR flip flop.

Figure 5. Full Automatic Design Simulation

Here, the first type of design flow i.e. full automatic hasbeen completed. Now proceeding to the second type ofdesign flow i.e. semi-custom in which NMOS and PMOSdevices are generated using MOS generator option fromthe palette. In this, the layout is directly created usingMicrowind. The advantage of this approach is that designrule errors can be avoided. Figure 6 shows the semi-customdesign layout of SR flip flop. The proposed semi-customlayout of SR flip flop is also designed in 45nm technologyin Microwind. In the following layout, the design isoptimized by bringing the inverters and gates closer, inorder to minimize the length of the polysilicon gates.

Figure 6. Semi-Custom SR Flip Flop Layout

Now, Figure 7 shows that the simulation result of semi-custom generated layout design is similar to that ofautomatically generated design.

Figure 7. Semi-Custom Design Simulation

5. RESULT ANALYSISIn this paper, the SR flip flop has been implemented usingtwo different design methodologies. So, performancecomparison is as depicted by Table 3. The aspects onwhich the comparison is done are area, delay and powerconsumption.

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Table 3. Performance Comparison for SR Flip Flop

Aspect FullAutomatic

Design

Semi-CustomDesign

Area (µm2) 82.2 43.6

Delay (ps) 540 527

Power (µW) 2.440 1.501

The analysis of above comparison shows that the SR flipflop designed using semi-custom design flow has betterperformance. Area reduces by 46.9% and powerconsumption gets reduced to 38.4%. The same results canbe observed graphically from Figure 8.

Figure 8. Comparison Analysis

6. CONCLUSIONIn this paper, an exhaustive analysis of two designmethodologies for SR flip flop in 45nm CMOS technologyhas been carried out. The comparison has been performedfor area, delay and power consumption. According to thepresented results, the SR flip flop in semi-custom design iscompact with less delay and low power consumption.Thus, it has better performance when used in memories.

REFERENCES[1] Rishikesh V. Tambat, Sonal A. Lakhotiya, “Design of Flip-Flops forHigh Performance VLSI Applications using Deep Submicron CMOSTechnology”, International Journal of Current Engineering andTechnology, Vol.4, No.2, pp. 770-774, 2014.[2] Priyanka Sharma, Rajesh Mehra, “True Single Phase Clocking BasedFlip-Flop Design Using Different Foundries”, International Journal ofAdvances in Engineering & Technology (IJAET), Vol. 7, Issue 2, pp.352-358, 2014.[3] K. Rajasri, A. Bharathi, M. Manikandan, “Performance of Flip-FlopUsing 22nm CMOS Technology”, International Journal of InnovativeResearch in Computer and Communication Engineering, Vol. 2, Issue 8,pp. 5272-5276, 2014.[4] Rachit Manchanda, Rajesh Mehra, “Low Propagation Delay Design of3-Bit Ripple Counter on 0.12 Micron Technology”, International Journalof Research in Computer Applications and Robotics, Vol.1, Issue.2, pp. 7-15, March-April 2013.[5] Mostafa H., Anis M., Elmasry M., “Comparative Analysis of TimingYield Improvement under Process Variations of Flip-Flop Circuits”, IEEEComputer Society Annual Symposium on VLSI (ISVLSI '09), pp. 133 -138, 2009.[6] Upwinder Kaur, Rajesh Mehra, “Low Power CMOS Counter UsingClock Gated Flip-Flop”, International Journal of Engineering andAdvanced Technology (IJEAT), Vol-2, Issue-4, pp. 796-798, April 2013.[7] Simmy Hirkaney, Sandip Nemade, Vikash Gupta, “Power EfficientDesign of Counter on 0.12 Micron Technology”, International Journal ofSoft Computing and Engineering (IJSCE), Volume-1, Issue-1, pp. 19-23,March 2011.

[8] Myneni Jahnavi, S. Asha Latha, T. Ravi, E. Logashanmugam, "Designand Analysis of Johnson Counter Using FinFET Technology ", IOSRJournal of VLSI and Signal Processing (IOSR-JVSP), Volume 1, Issue 6,pp. 1-6, 2013.[9] Naik S. , Chandel R. , “Design of a Low Power Flip-Flop UsingCMOS Deep Sub Micron Technology”, IEEE International Conference onRecent Trends in Information, Telecommunication and Computing (ITC),pp. 253-256, 2010.[10] Vladimir Stojanovic, Vojin G. Oklobdzija, “Comparative Analysis ofMaster–Slave Latches and Flip-Flops for High-Performance and Low-Power Systems”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, pp.536-548, April 1999.