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1
Introduction toCMOS VLSI
Design
Lecture 10: Sequential Circuits
David Harris
Harvey Mudd CollegeSpring 2004
2
10: Sequential Circuits Slide 2CMOS VLSI Design
OutlineFloorplanningSequencingSequencing Element DesignMax and Min-DelayClock SkewTime BorrowingTwo-Phase Clocking
3
10: Sequential Circuits Slide 3CMOS VLSI Design
Project StrategyProposal– Specifies inputs, outputs, relation between them
Floorplan– Begins with block diagram– Annotate dimensions and location of each block– Requires detailed paper design
Schematic– Make paper design simulate correctly
Layout– Physical design, DRC, NCC, ERC
4
10: Sequential Circuits Slide 4CMOS VLSI Design
FloorplanHow do you estimate block areas?– Begin with block diagram– Each block has
• Inputs• Outputs• Function (draw schematic)• Type: array, datapath, random logic
Estimation depends on type of logic
5
10: Sequential Circuits Slide 5CMOS VLSI Design
MIPS Floorplan
datapath2700 λ x 1050 λ
(2.8 Mλ2)
alucontrol200 λ x 100 λ
(20 kλ2)
zipper 2700 λ x 250 λ
2700 λ
1690 λ
wiring channel: 30 tracks = 240 λ
mips(4.6 Mλ2)
bitslice 2700 λ x 100 λ
control1500 λ x 400 λ
(0.6 Mλ2)
3500 λ
3500 λ
5000λ
5000 λ
10 I/O pads
10 I/O pads
10 I/O pads
10 I/O pads
6
10: Sequential Circuits Slide 6CMOS VLSI Design
Area EstimationArrays:– Layout basic cell– Calculate core area from # of cells– Allow area for decoders, column circuitry
Datapaths– Sketch slice plan– Count area of cells from cell library– Ensure wiring is possible
Random logic– Compare complexity do a design you have done
7
10: Sequential Circuits Slide 7CMOS VLSI Design
MIPS Slice Plan
mux2
inv
flop
flop
flop
flop
mux2
inv
writedriver
dualsram
dualsram
dualsram
dualsrambit0
srampullup
readmux
flop
mux4
flop
mux2
inv
flop
mux4
and2
flop
and2
inv
mux2
and2
or2
fulladder
mux4
register fileramslice
ALUadrmux
flop
MD
R
IR3...0 writem
ux
srcB srcA aluout
zerodetect
PC
memdatawritedata
adr
pcimmediate
aluout
aluresult
srcBsrcAbitlines
44 24 93 93 93 93 93 44 24 52 48 48 48 48 16 86 93 93 93 9344 24 4424131 131 13139 39 39 39 160
8
10: Sequential Circuits Slide 8CMOS VLSI Design
Typical Layout DensitiesTypical numbers of high-quality layoutDerate by 2 for class projects to allow routing and some sloppy layout.Allocate space for big wiring channels
100 λ2 / bitROM100 λ2 / bitDRAM1000 λ2 / bitSRAM
250 – 750 λ2 / transistorOr 6 WL + 360 λ2 / transistor
Datapath1000-1500 λ2 / transistorRandom logic (2 metal layers)AreaElement
9
10: Sequential Circuits Slide 9CMOS VLSI Design
SequencingCombinational logic– output depends on current inputs
Sequential logic– output depends on current and previous inputs– Requires separating previous, current, future– Called state or tokens– Ex: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine
10
10: Sequential Circuits Slide 10CMOS VLSI Design
Sequencing Cont.If tokens moved through pipeline at constant speed, no sequencing elements would be necessaryEx: fiber-optic cable– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses– But dispersion sets min time between pulses
This is called wave pipelining in circuitsIn most circuits, dispersion is high– Delay fast tokens so they don’t catch slow ones.
11
10: Sequential Circuits Slide 11CMOS VLSI Design
Sequencing OverheadUse flip-flops to delay fast tokens so they move through exactly one stage each cycle.Inevitably adds some delay to the slow tokensMakes circuit slower than just the logic delay– Called sequencing overhead
Some people call this clocking overhead– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence
12
10: Sequential Circuits Slide 12CMOS VLSI Design
Sequencing ElementsLatch: Level sensitive– a.k.a. transparent latch, D latch
Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams– Transparent– Opaque– Edge-trigger
D Flop
Latc
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
13
10: Sequential Circuits Slide 13CMOS VLSI Design
Sequencing ElementsLatch: Level sensitive– a.k.a. transparent latch, D latch
Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams– Transparent– Opaque– Edge-trigger
D Flop
Latc
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
14
10: Sequential Circuits Slide 14CMOS VLSI Design
Latch DesignPass Transistor LatchPros++
Cons––––––
D Q
φ
15
10: Sequential Circuits Slide 15CMOS VLSI Design
Latch DesignPass Transistor LatchPros+ Tiny+ Low clock load
Cons– Vt drop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion input
D Q
φ
Used in 1970’s
17
10: Sequential Circuits Slide 17CMOS VLSI Design
Latch DesignTransmission gate+ No Vt drop- Requires inverted clock D Q
φ
φ
18
10: Sequential Circuits Slide 18CMOS VLSI Design
Latch DesignInverting buffer+++ Fixes either
••
–
D
φ
φ
X Q
D Q
φ
φ
19
10: Sequential Circuits Slide 19CMOS VLSI Design
Latch DesignInverting buffer+ Restoring+ No backdriving+ Fixes either
• Output noise sensitivity• Or diffusion input
– Inverted output
D
φ
φ
X Q
D Q
φ
φ
21
10: Sequential Circuits Slide 21CMOS VLSI Design
Latch DesignTristate feedback+ Static– Backdriving risk
Static latches are now essential
φ
φ φ
φ
QD X
23
10: Sequential Circuits Slide 23CMOS VLSI Design
Latch DesignBuffered input+ Fixes diffusion input+ Noninverting
φ
φ
QD X
φ
φ
25
10: Sequential Circuits Slide 25CMOS VLSI Design
Latch DesignBuffered output+ No backdriving
Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading
φ
φ
Q
D X
φ
φ
27
10: Sequential Circuits Slide 27CMOS VLSI Design
Latch DesignDatapath latch+ Smaller, faster- unbuffered input
φ
φ φ
φ
Q
D X
28
10: Sequential Circuits Slide 28CMOS VLSI Design
Flip-Flop DesignFlip-flop is built as pair of back-to-back latches
D Q
φ
φ
φ
φ
X
D
φ
φ
φ
φ
X
Q
Qφ
φ
φ
φ
29
10: Sequential Circuits Slide 29CMOS VLSI Design
EnableEnable: ignore clock when en = 0– Mux: increase latch D-Q delay– Clock Gating: increase en setup time, skew
D Q
Latc
h
D Q
en
en
φ
φ
Latc
hDQ
φ
0
1
en
Latc
h
D Q
φ en
DQ
φ
0
1
enD Q
φ en
Flop
Flop
Flop
Symbol Multiplexer Design Clock Gating Design
30
10: Sequential Circuits Slide 30CMOS VLSI Design
ResetForce output low when reset assertedSynchronous vs. asynchronous
D
φ
φ
φ
φ
Q
Qφ
φ
φ
φ
reset
D
φ
φφ
φ
φ
φ
Qφ
φ
Dreset
φ
φ
Qφ
φ
Dreset
reset
φ
φ
reset
Synchronous R
esetA
synchronous Reset
Sym
bol FlopD Q
Latc
h
D Q
reset reset
φ φ
φ
φ
Q
reset
31
10: Sequential Circuits Slide 31CMOS VLSI Design
Set / ResetSet forces output high when enabled
Flip-flop with asynchronous set and reset
D
φ
φ
φ
φφ
φ
Q
φ
φ
reset
set reset
set
32
10: Sequential Circuits Slide 32CMOS VLSI Design
Sequencing MethodsFlip-flops2-Phase LatchesPulsed Latches
Flip-FlopsFl
opLa
tch
Flop
clk
φ1
φ2
φp
clk clk
Latc
h
Latc
h
φp φp
φ1 φ1φ2
2-Phase Transparent Latches
Pulsed Latches
Combinational Logic
CombinationalLogic
CombinationalLogic
Combinational Logic
Latc
h
Latc
h
Tc
Tc/2
tnonoverlap tnonoverlap
tpw
Half-Cycle 1 Half-Cycle 1
33
10: Sequential Circuits Slide 33CMOS VLSI Design
Timing Diagrams
Flop
A
Y
tpdCombinational
LogicA Y
D Q
clk clk
D
Q
Latc
hD Q
clk clk
D
Q
tcd
tsetup thold
tccq
tpcq
tccq
tsetup tholdtpcq
tpdqtcdqLatch/Flop Hold Timethold
Latch/Flop Setup Timetsetup
Latch D-Q Cont. Delaytpcq
Latch D-Q Prop Delaytpdq
Latch/Flop Clk-Q Cont. Delaytccq
Latch/Flop Clk-Q Prop Delaytpcq
Logic Cont. Delaytcd
Logic Prop. Delaytpd
Contamination and Propagation Delays
34
10: Sequential Circuits Slide 34CMOS VLSI Design
Max-Delay: Flip-Flops
F1 F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tpd
tsetuptpcq
( )sequencing overhead
pd ct T≤ −1442443
35
10: Sequential Circuits Slide 35CMOS VLSI Design
Max-Delay: Flip-Flops
F1 F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tpd
tsetuptpcq
( )setup
sequencing overhead
pd c pcqt T t t≤ − +14243
36
10: Sequential Circuits Slide 36CMOS VLSI Design
Max Delay: 2-Phase Latches
Tc
Q1
L1
φ1
φ2
L2 L3
φ1 φ1φ2
CombinationalLogic 1
CombinationalLogic 2
Q2 Q3D1 D2 D3
Q1
D2
Q2
D3
D1
tpd1
tpdq1
tpd2
tpdq2
( )1 2
sequencing overhead
pd pd pd ct t t T= + ≤ −1442443
37
10: Sequential Circuits Slide 37CMOS VLSI Design
Max Delay: 2-Phase Latches
Tc
Q1
L1
φ1
φ2
L2 L3
φ1 φ1φ2
CombinationalLogic 1
CombinationalLogic 2
Q2 Q3D1 D2 D3
Q1
D2
Q2
D3
D1
tpd1
tpdq1
tpd2
tpdq2
( )1 2
sequencing overhead
2pd pd pd c pdqt t t T t= + ≤ −123
38
10: Sequential Circuits Slide 38CMOS VLSI Design
Max Delay: Pulsed Latches
Tc
Q1 Q2D1 D2
Q1
D2
D1
φp
φp φp
Combinational LogicL1 L2
tpw
(a) tpw > tsetup
Q1
D2
(b) tpw < tsetup
Tc
tpd
tpdq
tpcq
tpd tsetup
( )sequencing overhead
max pd ct T≤ −14444244443
39
10: Sequential Circuits Slide 39CMOS VLSI Design
Max Delay: Pulsed Latches
Tc
Q1 Q2D1 D2
Q1
D2
D1
φp
φp φp
Combinational LogicL1 L2
tpw
(a) tpw > tsetup
Q1
D2
(b) tpw < tsetup
Tc
tpd
tpdq
tpcq
tpd tsetup
( )setup
sequencing overhead
max ,pd c pdq pcq pwt T t t t t≤ − + −14444244443
40
10: Sequential Circuits Slide 40CMOS VLSI Design
Min-Delay: Flip-Flops
cdt ≥ CL
clk
Q1
D2
F1
clk
Q1
F2
clk
D2
tcd
thold
tccq
41
10: Sequential Circuits Slide 41CMOS VLSI Design
Min-Delay: Flip-Flops
holdcd ccqt t t≥ − CL
clk
Q1
D2
F1
clk
Q1
F2
clk
D2
tcd
thold
tccq
42
10: Sequential Circuits Slide 42CMOS VLSI Design
Min-Delay: 2-Phase Latches
1, 2 cd cdt t ≥CL
Q1
D2
D2
Q1
φ1
L1
φ2
L2
φ1
φ2
tnonoverlap
tcd
thold
tccq
Hold time reduced by nonoverlap
Paradox: hold applies twice each cycle, vs. only once for flops.
But a flop is made of two latches!
43
10: Sequential Circuits Slide 43CMOS VLSI Design
Min-Delay: 2-Phase Latches
1, 2 hold nonoverlapcd cd ccqt t t t t≥ − −CL
Q1
D2
D2
Q1
φ1
L1
φ2
L2
φ1
φ2
tnonoverlap
tcd
thold
tccq
Hold time reduced by nonoverlap
Paradox: hold applies twice each cycle, vs. only once for flops.
But a flop is made of two latches!
44
10: Sequential Circuits Slide 44CMOS VLSI Design
Min-Delay: Pulsed Latches
cdt ≥ CL
Q1
D2
Q1
D2
φp tpw
φp
L1
φp
L2
tcd
thold
tccq
Hold time increased by pulse width
45
10: Sequential Circuits Slide 45CMOS VLSI Design
Min-Delay: Pulsed Latches
holdcd ccq pwt t t t≥ − +CL
Q1
D2
Q1
D2
φp tpw
φp
L1
φp
L2
tcd
thold
tccq
Hold time increased by pulse width
46
10: Sequential Circuits Slide 46CMOS VLSI Design
Time BorrowingIn a flop-based system:– Data launches on one rising edge– Must setup before next rising edge– If it arrives late, system fails– If it arrives early, time is wasted– Flops have hard edges
In a latch-based system– Data can pass through latch while transparent– Long cycle of logic can borrow time into next– As long as each loop completes in one cycle
47
10: Sequential Circuits Slide 47CMOS VLSI Design
Time Borrowing Example
Latc
h
Latc
h
Latc
h
Combinational Logic CombinationalLogic
Borrowing time acrosshalf-cycle boundary
Borrowing time acrosspipeline stage boundary
(a)
(b) Latc
h
Latc
hCombinational Logic Combinational
Logic
Loops may borrow time internally but must complete within the cycle
φ1
φ2
φ1 φ1
φ1
φ2
φ2
48
10: Sequential Circuits Slide 48CMOS VLSI Design
How Much Borrowing?
Q1
L1
φ1
φ2
L2
φ1 φ2
Combinational Logic 1Q2D1 D2
D2
Tc
Tc/2 Nominal Half-Cycle 1 Delay
tborrow
tnonoverlap
tsetup
( )borrow setup nonoverlap2cTt t t≤ − +
2-Phase Latches
borrow setuppwt t t≤ −
Pulsed Latches
49
10: Sequential Circuits Slide 49CMOS VLSI Design
Clock SkewWe have assumed zero clock skewClocks really have uncertainty in arrival time– Decreases maximum propagation delay– Increases minimum contamination delay– Decreases time borrowing
50
10: Sequential Circuits Slide 50CMOS VLSI Design
Skew: Flip-Flops
F1 F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tskew
CL
Q1
D2
F1
clk
Q1
F2
clk
D2
clk
tskew
tsetup
tpcq
tpdq
tcd
thold
tccq
( )setup skew
sequencing overhead
hold skew
pd c pcq
cd ccq
t T t t t
t t t t
≤ − + +
≥ − +
144424443
51
10: Sequential Circuits Slide 51CMOS VLSI Design
Skew: Latches
Q1
L1
φ1
φ2
L2 L3
φ1 φ1φ2
CombinationalLogic 1
CombinationalLogic 2
Q2 Q3D1 D2 D3
( )
( )
sequencing overhead
1 2 hold nonoverlap skew
borrow setup nonoverlap skew
2
,
2
pd c pdq
cd cd ccq
c
t T t
t t t t t t
Tt t t t
≤ −
≥ − − +
≤ − + +
123
2-Phase Latches
( )
( )
setup skew
sequencing overhead
hold skew
borrow setup skew
max ,pd c pdq pcq pw
cd pw ccq
pw
t T t t t t t
t t t t t
t t t t
≤ − + − +
≥ + − +
≤ − +
1444442444443
Pulsed Latches
52
10: Sequential Circuits Slide 52CMOS VLSI Design
Two-Phase ClockingIf setup times are violated, reduce clock speedIf hold times are violated, chip fails at any speedIn this class, working chips are most important– No tools to analyze clock skew
An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap timesCall these clocks φ1, φ2 (ph1, ph2)
53
10: Sequential Circuits Slide 53CMOS VLSI Design
Safe Flip-FlopIn class, use flip-flop with nonoverlapping clocks– Very slow – nonoverlap adds to setup time– But no hold times
In industry, use a better timing analyzer– Add buffers to slow signals if hold time is at risk
D
φ2
X
Q
Q
φ1
φ2
φ1
φ1φ1
φ2
φ2
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