logical effort a method to optimize circuit topology

Logical EffortA Method to Optimize Circuit

TopologySwarthmore College

E77 VLSI Design

Adem KaderDavid LuongMark Piper

December 6, 2005

Current Issues Facing Circuit Designers

• Wanting to optimize circuits for faster performance, inexperienced designers often encounter…

– “Simulate-and-Tweak” loops– Incomplete intuition in design process– Uncertainty in decision-making

Logical Effort as a Solution

• Quick method of circuit analysis– Circuit topology– Transistor sizing– Delay estimation

• Easy way to compare multi-stage designs

• “Back-of-the-envelope” calculation• Provides intuition of circuit timing

characteristics in complex circuitry

How does it work?

• Assumes RC model of a transistord = gh + p

d = propagation delaygh = effort delay

• g = logical effort• h = electrical effort = Cout/Cin

p = parasitic delay

Defining Logical Effort

• Ratio of the input capacitance of the gate to the input capacitance of an inverter that can deliver the same output current

• Measure of a gate to drive a particular fan-out relative to an inverter

Visualizing Logical Effort

Application of Logical EffortEstimating Delay Propagation

d = g h + p

timeofunitsCCCCd inAinAinAinB 5141)/4(11)/(1

timeofunitsCCd inAinB 6242)4/34(3/412)/(3/4

INVERTER

NAND

Multi-Stage Design and Logical Effort

• Often circuits are more complicated than an inverter or a NAND gate

• Same framework applies with the modification…

)(igG

Logical Effort and Transistor Sizing

• Interested in choosing transistor sizing to minimize stage and overall delay

f (min) = g(i) * h(i) = F1/N

• Delay equation becomes…PFND N /1

min/)()()( fiCigiC outin

• In the end…

Application of Transistor Sizing

timeofunitspGBH 14)128*1*37.2(3)2(3 33

How do we choose stage capacitances given we want to minimize propagation delay?

3/88137.2(min) 33 GBHf

CCfiCigC outlastgatein 4)3/8/(8)3/4((min)/)()((min)

CCfiCigC outtendtolastgain 2)3/8/(4)3/4((min)/)()((min)2

Optimal Number of GatesPath

Effort F

Optimal N

Minimum Delay, D

Stage Effort, f

0-5.83 1 1.0-6.8 0-5.8

5.82-22.3 2 6.8-11.4 2.4-4.7

22.3-82.2 3 11.4-16.0 2.8-4.4

82.2-300 4 16.0-20.7 3.0-4.2

300-1090 5 20.7-25.3 3.1-4.1

1090-3920

6 25.3-29.8 3.2-4.0

FN 4log

Rule of thumb is …

Note that single gate does not always translate to minimized delay

Example: The Implementation Problem

Which do you choose?

Using Logical Effort…

• Option 1:• Path logic effort G = 1 * 6/3 * 1 = 2• Path Branch Effort B = 1• Path electrical effort H = Cout/Cin = 8C/C = 8• Path Stage effort = F = GBH = 2*1*8 = 16• Dmin = N*F1/N+P = 3*(16)1/3 + (1+4*1 + 1)

= 3*3.25 + 6 = 13.5

Using Logical Effort…

• Option 2:• Path logic effort G = 1 * 4/3 * 5/3 = 20/9• Path Branch Effort B = 1• Path electrical effort H = Cout/Cin = 8C/C = 8• Path Stage effort = F = GBH = 20/9*1*8 =

160/9• Dmin = N*F1/N+P = 3*(160/9)1/3 + (1+2*1

+ 2) = 3*3.25 + 5 = 12.8

Using SPICE…

Example: Choosing the Optimal N

The Buffer Problem• Must drive 64 parallel inverters• Choose 1, 3, or 5 series inverter stages to

drive the load?

finding optimal #of stages

N 5 3 1

f 2.3 4 64

D 16.5 15 65

1 inverter

3 inverters

5 inverters

all together

Problems with logical effort

• It’s only an approximation– But a good one

• It does not guarantee optimal solution– but gets quite close

• Chicken and egg problem– chicken

• Built for speed– Does not account for power consumption and physical size

So What Have We Learned?

• Logical Effort…– Provides method to quickly determine

speed of design topologies for comparison

– Displays changes to parameter tweaking

I agree withstupid

It’s so… logical!

now that makes sense!