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LPC11XX HANDS ONDaniel WidyantoSeptember 2010
2
Disclaimer
Although this presentation has been made as correct as possible, it cannot replace the user manual as the main source of the information
In doubts, please check the LPC11xx User Manual
3
Contents
Understanding LPC11xx Clock
In-Application Programming
LPC11xx Power Management
4
Understanding LPC11xx ClockHands On
5
Understanding LPC11xx Clock
6
Understanding LPC11xx Clock
LPC11xx clock source:– Internal RC oscillator : 12MHz ±1% – Watchdog oscillator : 7.8kHz – 1.7MHz ±40% – System oscillator : 1MHz – 25MHz
• External clock ?
Internal RC oscillator
7
Understanding LPC11xx Clock
Watchdog oscillator
8
Understanding LPC11xx Clock
System Oscillator
9
Understanding LPC11xx Clock
System PLL (Phase Lock Loop)– To multiply the input clock into desired operating frequency
10
Understanding LPC11xx Clock
Calculating PLL parameter values
Fclkout = M x FclkinM = Fclkout1) / Fclkin2)
1) 10MHz <= Fclkin < 25MHz2) Fclkin <= Fclkout <= 50MHz
Fcco3) = 2 x P x Fclkout3)156MHz <= Fcco <= 320MHz
11
Understanding LPC11xx Clock
Initializing PLL1. Select PLL input2. Toggle ENA bit on SYSPLLCLKUEN 3. Fill the ‘M’ and ‘N’ value to SYSPLLCTRL4. Power on SYSPLL
1. Wait until it’s locked
12
Understanding LPC11xx Clock
Main clock
13
Understanding LPC11xx Clock
System clock– Control core’s clock, flash, ROM, RAM, and most of the
peripherals
14
Understanding LPC11xx Clock
Peripheral clocks
15
Understanding LPC11xx Clock
Watchdog peripheral
16
Understanding LPC11xx Clock
CLKOUT pin
17
Understanding LPC11xx ClockHands On
Open ‘LPCXpresso’ and use ‘blinky’ for LPC1114 as the hands on code
Answer these questions:– Just before main() is called, which LPC1114 peripherals that are
not activated (turned off) ?– What is the core frequency of ‘blinky’ ?– Change the main clock frequency of ‘blinky’ into half of the
current frequency. What are the things that you need to modify ?– View the main clock frequency through oscilloscope (if available).
Enable the CLKOUT pin to connect with main clock. What are the things that you need to modify ?
18
In-Application ProgrammingHands On
19
In-Application Programming
What is that ?– Capability of the MCU to reprogram its own flash from user’s
software– No external circuitry is needed
Usage:– Field firmware upgrade– EEPROM replacement– Firmware configuration storage– Data storage– Etc
Limitation:– Can only be erased in 1-block size (ie. 4kBytes)– Slow erase time (100ms) and writing time (1ms)– Flash is not accessible during write / erase time
• The codes need to be run from RAM during IAP
20
IAP functionsISP functionsChecksum functions…………
Boot loader
In-Application Programming
LPC1114 Implementation
ARMCortex-M0
RAM
Flash
Peripherals
ROM
0x1FFF1FF1
21
In-Application Programming
How to call the ROM function from C ?
Function pointer– Can use the same concept using function pointer
GPIOSetDir( 0, 7, 1 );
e8:2000 movs r0, #0 ea:2107 movs r1, #7 ec:2201 movs r2, #1 ee:f000 f81b bl 128 <GPIOSetDir>
22
In-Application Programming
Function pointer#define IAP_LOCATION 0x1fff1ff1
unsigned long result[4];unsigned long command[5];
typedef void (*IAP)(unsigned int [],unsigned int[]);IAP iap_entry;
unsigned long calling_IAP_functions(void) { // Fill up the command values command[0] = 0x5410
iap_entry=(IAP) IAP_LOCATION; iap_entry (command, result);
// Result is in result[0] return result[0];}
23
In-Application Programming
IAP Parameter Passing
24
In-Application Programming
LPC11xx flash operation cheat sheet– To erase sector:
• Issue ‘Prepare sector(s) for write operation’ command first, followed by ‘Erase sector[s]’ command
– To write sector:• Issue ‘Prepare sector(s) for write operation’ command first, followed by
‘Copy RAM to Flash’ command
– To read sector:• Read like ordinary memory• Eg. If the data is 4-bytes long, written at 0x020, use:
– To check whether the sector is blank:• Issue ‘Blank check sector(s)’
uint32_t stored_value = * ((uint32_t *) 0x20);
25
In-Application Programming
Flash sector – Address mapping
26
In-Application ProgrammingHands On
Import the ‘LPC11xx_IAP_Demo’ program into LPCXpresso workspace
Hands On:– The minimum of flash writing is 256 bytes. Write the
‘demo_config’ data and fill up the rest of the 256 bytes with ‘0xAA’. Show it into your LPCXpresso
– Implement IAP function: ‘Blank Check’ sector.
Answer these questions:– The 32-bytes on top of the SRAM is reserved for IAP. How to
arrange the linker to avoid 32-bytes of the top of SRAM for IAP ?
27
LPC11xx Power ManagementHands On
28
LPC11xx Power Management
ARM Cortex-M0 core power management– Comes with the system core– Consist of: sleep mode and deep sleep mode
Sleep mode:– Stops the processor clock -> execution of instructions is
suspended until either a reset or an interrupt occurs– Implemented by all of ARM Cortex-M3 vendors
Deep sleep mode:– Vendor implementation specific– Stops the any peripherals that is controlled by ‘PDRUNCFG’,
except for BOD and watchdog oscillator
29
LPC11xx Power Management
NXP specific Power Mode– Consist of deep power down mode
Deep power down mode– All peripherals are powered down, except for WAKEUP pins– When wake up, all peripherals are reset. Only GPREG0 – GPREG4
and PCON that will be in the current status before deep power down mode
30
LPC11xx Power Management
Selecting Power Management Modes
0
DPDEN
1
0
SLEEPDEEP
1Deep Power-Down
Sleep
Deep Sleep
31
LPC11xx Power Management
Entering power saving mode– Configure the wake-up source– Select the power mode– Use ARM WFI instruction
• ARM Cortex-M0 also supports WFE (‘Wait For Event’) to enter sleep mode instruction but it is not implemented in LPC11xx
Options– PDRUNCFG (0x4004 8238)
• Control peripherals power during active mode– PDWAKECFG (0x4004 8234)
• Control peripherals power that needs to be activated after wake up– PDSLEEPCFG (0x4004 8230)
• Control watchdog and brownout circuit when entering deep sleep mode
– SLEEPONEXIT on SCR (0xE000 ED10)• Control whether system should sleep after finish serving IRQ
32
LPC11xx Power Management
Configure wake up source– For sleep and deep sleep:
• The wake up source interrupt must be enabled at NVIC– For deep sleep:
• Only start logic pins (PIO0_0 – PIO0_11 and PIO1_0) that able to wake the MCU
• Only peripherals that have pin out mux-ed with one of PIO0_0 – PIO0_11 or PIO_1, and can use watchdog oscillator as its clock source is able to wake the MCU
– For deep power down:• Only start logic pins (PIO0_0 – PIO0_11 and PIO1_0) that able to
wake the MCU• The start logic must be set to falling edge trigger
33
LPC11xx Power Management
Things to remember– Never let main clock source from PLL or system oscillator during
power saving mode• The system will never be awaken (for deep sleep and power down
mode)• If periodic wake up is needed, use watchdog oscillator as main clock
source• Otherwise, always set the internal RC oscillator as main clock
– The ‘start logic pins’ interrupt must be activated to enable start logic
• Including power down mode
34
LPC11xx Power ManagementHands On
Import ‘LPC11xx_PowerManagement_Demo’ program into LPCXpresso
Try both sleep mode and deep sleep mode– The JTAG will not work if device is entering power saving mode
(sleep, deep sleep, and power down mode).– Once the debug screen is appeared, stop the debug mode, unplug
and plug the LPCXpresso to test the firmware
Answer / do the exercises below:– Why the Timer interrupt needs to be disabled to make the device
enter the ‘sleep’ mode ?– Change the wake-up source into PIO0_7– Enable the power down mode. Check deep power down mode flag
in PCON, and skip sleeping if it is active
1
LPC11XX HANDS ONDaniel WidyantoSeptember 2010
2
2
Disclaimer
Although this presentation has been made as correct as possible, it cannot replace the user manual as the main source of the information
In doubts, please check the LPC11xx User Manual
3
3
Contents
Understanding LPC11xx Clock
In-Application Programming
LPC11xx Power Management
4
4
Understanding LPC11xx ClockHands On
5
5
Understanding LPC11xx Clock
LPC11xx clock system consists of three major blocks:• Three oscillators to generate the clock• One PLL to multiply the clock• Six clock divider to generate different clock rate for different devices
6
6
Understanding LPC11xx Clock
LPC11xx clock source:– Internal RC oscillator : 12MHz ±1% – Watchdog oscillator : 7.8kHz – 1.7MHz ±40% – System oscillator : 1MHz – 25MHz
• External clock ?
Internal RC oscillator
The internal RC oscillator can be turned off using ‘PDRUNCFG’ register
The internal RC oscillator is calibrated at NXP manufacturing site. The calibration value is written by bootloader during boot up. User can change the register value to change the internal RC oscillation frequency, but it is not recommended since each device has different characteristic (ie. The frequency change per TRIM value change is not always same for each device).
7
7
Understanding LPC11xx Clock
Watchdog oscillator
The watchdog oscillator frequency is controlled by two things:• Watchdog oscillator divider (DIVSEL)• Watchdog output frequency selection
Any FREQSEL value will generate output frequency within 40% tolerance. Hence, it is not recommended for application that needs accurate timing
The watchdog frequency is undefined after reset. The WDTOSCCTRL must be programmed before watchdog oscillator is used.
The watchdog oscillator can be powered down using ‘PDRUNCFG’ register.
8
8
Understanding LPC11xx Clock
System Oscillator
System oscillator can be bypassed if user wants to use external clock instead of crystal.
System oscillator can be powered down using ‘PDRUNCFG’ register.
9
9
Understanding LPC11xx Clock
System PLL (Phase Lock Loop)– To multiply the input clock into desired operating frequency
System PLL can use internal RC oscillator or system oscillator as its source. Refer to SYSPLLCLKSEL for the PLL input source. Both clocks must be running before clock source is updated.
After the PLL input source is changed, the ENA bit should be toggled. Here’s the code example:
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */LPC_SYSCON->SYSPLLCLKUEN = 0x01;while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
10
10
Understanding LPC11xx Clock
Calculating PLL parameter values
Fclkout = M x FclkinM = Fclkout1) / Fclkin2)
1) 10MHz <= Fclkin < 25MHz2) Fclkin <= Fclkout <= 50MHz
Fcco3) = 2 x P x Fclkout3)156MHz <= Fcco <= 320MHz
The PLL can only accept 10Mhz – 25Mhz input (either from internal RC oscillator or system oscillator). This frequency will be multiplied according to user’s target frequency (Fclkout).
The Fclkout cannot over than 50MHz since the silicon die is guaranteed to work correctly according to the specification until 50Mhz.
The Fcco can range from 156MHz – 320Mhz. The lower Fcco, the lower PLL power consumption is.
11
11
Understanding LPC11xx Clock
Initializing PLL1. Select PLL input2. Toggle ENA bit on SYSPLLCLKUEN 3. Fill the ‘M’ and ‘N’ value to SYSPLLCTRL4. Power on SYSPLL
1. Wait until it’s locked
Changing PLL value must started with power down the PLL first
The PLL parameter value cannot be changed during PLL locked is active. It may cause software crash.
12
12
Understanding LPC11xx Clock
Main clock
By selecting MAINCLKSEL = 0x01, user can use the main oscillator frequency (bypassing the PLL).
After the MAINCLKSEL is updated, the ENA bit at MAINCLKUEN must be toggled. Here’s the code example to toggle it.LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */LPC_SYSCON->MAINCLKUEN = 0x01;while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
13
13
Understanding LPC11xx Clock
System clock– Control core’s clock, flash, ROM, RAM, and most of the
peripherals
System clock controls core and most of the peripherals clock, including SYSAHBCLKCTRL
The SYSAHBCLKCTRL is register to enable / disable other peripheral’s clock, including the ones that have independent clock divider (UART, SSP0, SSP1, Watchdog, CLKOUT). Therefore, SYSAHBCLKDIV cannot be disabled (by writing 0) or the whole system will freeze.
14
14
Understanding LPC11xx Clock
Peripheral clocks
The independent clock divider allows these peripheral to be independently disabled / enabled.
Other than SSP0CLKDIV, SSP1CLKDIV, and UARTCLKDIV, the SYSAHBCLKCTRL (shown on page before this) also have control to enable / disable the peripheral clock.
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15
Understanding LPC11xx Clock
Watchdog peripheral
After the MAINCLKSEL is updated, the ENA bit at MAINCLKUEN must be toggled.
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16
Understanding LPC11xx Clock
CLKOUT pin
LPC11xx pin as oscillator output• Can be used to debug the clock settings• Can be used to drive other external peripherals• Can only pump 50MHz max (LPC11xx pin limitation)
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17
Understanding LPC11xx ClockHands On
Open ‘LPCXpresso’ and use ‘blinky’ for LPC1114 as the hands on code
Answer these questions:– Just before main() is called, which LPC1114 peripherals that are
not activated (turned off) ?– What is the core frequency of ‘blinky’ ?– Change the main clock frequency of ‘blinky’ into half of the
current frequency. What are the things that you need to modify ?– View the main clock frequency through oscilloscope (if available).
Enable the CLKOUT pin to connect with main clock. What are the things that you need to modify ?
18
18
In-Application ProgrammingHands On
19
19
In-Application Programming
What is that ?– Capability of the MCU to reprogram its own flash from user’s
software– No external circuitry is needed
Usage:– Field firmware upgrade– EEPROM replacement– Firmware configuration storage– Data storage– Etc
Limitation:– Can only be erased in 1-block size (ie. 4kBytes)– Slow erase time (100ms) and writing time (1ms)– Flash is not accessible during write / erase time
• The codes need to be run from RAM during IAP
The LPC11xx Flash data retention is 10K program/erase-cycles. The programming can be done as minimum as 256kBytes for each writing operation. Hence, each sector could be written 16 times before it is erased.
20
20
IAP functionsISP functionsChecksum functions…………
Boot loader
In-Application Programming
LPC1114 Implementation
ARMCortex-M0
RAM
Flash
Peripherals
ROM
0x1FFF1FF1
21
21
In-Application Programming
How to call the ROM function from C ?
Function pointer– Can use the same concept using function pointer
GPIOSetDir( 0, 7, 1 );
e8:2000 movs r0, #0 ea:2107 movs r1, #7 ec:2201 movs r2, #1 ee:f000 f81b bl 128 <GPIOSetDir>
When a function is disassembled, its parameters are passed through the registers (or stack, but not in ARM architecture case), then the address of the function is called
We can reuse the concept using function pointer to call ROM functions in C
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In-Application Programming
Function pointer#define IAP_LOCATION 0x1fff1ff1
unsigned long result[4];unsigned long command[5];
typedef void (*IAP)(unsigned int [],unsigned int[]);IAP iap_entry;
unsigned long calling_IAP_functions(void) { // Fill up the command values command[0] = 0x5410
iap_entry=(IAP) IAP_LOCATION; iap_entry (command, result);
// Result is in result[0] return result[0];}
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23
In-Application Programming
IAP Parameter Passing
The IAP takes two parameters: the pointer to command table, and pointer to result table. The command parameter address is passed through R0, the result table address is passed through R1.
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24
In-Application Programming
LPC11xx flash operation cheat sheet– To erase sector:
• Issue ‘Prepare sector(s) for write operation’ command first, followed by ‘Erase sector[s]’ command
– To write sector:• Issue ‘Prepare sector(s) for write operation’ command first, followed by
‘Copy RAM to Flash’ command
– To read sector:• Read like ordinary memory• Eg. If the data is 4-bytes long, written at 0x020, use:
– To check whether the sector is blank:• Issue ‘Blank check sector(s)’
uint32_t stored_value = * ((uint32_t *) 0x20);
25
25
In-Application Programming
Flash sector – Address mapping
26
26
In-Application ProgrammingHands On
Import the ‘LPC11xx_IAP_Demo’ program into LPCXpresso workspace
Hands On:– The minimum of flash writing is 256 bytes. Write the
‘demo_config’ data and fill up the rest of the 256 bytes with ‘0xAA’. Show it into your LPCXpresso
– Implement IAP function: ‘Blank Check’ sector.
Answer these questions:– The 32-bytes on top of the SRAM is reserved for IAP. How to
arrange the linker to avoid 32-bytes of the top of SRAM for IAP ?
27
27
LPC11xx Power ManagementHands On
28
28
LPC11xx Power Management
ARM Cortex-M0 core power management– Comes with the system core– Consist of: sleep mode and deep sleep mode
Sleep mode:– Stops the processor clock -> execution of instructions is
suspended until either a reset or an interrupt occurs– Implemented by all of ARM Cortex-M3 vendors
Deep sleep mode:– Vendor implementation specific– Stops the any peripherals that is controlled by ‘PDRUNCFG’,
except for BOD and watchdog oscillator
LPC11xx has two different kind of power management:• ARM Cortex-M0 core power management• NXP power management IP
The deep sleep behaviour may be different from ARM Cortex-M3 vendors.
29
29
LPC11xx Power Management
NXP specific Power Mode– Consist of deep power down mode
Deep power down mode– All peripherals are powered down, except for WAKEUP pins– When wake up, all peripherals are reset. Only GPREG0 – GPREG4
and PCON that will be in the current status before deep power down mode
30
30
LPC11xx Power Management
Selecting Power Management Modes
0
DPDEN
1
0
SLEEPDEEP
1Deep Power-Down
Sleep
Deep Sleep
31
31
LPC11xx Power Management
Entering power saving mode– Configure the wake-up source– Select the power mode– Use ARM WFI instruction
• ARM Cortex-M0 also supports WFE (‘Wait For Event’) to enter sleep mode instruction but it is not implemented in LPC11xx
Options– PDRUNCFG (0x4004 8238)
• Control peripherals power during active mode– PDWAKECFG (0x4004 8234)
• Control peripherals power that needs to be activated after wake up– PDSLEEPCFG (0x4004 8230)
• Control watchdog and brownout circuit when entering deep sleep mode
– SLEEPONEXIT on SCR (0xE000 ED10)• Control whether system should sleep after finish serving IRQ
32
32
LPC11xx Power Management
Configure wake up source– For sleep and deep sleep:
• The wake up source interrupt must be enabled at NVIC– For deep sleep:
• Only start logic pins (PIO0_0 – PIO0_11 and PIO1_0) that able to wake the MCU
• Only peripherals that have pin out mux-ed with one of PIO0_0 – PIO0_11 or PIO_1, and can use watchdog oscillator as its clock source is able to wake the MCU
– For deep power down:• Only start logic pins (PIO0_0 – PIO0_11 and PIO1_0) that able to
wake the MCU• The start logic must be set to falling edge trigger
33
33
LPC11xx Power Management
Things to remember– Never let main clock source from PLL or system oscillator during
power saving mode• The system will never be awaken (for deep sleep and power down
mode)• If periodic wake up is needed, use watchdog oscillator as main clock
source• Otherwise, always set the internal RC oscillator as main clock
– The ‘start logic pins’ interrupt must be activated to enable start logic
• Including power down mode
The PLL and system oscillator needs software configuration to run. If one of them is enabled as main clock source during power saving mode, there will be no clock to run the software to configure
34
34
LPC11xx Power ManagementHands On
Import ‘LPC11xx_PowerManagement_Demo’ program into LPCXpresso
Try both sleep mode and deep sleep mode– The JTAG will not work if device is entering power saving mode
(sleep, deep sleep, and power down mode).– Once the debug screen is appeared, stop the debug mode, unplug
and plug the LPCXpresso to test the firmware
Answer / do the exercises below:– Why the Timer interrupt needs to be disabled to make the device
enter the ‘sleep’ mode ?– Change the wake-up source into PIO0_7– Enable the power down mode. Check deep power down mode flag
in PCON, and skip sleeping if it is active
The LPCXpresso will download the debugged program into flash. Hence, even if the IDE is not running, the program can still run from the board.
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