mapp: the berkeley model and algorithm prototyping platform - … · a. gokcen mahmutoglu,...

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 1

MAPP: The Berkeley Model and Algorithm

Prototyping Platform

Tianshi Wang, Karthik Aadithya, A. Gokcen MahmutogluBichen Wu, Jian Yao and Jaijeet Roychowdhury

EECS Department University of California at Berkeley

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 2

Model Development Today

Device physics into mathematical code (MATLAB)

Interdependent with simulation

» Check for errors

» Does it converge?

» Can it replicate real dynamical device behavior?

Translate into Verilog-A → Run with HSpice or Spectre

What if there are problems?

» Simulators: Complicated under the hood

» Makes testing and debugging hard MAPP: specifically designed with model development in mind

» All purpose model development in pure MATLAB

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 3

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 4

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

WriteVerilog-A

Model

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 5

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

WriteVerilog-A

Model

Run Circuitsin Commercial

Simulators

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 6

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

WriteVerilog-A

Model

robustconvergence?

Run Circuitsin Commercial

Simulators

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 7

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

WriteVerilog-A

Model

robustconvergence?

Run Circuitsin Commercial

Simulators

YesDeploy model

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 8

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

WriteVerilog-A

Model

robustconvergence?

Run Circuitsin Commercial

Simulators

YesDeploy model

convergence vsphysics tradeoff

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 9

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

WriteVerilog-A

Model

robustconvergence?

support forconvergence hooks

limited/missing

Run Circuitsin Commercial

Simulators

YesDeploy model

convergence vsphysics tradeoff

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 10

Verilog-A-based Model Development Flow

Devicephysics

AnalyticalEquationsfor Device

WriteVerilog-A

Model

robustconvergence?

support forconvergence hooks

limited/missing

Run Circuitsin Commercial

Simulators

x

no ability todebug code

YesDeploy model

convergence vsphysics tradeoff

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 11

Three Steps of MAPP

● First Step

Create correct, robust model in pure MATLAB

● Second Step

Create and verify Verilog-A model: VAPP

● Third Step

Convert into fast C++ code: MAPP C++ API, Xyce-ModSpec interface

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 12

MAPP for Device Model Development

CompactModel

Equations

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 13

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

➔ format itself eliminates somecommon modelling mistakes

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 14

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

Testimmediately(standalone)

basic debug

➔ format itself eliminates somecommon modelling mistakes

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 15

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

Run SmallCircuits in

MAPP

Testimmediately(standalone)

basic debug

➔ format itself eliminates somecommon modelling mistakes

DC/AC/TRANin MATLAB

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 16

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

Run SmallCircuits in

MAPP

Testimmediately(standalone)

Problems?

basic debug

➔ format itself eliminates somecommon modelling mistakes

DC/AC/TRANin MATLAB

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 17

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

Run SmallCircuits in

MAPP

Testimmediately(standalone)

Problems?Yes

basic debugcode/facilitiesfor inspectionand debugging

➔ model doesn't evaluate➔ overflow/domain errors

➔ DC conv. failure➔ transient timestep too small➔ unphysical results➔ voltage/current blows up

➔ format itself eliminates somecommon modelling mistakes

DC/AC/TRANin MATLAB

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 18

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

Run SmallCircuits in

MAPP

Testimmediately(standalone)

Problems?Yes

basic debugcode/facilitiesfor inspectionand debugging

➔ model doesn't evaluate➔ overflow/domain errors

➔ DC conv. failure➔ transient timestep too small➔ unphysical results➔ voltage/current blows up

➔ smoothing➔ define custom functions/derivatives➔ custom init/limiting➔ gmin

➔ format itself eliminates somecommon modelling mistakes

DC/AC/TRANin MATLAB

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 19

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

Run SmallCircuits in

MAPP

Testimmediately(standalone)

Problems?Yes

basic debugcode/facilitiesfor inspectionand debugging

➔ model doesn't evaluate➔ overflow/domain errors

➔ DC conv. failure➔ transient timestep too small➔ unphysical results➔ voltage/current blows up

➔ smoothing➔ define custom functions/derivatives➔ custom init/limiting➔ gmin

➔ format itself eliminates somecommon modelling mistakes

DC/AC/TRANin MATLAB

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 20

MAPP for Device Model Development

CompactModel

Equations

Write in MATLAB(ModSpec format)

Run SmallCircuits in

MAPP

Testimmediately(standalone)

Problems?Yes

basic debugcode/facilitiesfor inspectionand debugging

➔ model doesn't evaluate➔ overflow/domain errors

➔ DC conv. failure➔ transient timestep too small➔ unphysical results➔ voltage/current blows up

➔ smoothing➔ define custom functions/derivatives➔ custom init/limiting➔ gmin

➔ format itself eliminates somecommon modelling mistakes

DC/AC/TRANin MATLAB

No

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 21

Glimpse: Diode Model in MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 22

Glimpse: Diode Model in MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 23

Glimpse: Diode Model in MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 24

Glimpse: Diode Model in MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 25

Glimpse: Diode Model in MAPP

MOD.terminalsMOD.parmsMOD.explicit_outsMOD.f: function handleMOD.q: function handle…

MODSPECformat

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 26

Glimpse: Diode Model in MAPP

● executable (in Matlab)

● takes 10min to write

● works in all analyses

MOD.terminalsMOD.parmsMOD.explicit_outsMOD.f: function handleMOD.q: function handle…

MODSPECformat

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 27

MAPP: Compact Model Prototyping

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 28

FEFET: Char Curves, Inverter Ferro-electrical FET (negative cap. gate)

» modified MVS model by Dimitri Antoniadis (MIT)– Unpublished work

» homotopy needed to capture -ve res. region

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 29

FEFET: Char Curves, Inverter Ferro-electrical FET (negative cap. gate)

» modified MVS model by Dimitri Antoniadis (MIT)– Unpublished work

» homotopy needed to capture -ve res. region

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 30

Landau-Lifshitz-Gilbert (LLG) Model: Spin-Torque Devices

Three dimensional oscillator – rotation of magnetization in response to torques

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 31

MAPP's Multi-Physics Capabilities

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 32

MAPP's Multi-Physics Capabilities

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

Electronics Electronics

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 33

MAPP's Multi-Physics Capabilities

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

Electronics ElectronicsOptics Optics

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 34

MAPP's Multi-Physics Capabilities

Networks in different physical domains supported» via domain-specific Equation Engines

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

Electronics ElectronicsOptics Optics

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 35

MAPP's Multi-Physics Capabilities

Networks in different physical domains supported» via domain-specific Equation Engines

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

Electronics ElectronicsOptics Optics

Opto-Electronics

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 36

MAPP's Multi-Physics Capabilities

Networks in different physical domains supported» via domain-specific Equation Engines

Domains interact via devices with multiple Network Interface Layers (NILs)

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

Electronics ElectronicsOptics Optics

Opto-Electronics

ModSpec Core(Equations)

Electrical

Electrical

Network Interface Layer

node voltages, branch currents,

KCL, KVL

MechanicalMechanicalNILNIL

SpintronicSpintronicNILNIL

BiochemicalBiochemicalNILNIL

ThermalThermalNILNIL

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 37

MAPP's Multi-Physics Capabilities

Networks in different physical domains supported» via domain-specific Equation Engines

Domains interact via devices with multiple Network Interface Layers (NILs)

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

Electronics ElectronicsOptics Optics

Opto-Electronics

ModSpec Core(Equations)

Electrical

Electrical

Network Interface Layer

node voltages, branch currents,

KCL, KVL

MechanicalMechanicalNILNIL

SpintronicSpintronicNILNIL

BiochemicalBiochemicalNILNIL

ThermalThermalNILNIL

opto-electronicdevices

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 38

MAPP's Multi-Physics Capabilities

Networks in different physical domains supported» via domain-specific Equation Engines

Domains interact via devices with multiple Network Interface Layers (NILs)

Master Equation Engine orchestrates domain-specific Engines to produce multi-physics system DAEs

photo-detector

Mach-Zehnderelectro-optical modulator

combiner

multi-modefiber

multi-modefiber

splitterlaser

Electronics ElectronicsOptics Optics

Opto-Electronics

ModSpec Core(Equations)

Electrical

Electrical

Network Interface Layer

node voltages, branch currents,

KCL, KVL

MechanicalMechanicalNILNIL

SpintronicSpintronicNILNIL

BiochemicalBiochemicalNILNIL

ThermalThermalNILNIL

opto-electronicdevices

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 39

MAPP Model Development Flow (2)

ModSpec Model(in MATLAB)hand-coded

Step 1: model developed in ModSpec/MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 40

translate manually

to NEEDS-compatible Verilog-A

Step 2

NEEDS-compatibleVerilog-A model

MAPP Model Development Flow (2)

ModSpec Model(in MATLAB)hand-coded

Step 1: model developed in ModSpec/MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 41

translate manually

to NEEDS-compatible Verilog-A

Step 2

NEEDS-compatibleVerilog-A model

MAPP Model Development Flow (2)

ModSpec Model(in MATLAB)hand-coded

ModSpec Model(in MATLAB)

auto-generatedfrom Verilog-A

automatic translator

Step 1: model developed in ModSpec/MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 42

translate manually

to NEEDS-compatible Verilog-A

Step 2

double-checkin MAPP

compare code, check consistency

NEEDS-compatibleVerilog-A model

MAPP Model Development Flow (2)

ModSpec Model(in MATLAB)hand-coded

ModSpec Model(in MATLAB)

auto-generatedfrom Verilog-A

automatic translator

Step 1: model developed in ModSpec/MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 43

end of Step 2: high level of confidence Verilog-A model is correct/debugged

translate manually

to NEEDS-compatible Verilog-A

Step 2

double-checkin MAPP

compare code, check consistency

NEEDS-compatibleVerilog-A model

MAPP Model Development Flow (2)

ModSpec Model(in MATLAB)hand-coded

ModSpec Model(in MATLAB)

auto-generatedfrom Verilog-A

automatic translator

Step 1: model developed in ModSpec/MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 44

end of Step 2: high level of confidence Verilog-A model is correct/debugged

translate manually

to NEEDS-compatible Verilog-A

Step 2

double-checkin MAPP

compare code, check consistency

NEEDS-compatibleVerilog-A model

MAPP Model Development Flow (2)

ModSpec Model(in MATLAB)hand-coded

ModSpec Model(in MATLAB)

auto-generatedfrom Verilog-A

automatic translator

Step 1: model developed in ModSpec/MAPP

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 45

Verilog-A to ModSpec Translation

Verilog-AModel VAPP

ModSpecModel

(MATLAB)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 46

Verilog-A to ModSpec Translation

Verilog-AModel VAPP

ModSpecModel

(MATLAB)

● DAE formulation ● Semantic checking

● Check good coding practices ● Auto Diff or hardcoded Jacobians

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 47

Verilog-A to ModSpec Translation

Verilog-A VAPP ModSpec

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 48

Verilog-A to ModSpec Translation

Verilog-A ModSpecAST IR-1 IR-2

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 49

Verilog-A to ModSpec Translation

Verilog-A ModSpecAST IR-1 IR-2

I(p,n) <+ G*V(p,n)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 50

Verilog-A to ModSpec Translation

Verilog-A ModSpecAST IR-1 IR-2

<+

I

p n

*

G V

p n

I(p,n) <+ G*V(p,n) ● Start with tokens

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 51

Verilog-A to ModSpec Translation

Verilog-A ModSpecAST IR-1 IR-2

Contribution

IO Math

IO

I(p,n) <+ G*V(p,n) ● Start with tokens● Contract representation into more abstract direction.● Create objects and link them

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 52

Verilog-A to ModSpec Translation

Verilog-A ModSpecAST IR-1 IR-2

ContributionlhsIOrhsIOsIsExplicitDiffEqnprint

ModelIOsParmsTerminalsprint

I(p,n) <+ G*V(p,n) ● Start with tokens● Contract representation into more abstract direction.● Create objects and link them● Top level objects directly related to ModSpec internals

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 53

Verilog-A to ModSpec Translation

Verilog-A ModSpecAST IR-1 IR-2

ContributionlhsIOrhsIOsIsExplicitDiffEqnprint

ModelIOsParmsTerminalsprint

I(p,n) <+ G*V(p,n) ● Start with tokens● Contract representation into more abstract direction.● Create objects and link them● Top level objects directly related to ModSpec internals

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 54

Glimpse: Verilog-A → ModSpec Translator

Verilog-AModSpec (MATLAB)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 55

Glimpse: Verilog-A → ModSpec Translator

Verilog-AModSpec (MATLAB)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 56

Glimpse: Verilog-A → ModSpec Translator

Verilog-AModSpec (MATLAB)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 57

MAPP Model Development Flow (3)

Step 3

NEEDS-compatibleVerilog-A model

(from Step 2)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 58

automatictranslator

MAPP Model Development Flow (3)

Step 3

NEEDS-compatibleVerilog-A model

(from Step 2)

ModSpecModel

(C++ API)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 59

automatictranslator

confirmmodel with

DC/AC/TRANin C++ MAPP

MAPP Model Development Flow (3)

Step 3

NEEDS-compatibleVerilog-A model

(from Step 2)

proof of modelgoodness

ModSpecModel

(C++ API)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 60

automatictranslator

confirmmodel with

DC/AC/TRANin C++ MAPP

MAPP Model Development Flow (3)

Step 3

NEEDS-compatibleVerilog-A model

(from Step 2)

proof of modelgoodness model supported

in Open-sourceSimulators

(Xyce)

ModSpecModel

(C++ API)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 61

automatictranslator

confirmmodel with

DC/AC/TRANin C++ MAPP

MAPP Model Development Flow (3)

Step 3

NEEDS-compatibleVerilog-A model

(from Step 2)

use modelin Commercial

Simulators

proof of modelgoodness model supported

in Open-sourceSimulators

(Xyce)

ModSpecModel

(C++ API)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 62

“simulation-ready” model deployed

automatictranslator

confirmmodel with

DC/AC/TRANin C++ MAPP

MAPP Model Development Flow (3)

Step 3

NEEDS-compatibleVerilog-A model

(from Step 2)

use modelin Commercial

Simulators

proof of modelgoodness model supported

in Open-sourceSimulators

(Xyce)

ModSpecModel

(C++ API)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 63

“simulation-ready” model deployed

automatictranslator

confirmmodel with

DC/AC/TRANin C++ MAPP

MAPP Model Development Flow (3)

Step 3

NEEDS-compatibleVerilog-A model

(from Step 2)

use modelin Commercial

Simulators

proof of modelgoodness model supported

in Open-sourceSimulators

(Xyce)

ModSpecModel

(C++ API)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 64

Glimpse: ModSpec Model in Xyce

ModSpec Model(C++ API)

model supported in Xyce

.so libraries(dynamically loadable)

compile standalone

Xyce-ModSpecInterface

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 65

Glimpse: ModSpec Model in Xyce

1 *** Test-bench for generting dc response of an inverter 2 3 *** Creat sub-circuit for the inverter 4 .subckt inverter Vin Vout Vvdd Vgnd 5 6 yModSpec_Device X1 Vvdd Vin Vout Vvdd MVSmod type=-1 W=1.0e-4 7 Lgdr=32e-7 dLg=8e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 8 Cif = 1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 9 CTM_select=1 Rs0=100 Rd0 = 100 n0=1.68 nd=0.1 vxo=7542204 10 mu=165 Vt0=0.5535 delta=0.15 11 12 yModSpec_Device X0 Vout Vin Vgnd Vgnd MVSmod type=1 W=1e-4 13 Lgdr=32e-7 dLg=9e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 14 Cif=1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 15 CTM_select=1 Rs0=100 Rd0=100 n0=1.68 nd=0.1 vxo=1.2e7 16 mu=200 Vt0=0.4 delta=0.15 17 18 .model MVSmod MODSPEC_DEVICE SONAME=MVS_ModSpec_Element.so 19 20 .ends 21 22 *** circuit layout 23 Vsup sup 0 1 24 Vin in 0 0 25 Vsource source 0 0 26 X2 in out sup 0 inverter 27 28 *** simulation 29 .dc Vin 0 1 0.01 30 31 .print dc V(in) V(out) 32 *** END 33 .end

Xyce netlist for inverter(using MVS ModSpec/C++ model)

ModSpec Model(C++ API)

model supported in Xyce

.so libraries(dynamically loadable)

compile standalone

Xyce-ModSpecInterface

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 66

Glimpse: ModSpec Model in Xyce

1 *** Test-bench for generting dc response of an inverter 2 3 *** Creat sub-circuit for the inverter 4 .subckt inverter Vin Vout Vvdd Vgnd 5 6 yModSpec_Device X1 Vvdd Vin Vout Vvdd MVSmod type=-1 W=1.0e-4 7 Lgdr=32e-7 dLg=8e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 8 Cif = 1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 9 CTM_select=1 Rs0=100 Rd0 = 100 n0=1.68 nd=0.1 vxo=7542204 10 mu=165 Vt0=0.5535 delta=0.15 11 12 yModSpec_Device X0 Vout Vin Vgnd Vgnd MVSmod type=1 W=1e-4 13 Lgdr=32e-7 dLg=9e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 14 Cif=1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 15 CTM_select=1 Rs0=100 Rd0=100 n0=1.68 nd=0.1 vxo=1.2e7 16 mu=200 Vt0=0.4 delta=0.15 17 18 .model MVSmod MODSPEC_DEVICE SONAME=MVS_ModSpec_Element.so 19 20 .ends 21 22 *** circuit layout 23 Vsup sup 0 1 24 Vin in 0 0 25 Vsource source 0 0 26 X2 in out sup 0 inverter 27 28 *** simulation 29 .dc Vin 0 1 0.01 30 31 .print dc V(in) V(out) 32 *** END 33 .end

Xyce netlist for inverter(using MVS ModSpec/C++ model)

ModSpec Model(C++ API)

model supported in Xyce

.so libraries(dynamically loadable)

compile standalone

Xyce-ModSpecInterface

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 67

Glimpse: ModSpec Model in Xyce

1 *** Test-bench for generting dc response of an inverter 2 3 *** Creat sub-circuit for the inverter 4 .subckt inverter Vin Vout Vvdd Vgnd 5 6 yModSpec_Device X1 Vvdd Vin Vout Vvdd MVSmod type=-1 W=1.0e-4 7 Lgdr=32e-7 dLg=8e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 8 Cif = 1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 9 CTM_select=1 Rs0=100 Rd0 = 100 n0=1.68 nd=0.1 vxo=7542204 10 mu=165 Vt0=0.5535 delta=0.15 11 12 yModSpec_Device X0 Vout Vin Vgnd Vgnd MVSmod type=1 W=1e-4 13 Lgdr=32e-7 dLg=9e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 14 Cif=1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 15 CTM_select=1 Rs0=100 Rd0=100 n0=1.68 nd=0.1 vxo=1.2e7 16 mu=200 Vt0=0.4 delta=0.15 17 18 .model MVSmod MODSPEC_DEVICE SONAME=MVS_ModSpec_Element.so 19 20 .ends 21 22 *** circuit layout 23 Vsup sup 0 1 24 Vin in 0 0 25 Vsource source 0 0 26 X2 in out sup 0 inverter 27 28 *** simulation 29 .dc Vin 0 1 0.01 30 31 .print dc V(in) V(out) 32 *** END 33 .end

model's name model parameter:name of .so library

.model line

Xyce netlist for inverter(using MVS ModSpec/C++ model)

ModSpec Model(C++ API)

model supported in Xyce

.so libraries(dynamically loadable)

compile standalone

Xyce-ModSpecInterface

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 68

Glimpse: ModSpec Model in Xyce

1 *** Test-bench for generting dc response of an inverter 2 3 *** Creat sub-circuit for the inverter 4 .subckt inverter Vin Vout Vvdd Vgnd 5 6 yModSpec_Device X1 Vvdd Vin Vout Vvdd MVSmod type=-1 W=1.0e-4 7 Lgdr=32e-7 dLg=8e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 8 Cif = 1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 9 CTM_select=1 Rs0=100 Rd0 = 100 n0=1.68 nd=0.1 vxo=7542204 10 mu=165 Vt0=0.5535 delta=0.15 11 12 yModSpec_Device X0 Vout Vin Vgnd Vgnd MVSmod type=1 W=1e-4 13 Lgdr=32e-7 dLg=9e-7 Cg=2.57e-6 beta=1.8 alpha=3.5 Tjun=300 14 Cif=1.38e-12 Cof=1.47e-12 phib=1.2 gamma=0.1 mc=0.2 15 CTM_select=1 Rs0=100 Rd0=100 n0=1.68 nd=0.1 vxo=1.2e7 16 mu=200 Vt0=0.4 delta=0.15 17 18 .model MVSmod MODSPEC_DEVICE SONAME=MVS_ModSpec_Element.so 19 20 .ends 21 22 *** circuit layout 23 Vsup sup 0 1 24 Vin in 0 0 25 Vsource source 0 0 26 X2 in out sup 0 inverter 27 28 *** simulation 29 .dc Vin 0 1 0.01 30 31 .print dc V(in) V(out) 32 *** END 33 .end

model's name model parameter:name of .so library

.model line

Xyce netlist for inverter(using MVS ModSpec/C++ model)

ModSpec Model(C++ API)

model supported in Xyce

.so libraries(dynamically loadable)

compile standalone

Xyce-ModSpecInterface

DC sweep using Xyce

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 69

Glimpse: ModSpec models in Xyce

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 70

Glimpse: ModSpec models in Xyce

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 71

Glimpse: ModSpec models in Xyce

20 ModSpec BJTs

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 72

Glimpse: ModSpec models in Xyce

20 ModSpec BJTs

Xyce-ModSpec-Interface supportsvoltage limiting (e.g., pnjlim, fetlim, limvds)

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 73

Glimpse: ModSpec models in Xyce

20 ModSpec BJTsmultiple ModSpec models in one netlist

Xyce-ModSpec-Interface supportsvoltage limiting (e.g., pnjlim, fetlim, limvds)

T. Wang and J. Roychowdhury, University of California at Berkeley Slide 74

Glimpse: ModSpec models in Xyce

20 ModSpec BJTsruns in other analyses as well, e.g., HB.

multiple ModSpec models in one netlist

Xyce-ModSpec-Interface supportsvoltage limiting (e.g., pnjlim, fetlim, limvds)

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 75

MAPP: Features

Works entirely in MATLAB Help system (start with help MAPP) Automatic differentiation (vecvalder) Executable device specification (ModSpec) DC, AC, transient analyses

» also noise, homotopy, HB, shooting, PPV, MOR, etc. (not released yet)

Automated testing system exercising suite of tests Verilog-A model translator (VAPP) Xyce – ModSpec interface

A. Gokcen Mahmutoglu, amahmutoglu@berkeley.edu Slide 76

Summary

http://MAPP.eecs.berkeley.edu