meljun cortes combinational circuits (part 1)
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8/8/2019 MELJUN CORTES Combinational Circuits (Part 1)
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the resulting circuit when combinational logic isconverted into a physical entity
CombinationalCircuit
outputs are determined by the inputs alone atthe present time
Procedure in Designing the circuit:
Step 1: Determine the input and outputrequirements
Step 2: Obtain the truth table based on the input-output requirements; and/or
Derive the Boolean expression of each of
the outputs based on the input output
Combinational Circuits (Part 1) * Property of STI Page 1 of 26
Step 3: Simplify the Boolean expressionStep 4: Derive the logic diagram based on thesimplified Boolean expression
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a combinational circuit that performs theaddition of two bits
Half Adder
from the two bits (0 or 1), form all possiblecombinations of how they can be added
Step 1: Determine the input and outputrequirements
Combinational Circuits (Part 1) * Property of STI Page 2 of 26
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Step 2: Rewrite the results in a table:
Half Adder
Derive the Boolean expression of each of
the outputs based on the input outputrelationship
Combinational Circuits (Part 1) * Property of STI Page 3 of 26
sum = x’y + xy’
carry = xy
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Step 3: Simplify the Boolean expression
The Boolean ex ression above is alread
Half Adder
in its simplest formStep 4: Draw the logic diagram
Combinational Circuits (Part 1) * Property of STI Page 4 of 26
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direct extension of the half-adder
erforms additions of three bits
Full Adder
procedures are similar to that of the half-adder
Step 1: Determine the input and outputrequirements
Name the bits: x , y , and z
Enumerate all possible combinations
that can result from the addition of thethree bits
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Step 2: Obtain the truth table and Booleanexpression
Full Adder
Derive the Boolean expression of each ofthe outputs based on the input output
Combinational Circuits (Part 1) * Property of STI Page 6 of 26
sum = x’y’z + x’yz’ + xy’z’ + xyz = z Å (x Å y )
carry = xy + xz + yz
Step 3: Simplify the Boolean expression
Simplification of the above expression is
not needed
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Step 4: Draw the logic diagram
Full Adder
Combinational Circuits (Part 1) * Property of STI Page 7 of 26
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inputs are manipulated in binary forms butoutputs are determined by their equivalent
Decimal Adder
decimal value adds two decimal digits
Decimal number
represented by four bits, with the following
equivalent decimal weight:
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Step 1: Determine the input and outputrequirements
Decimal Adder
there are 8 inputs - to represent twodecimal numbers, you need two sets of
four bits
form all possible combinations of howthe two decimal numbers can be added
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Decimal Adder
Combinational Circuits (Part 1) * Property of STI Page 10 of 26
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Decimal Adder
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Step 2: Choose from two ways of implementingthe combinational circuit required:
Decimal Adder
generate a truth table that will show therelationship of the output bits with the
input bits; or
use the principle of the full-adder to comeup with an easier implementation of thedecimal adder
Make use of the 4-bit binary (full)-adderyielding 5 bits of output.
Note: Define only a circuit that will
convert the output of the binary addition tocorresponding decimal output
Combinational Circuits (Part 1) * Property of STI Page 12 of 26
Comparison of the binary sum and the
corresponding binary coded decimalequivalent
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Decimal Adder
Combinational Circuits (Part 1) * Property of STI Page 13 of 26
For decimal sums 10 to 18, correction needs to be done:
Whenever binary sum bit K is 1, a correction must be made;and
Whenever binary sum bits B 3 and B 2 are equal to 1, acorrection must be made;
Whenever binary sum bits B 3 and B 1 are equal to 1, a
correction must be made.
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The output bit carry is defined as follows:
Out ut Carr = K + B 3B 2 + B 3B 1
Decimal Adder
Circuit implementation of the BCD Adder
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a combinational circuit that subtracts two binarynumbers
BinarySubtractor
Step 1: Determine the input and outputrequirements
inputs - two, with 4 bits each = 8variables
outputs - requires a minimum of 4 bitsand another bit that will verify if theoperation is successful or not = 5variables
Step 2: Obtain the truth table based on the input- output requirements
Combinational Circuits (Part 1) * Property of STI Page 15 of 26
the difference of the input numbers range
between 0 and F to represent hexadecimal numbers 8 to F in its binary equivalent, we need 4 bits
Step 3: Simplify the Boolean expression or truthtable
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Subtracting binary numbers using
Binary Complements:
BinarySubtractor
(1) R ’s complement = r n – N for N ¹ 0 Equation 1where N is the given number,
r is the base of the number N , and
n is the number of decimal places representing theintegral part of the number N
(2) (R -1)’s complement = r n – r -m - N for N ¹ 0Equation 2
where N is the given number,
r is the base of the number N , and
n is the number of decimal places representing theintegral part of the number N
m is the number of decimal places representing thefractional part of the number N
Combinational Circuits (Part 1) * Property of STI Page 16 of 26
r ’s complement r = 2
2’s complement 2n – N Equation 3
(r -1)’s complement r = 2
1’s complement
2n – 20 – N = 2n – 1 – N Equation 4
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A – B ? = A + (2’s complement of B )
? = A + (2n – B )
BinarySubtractor
? = A + 2n
– B ? = 2n + (A – B )
To balance this equation we shall have to add2n to the left side of the equation, as shownbelow:
A – B + 2n = 2n + (A – B ) Equation 5
Step 4: Draw the logic diagram based on thesimplified Boolean expression
Combinational Circuits (Part 1) * Property of STI Page 17 of 26
Circuit implementation of the Binary Adder
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Example 1:
Given two binar numbers, show how binar
BinarySubtractor
subtraction is performed using complements:
Solution:
Step 1 Get the 1’s complement of thesubtrahend
1001’s 1’s complement = 0110
Step 2 Get the 2’s complement of 1001
’
Combinational Circuits (Part 1) * Property of STI Page 18 of 26
0110 + 0001 = 0111Step 3 Add the 2’s complement of the
subtrahend (0111) to the minuend
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Example 2:
Given two binar numbers, show how binar
BinarySubtractor
subtraction is performed using complements:
Solution:
Step 1 Get the 1’s complement of thesubtrahend
0111’s 1’s complement = 1000
Step 2 Get the 2’s complement of 0111
’
Combinational Circuits (Part 1) * Property of STI Page 19 of 26
1000 + 0001 = 1001Step 3 Add the 2’s complement of the
subtrahend (1001) to the minuend
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takes two inputs and determines whether thefirst number is greater than , equal to or less
MagnitudeComparator
than the second input thus, it has three outputs
Step 1: The magnitude comparator has two 1-bitinputs
Step 2: The possible combinations are as follows:
Combinational Circuits (Part 1) * Property of STI Page 20 of 26
Step 3: Observe that it has three outputs:
G A > B
E A = B
L A < B
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Step 4: Define the relationship of the input bits tothe output bits.
MagnitudeComparator
The output G is equal to ‘1’ only when Ais ‘1’ and B is ‘0’.
The output E is equal to ‘1’ when both A
and B are ‘0’ or ‘1’.
The output L is equal to ‘1’ only when Ais ‘0’ and B is ‘1’.
G = AB ’ E = AB + A’B ’ L = A’B
Circuit Implementation of the Single-BitMagnitude Comparator
Combinational Circuits (Part 1) * Property of STI Page 21 of 26
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Now, implement a 2-bit magnitude comparator:
MagnitudeComparator
Step 1: The 2-bit magnitude comparator has two2-bit inputs
Step 2: The possible combinations are as follows:
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The Three outputs:
G Input #1 > Input #2
MagnitudeComparator
E Input #1 = Input #2L Input #1 < Input #2
Define the relationship of the input bits to the output bits.
The cases for which the output G is equal to ‘1’ aredefined by the minterms: A’BX’Y’ , AB’X’Y’ , AB’X’Y ,ABX’Y’ , ABX’Y , ABXY’ .
G = A’BX’Y’ + AB’X’Y’ + AB’X’Y + ABX’Y’ + ABX’Y + ABXY’
Step 3: Simplify the equation using K-Map
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The cases for which the output E is equal to ‘1’are defined by the minterms: A’B’X’Y’ , A’BX’Y ,
MagnitudeComparator
AB’XY’ , ABXY .E = A’B’X’Y’ + A’BX’Y + AB’XY’ + ABXY
A K-map is also used for this output but it can
be seen that the expression above is alreadysimplified as it is.
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The cases for which the output L is equal to ‘1’are defined by the minterms: A’B’XY’ , A’B’XY’ ,
’ ’ ’ ’ ’ ’
MagnitudeComparator
, , , .
L = A’B’X’Y + A’B’XY’ + A’B’XY + A’BXY’ + A’BXY +AB’XY
Based on the K-map below, it is still possible tosimplify the expression above by observing themap below. After simplification for the output, L
is:
L = B’XY + A’B’Y + A’X
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Step 3: Draw the combinational circuitcorresponding to the simplified equations
MagnitudeComparator
Circuit Implementation of the 2-Bit
Magnitude Comparator
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