modern vlsi design 4e: chapter 5 copyright 2008 wayne wolf topics n sequential machine...

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Topics

Sequential machine implementation:– clocking.

Sequential machine design.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Sequential machine design

Two ways to specify sequential machine:– structure: interconnection of logic gates and

memory elements.– function: Boolean description of next-state and

output functions. Best way depends on type of machine being

described.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Counter

Easy to specify as one-bit counter. Harder to specify n-bit counter behavior.

Can specify n-bit counter as structure made of 1-bit counters.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

One-bit counter

Truth table:

count Cin next Cout

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

One-bit counter implementation

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

One-bit counter operation

All operations are performed as s2.

XOR computes next value of this bit of counter.

NAND/inverter compute carry-out.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

One-bit counter sticks

l1(latch) n(NAND) i(INV) x(XOR) l2(latch)

Cin

Cout

VDD

VSS

1 1’ 2 2’

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

n-bit counter structure

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

State transition graphs/tables

Basic functional description of FSM. Symbolic truth table for next-state, output

functions:– no structure of logic;– no encoding of states.

State transition graph and table are functionally equivalent.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

01 string recognizer

Behavior of machine which recognizes “01” in continuous stream of bits:

time 0 1 2 3 4 5

input 0 0 1 1 0 1

state bit1 bit2 bit2 bit1 bit1 bit2

next bit2 bit2 bit1 bit1 bit2 bit1

output 0 0 1 0 0 1

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

01 recognizer operation

Waits for 0 to appear in state bit1. Goes into separate state bit2 when 0

appears. If 1 appears immediately after 0, can’t have

a 01 on next cycle, so can go back to wait for 0 in state bit1.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

State transition table

Symbolic state transition table:

input present next output

0 bit1 bit2 0

1 bit1 bit1 0

0 bit2 bit2 0

1 bit2 bit1 1

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

State transition graph

Equivalent to state transition table:

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

State assignment

Must find binary encoding for symbolic states—state assignment.

Choice of state assignment directly affects both the next-state and output logic:– area;– delay.

May also encode some machine inputs/outputs.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

01 recognizer encoding

Choose bit1= 0, bit2 = 1:

input present next output

0 0 1 0

1 0 0 0

0 1 1 0

1 1 0 1

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Logic implementation

After encoding, truth table can be implemented in gates:

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Traffic light controller

Intersection of two roads:– highway (busy);– farm (not busy).

Want to give green light to highway as much as possible.

Want to give green to farm when needed. Must always have at least one red light.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Traffic light system

highway

farm road

sensor

trafficlight

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

System operation

Sensor on farm road indicates when cars on farm road are waiting for green light.

Must obey required lengths for green, yellow lights.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Traffic light machine

Build controller out of two machines:– sequencer which sets colors of lights, etc.– timer which is used to control durations of

lights. Separate counter isolates logical design

from clock period. Separate counter greatly reduces number of

states in sequencer.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Sequencer state transition graph

hwy-green

farm-green

hwy-yellow

farm-yellow

(cars & long)’ / 0 green red

cars & long / 1 green red

short’ / 0 yellow red

short / 1 yellow red

cars & long’ / 0 green red

cars’ & long / 1 green red

short’ / 0 red yellow

short/ 1 red yellow