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Chapter 1: Introduction1-1
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Princip ios de Arquitectur a de ComputadorasMiles Murdocca y Vincent Heuring
Capitulo 1: Introduc ción
Chapter 1: Introduction1-2
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Conten ido del Capítulo1.1 Introducción. Planteo General1.2 Una Breve Historia1.3 El modelo de Von Neumann1.4 El Modelo de Interconexión a través de Bus1.5 Niveles de Máquina1.6 Compatibili dad hacia Arriba1.7 Los Niveles1.8 Un Sistema de Computación Típico
Chapter 1: Introduction1-3
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Algunas Defini cion es• La Arquitectura de comput adoras trata sobre el comportamiento
funcional de un sistema de computación visto por un programador(en aspectos tales como que un número entero ocupa 32 bits ).
• La organización de computadoras muestra relaciones estructuralesno visible s para un program ador (tales como la frecuencia de relojo el tamaño físico de la memoria).
• Existe un concepto de niveles en la arquitectur a de computadoras.La idea es que una computadoras básica puede estudiarse en basea diferentes niveles. Desde el nivel alto en el que el usuario correprogram as, al nivel mas bajo, donde existen transistor es y cables.
Chapter 1: Introduction1-4
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Maquina calculadora de Pascal• Realizaba operaciones aritméticas básicas(a mediados del 1600).
No tenía elementos básicos para considerarla una computadora.
• Recién despues que Babbage (1800) introdujo los conceptos de control y cálculo mecánic o en una misma máquina se pudo reco-nocer en ellas partes básicas de una computadora digital actual.
(Fuente: IBMFotografía de Archivo.
Chapter 1: Introduction1-5
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
U.de EntradaUnidad de
Aritmetica y logica(ALU)
U.de Salida
Unidad de Memoria
U.de Control
El Modelo de von Neumann• El modelo de Von Neumann está formado por 5 elementos principales:(1) uni dad de entrada; (2) uni dad de salida; (3) unidad aritm étic o-lógic a
(4) uni dad de memoria; (5) unidad de control.
Chapter 1: Introduction1-6
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Syst
em B
us
Bus de Datos
Bus de Direcciones
Bus de Control
(ALU, Registros,
y Control)
Memoria Entrada y Salida (I/O)
CPU
El modelo de Interconexión de Bus • Una mejora al modelo de von Neumann , es el modelo de bus que
tiene una CPU (ALU y control), memor ia, y unidades entrada/salida.
• La Comunica ción entre component es es manejada por un caminocompartido llamado bus del sistema, formado por los buses de datos, direcciones, y control. Tambien hay un bus de energia. Algunas arquitectur as pueden tener tambien un bus I/O separado.
Chapter 1: Introduction1-7
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Alto Nivel
Lenguajes de Alto Nivel
Nivel de Usuario: ProgramasAplicaciones
Bajo Nivel
U.Funcionales (Memoria, ALU, etc.)
Compuertas Logicas
Transistores y Cables
Lenguaje ensamblador/Codigo maquina
Control Microprogramado / Cableado
Niveles de las Maquinas• Hay un número de niveles en una computadora (depende del autor)
que va desde el nivel del usuario, hasta el nivel de transistor .
• Avanzando desde arriba hacia abajo, los niveles se hacen menosabstract os a medida que la estructura interna de la computadorase hace visible.
Chapter 1: Introduction1-8
Principios de Arquitectura de Computadoras por M. Murdocca y V. Heuring © 1999 M. Murdocca and V. Heuring
Monitor
Drive de CD-ROM
Drive de Disco Duro
Teclado
Ranuras para memorias internas
CPU (Microprocesador debajo del disipador de calor
Ranuras para conectar Tarjetas de expansión
Drive de Diskette
Una Computadora Típica
Chapter 1: Introduction1-9
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Memory
Input / output
Battery
Plug-in expansion card slots
Power supply connector
Pentium II processor slot (ALU/control)
La Placa Madre • Los cinco componentes de von Neumann se ven claramente en esta
Placa Madre, en el contexto del modelo de interconexión por bus.
(Source: TYAN Computer,http://www.tyan.com)
Chapter 1: Introduction1-10
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Manchester University Mark I• Las Supercomput adoras, que se fabrican en pequeñas cantidades y
con un precio elevado, están siendo reemplazadas por máquinas deproducción masiva, bajo precio y mejor relación costo/rendimiento.
(Source: http://www.paralogos.com/DeadSuper)
Chapter 1: Introduction1-11
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Ley de Moore
• A igual precio las computadoras duplican su potencia cada 18 meses.
• Esta observacion debe considerarse seriamente : Una innovacion en la arquitectura que se hace para obtener un rendimiento cuadrupleen tres años puede llegar a ser irrelevante: Las arquitecturas queexistan para entonces tal vez ya ofrezcan un cuadruple rendimientoy verse totalmente diferentes para cuando la modificacion se espe-raba que estuviera disponible
Chapter 2: Data Representation2-1
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Principles of Computer ArchitectureMiles Murdocca and Vincent Heuring
Chapter 2: Data Representation
Chapter 2: Data Representation2-2
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Chapter Contents2.1 Introduction2.2 Fixed Point Numbers2.3 Floating Point Numbers2.4 Case Study: Patriot Missile Defense Failure Caused by Loss of
Precision2.5 Character Codes
Chapter 2: Data Representation2-3
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Fixed Point Numbers• Using only two digits of precision for signed base 10 numbers,
the range (interval between lowest and highest numbers) is[-99, +99] and the precision (distance between successive num-bers) is 1.
• The maximum error , which is the difference between the value of areal number and the closest representable number, is 1/2 the pre-cision. For this case, the error is 1/2 × 1 = 0.5.
• If we choose a = 70, b = 40, and c = -30, then a + (b + c) = 80 (whichis correct) but (a + b) + c = -30 which is incorrect. The problem isthat (a + b) is +110 for this example, which exceeds the range of+99, and so only the rightmost two digits (+10) are retained in theintermediate result. This is a problem that we need to keep inmind when representing real numbers in a finite representation.
Chapter 2: Data Representation2-4
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Weighted Position Code• The base, or radix of a number system defines the range of pos-
sible values that a digit may have: 0 – 9 for decimal; 0,1 for binary.
• The general form for determining the decimal value of a number isgiven by:
Example:
541.2510 = 5 × 102 + 4 × 101 + 1 × 100 + 2 × 10-1 + 5 × 10-2
= (500)10 + (40)10 + (1)10 + (2/10)10 + (5/100)10
= (541.25)10
Chapter 2: Data Representation2-5
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Base Conversion with the RemainderMethod
• Example: Convert 23.375 10 to base 2. Start by converting the inte-ger portion:
23/2 = 11 R 1
11/2 = 5 R 1
5/2 = 2 R 1
2/2 = 1 R 0
1/2 = 0 R 1
Integer Remainder
Least significant bit
Most significant bit
(23)10 = (10111)2
Chapter 2: Data Representation2-6
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Base Conversion with the Multiplica-tion Method
• Now, convert the fraction:
.375 × 2 = 0.75
.75 × 2 = 1.50
.5 × 2 = 1.00
Least significant bit
Most significant bit
(.375)10 = (.011)2
• Putting it all together, 23.375 10 = 10111.0112.
Chapter 2: Data Representation2-7
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Nonterminating Base 2 Fraction• We can’t always convert a terminating base 10 fraction into an
equivalent terminating base 2 fraction:
.2
.4
.8
.6
.2
.
.
.
0.4
0.8
1.6
1.2
0.4
=
=
=
=
=
2
2
2
2
2
×
×
×
×
×
Chapter 2: Data Representation2-8
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Base 2, 8, 10, 16 Number Systems
• Example: Show a column for ternary (base 3). As an extension ofthat, convert 14 10 to base 3, using 3 as the divisor for the remain-der method (instead of 2). Result is 112 3
Binary(base 2)
01
1011
100101110111
10001001101010111100110111101111
Octal(base 8)
01234567
1011121314151617
Decimal(base 10)
0123456789
101112131415
Hexadecimal(base 16)
0123456789ABCDEF
Chapter 2: Data Representation2-9
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
More on Base Conversions• Converting among power-of-2 bases is particularly simple:
10112 = (102)(112) = 234
234 = (24)(34) = (102)(112) = 10112
1010102 = (1012)(0102) = 528
011011012 = (01102)(11012) = 6D16
• How many bits should be used for each base 4, 8, etc. , digit? Forbase 2, in which 2 = 2 1, the exponent is 1 and so one bit is usedfor each base 2 digit. For base 4, in which 4 = 2 2, the exponent is2, so so two bits are used for each base 4 digit. Likewise, for base8 and base 16, 8 = 2 3 and 16 = 24, and so 3 bits and 4 bits are usedfor base 8 and base 16 digits, respectively.
Chapter 2: Data Representation2-10
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Binary Addition• This simple binary addition example provides background for the
signed number representations to follow.
Operands0
0+
00
SumCarry out
Carry in 0
0
1+
10
0
1
0+
10
0
1
1+
01
0
Example:
Carry
Addend: A
Augend: B
Sum
0 1 1 1 1 1 0 0
0 1 0 1 1 0 1 0
1 1 1 1 0 0 0 0
1 1 0 1 0 1 1 0
+
(124)10
(90)10
(214)10
0
0+
10
1
0
1+
01
1
1
0+
01
1
1
1+
11
1
Chapter 2: Data Representation2-11
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Signed Fixed Point Numbers• For an 8-bit number, there are 2 8 = 256 possible bit patterns.
These bit patterns can represent negative numbers if we chooseto assign bit patterns to numbers in this way. We can assign halfof the bit patterns to negative numbers and half of the bit patternsto positive numbers.
• Four signed representations we will cover are:
Signed Magnitude
One’s Complement
Two’ s Complement
Excess (Biased)
Chapter 2: Data Representation2-12
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Signed Magnitude• Also know as “sign and magnitude,” the leftmost bit is the sign (0
= positive, 1 = negative) and the remaining bits are the magnitude.
• Example:
+2510 = 000110012
-2510 = 100110012
• Two representations for zero: +0 = 00000000 2, -0 = 100000002.
• Largest number is +127, smallest number is -127 10, using an 8-bitrepresentation.
Chapter 2: Data Representation2-13
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
One’s Complement• The leftmost bit is the sign (0 = positive, 1 = negative). Negative of
a number is obtained by subtracting each bit from 2 (essentially,complementing each bit from 0 to 1 or from 1 to 0). This goes bothways: converting positive numbers to negative numbers, and con-verting negative numbers to positive numbers.
• Example:
+2510 = 000110012
-2510 = 111001102
• Two representations for zero: +0 = 00000000 2, -0 = 111111112.
• Largest number is +127 10, smallest number is -127 10, using an 8-bit representation.
Chapter 2: Data Representation2-14
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Two’s Complement• The leftmost bit is the sign (0 = positive, 1 = negative). Negative of
a number is obtained by adding 1 to the one’s complement nega-tive. This goes both ways, converting between positive and nega-tive numbers.
• Example (recall that -25 10 in one’s complement is 11100110 2):
+2510 = 000110012
-2510 = 111001112
• One representation for zero: +0 = 00000000 2, -0 = 000000002.
• Largest number is +127 10, smallest number is -128 10, using an 8-bit representation.
Chapter 2: Data Representation2-15
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Excess (Biased)• The leftmost bit is the sign (usually 1 = positive, 0 = negative).
Positive and negative representations of a number are obtainedby adding a bias to the two’s complement representation. Thisgoes both ways, converting between positive and negative num-bers. The effect is that numerically smaller numbers have smallerbit patterns, simplifying comparisons for floating point exponents.
• Example (excess 128 “adds” 128 to the two’s complement ver-sion, ignoring any carry out of the most significant bit) :
+1210 = 100011002
-1210 = 011101002
• One representation for zero: +0 = 10000000 2, -0 = 100000002.
• Largest number is +127 10, smallest number is -128 10, using an 8-bit representation.
Chapter 2: Data Representation2-16
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
BCD Representations in Nine’s andTen’s Complement
• Each binary coded decimal digit is composed of 4 bits.0 0 0 0
(0)10
0 0 1 1
(3)10
0 0 0 0
(0)10
0 0 0 1
(1)10
(+301)10
1 0 0 1
(9)10
0 1 1 0
(6)10
1 0 0 1
(9)10
1 0 0 0
(8)10
(–301)10
1 0 0 1
(9)10
0 1 1 0
(6)10
1 0 0 1
(9)10
1 0 0 1
(9)10
(–301)10
Nine’s complement
Ten’s complement
Nine’s and ten’s complement
(a)
(b)
(c)
• Example: Represent +079 10 in BCD: 0000 0111 1001
• Example: Represent -079 10 in BCD: 1001 0010 0001. This is ob-tained by first subtracting each digit of 079 from 9 to obtain thenine’s complement, so 999 - 079 = 920. Adding 1 produces theten’s complement: 920 + 1 = 921. Converting each base 10 digit of921 to BCD produces 1001 0010 0001.
Chapter 2: Data Representation2-17
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
3-Bit Signed Integer Representations
Chapter 2: Data Representation2-18
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Base 10 Floating Point Numbers• Floating point numbers allow very large and very small numbers
to be represented using only a few digits, at the expense of preci-sion. The precision is primarily determined by the number of dig-its in the fraction (or significand , which has integer and fractionalparts), and the range is primarily determined by the number ofdigits in the exponent.
• Example (+6.023 × 1023):
+
Sign
2 3 6 0 2
Exponent(two digits)
Significand (four digits)
Position of decimal point
3.
Chapter 2: Data Representation2-19
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Normalization• The base 10 number 254 can be represented in floating point form
as 254 × 100, or equivalently as:
25.4 × 101, or
2.54 × 102, or
.254 × 103, or
.0254 × 104, or
infinitely many other ways, which creates problems when makingcomparisons, with so many representations of the same number.
• Floating point numbers are usually normalized , in which the radixpoint is located in only one possible position for a given number.
• Usually, but not always, the normalized representation places theradix point immediately to the left of the leftmost, nonzero digit inthe fraction, as in: .254 × 103.
Chapter 2: Data Representation2-20
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Floating Point Example• Represent .254 × 103 in a normalized base 8 floating point format
with a sign bit, followed by a 3-bit excess 4 exponent, followed byfour base 8 digits.
• Step #1: Convert to the target base.
.254 × 103 = 25410. Using the remainder method, we find that 254 10= 376 × 80:
254/8 = 31 R 6
31/8 = 3 R 7
3/8 = 0 R 3
• Step #2: Normalize: 376 × 80 = .376 × 83.
• Step #3: Fill in the bit fields, with a positive sign (sign bit = 0), anexponent of 3 + 4 = 7 (excess 4), and 4-digit fraction = .3760:
0 111 . 011 111 110 000
Chapter 2: Data Representation2-21
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Error, Range, and Precision• In the previous example, we have the base b = 8, the number of
significant digits (not bits!) in the fraction s = 4, the largest expo-nent value (not bit pattern) M = 3, and the smallest exponent valuem = -4.
• In the previous example, there is no explicit representation of 0,but there needs to be a special bit pattern reserved for 0 other-wise there would be no way to represent 0 without violating thenormalization rule. We will assume a bit pattern of0 000 000 000 000 000 represents 0.
• Using b, s, M, and m, we would like to characterize this floatingpoint representation in terms of the largest positive representablenumber, the smallest (nonzero) positive representable number,the smallest gap between two successive numbers, the largestgap between two successive numbers, and the total number ofnumbers that can be represented.
Chapter 2: Data Representation2-22
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Error, Range, and Precision (cont’)
• Largest representable number: bM × (1 - b-s) = 83 × (1 - 8-4)
• Smallest representable number: bm × b-1 = 8-4 - 1 = 8-5
• Largest gap: bM × b-s = 83 - 4 = 8-1
• Smallest gap: bm × b-s = 8-4 - 4= 8-8
Chapter 2: Data Representation2-23
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Error, Range, and Precision (cont’)
• Number of representable numbers: There are 5 components: (A)sign bit; for each number except 0 for this case, there is both apositive and negative version; (B) ( M - m) + 1 exponents; (C) b - 1values for the first digit (0 is disallowed for the first normalizeddigit); (D) bs-1 values for each of the s-1 remaining digits, plus (E)a special representation for 0. For this example, the 5 componentsresult in: 2 × ((3 - 4) + 1) × (8 - 1) × 84-1 + 1 numbers that can berepresented. Notice this number must be no greater than the num-ber of possible bit patterns that can be generated, which is 2 16.
2 × ((M - m) + 1) × (b - 1) × bs-1 +
Sign bitFirst digit of fraction
Remaining digits of fraction
The number of exponents Zero
A EB C D
1
Chapter 2: Data Representation2-24
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example Floating Point Format
• Smallest number is 1/8
• Largest number is 7/4
• Smallest gap is 1/32
• Largest gap is 1/4
• Number of representable numbers is 33.
–3 –1 –1 0 1 1 3– 1
414
– 18
18
22 2 2
b = 2 M = +1s = 3 m = –2
Chapter 2: Data Representation2-25
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Gap Size Follows Exponent Size• The relative error is approximately the same for all numbers.
• If we take the ratio of a large gap to a large number, and comparethat to the ratio of a small gap to a small number, then the ratiosare the same:
bM × (1 – b– s)
bM– s
1 – b– s
b– s
= =bs–1A large number
A large gap 1
bm × (1 – b– s)
bm– s
1 – b– s
b– s
= =bs–1A small number
A small gap 1
Chapter 2: Data Representation2-26
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Conversion Example• Example: Convert (9.375 × 10-2)10 to base 2 scientific notation
• Start by converting from base 10 floating point to base 10 fixedpoint by moving the decimal point two positions to the left, whichcorresponds to the -2 exponent: .09375.
• Next, convert from base 10 fixed point to base 2 fixed point:
.09375 × 2 = 0.1875
.1875 × 2 = 0.375
.375 × 2 = 0.75
.75 × 2 = 1.5
.5 × 2 = 1.0
• Thus, (.09375) 10 = (.00011)2.
• Finally, convert to normalized base 2 floating point:
.00011 = .00011 × 20 = 1.1 × 2-4
Chapter 2: Data Representation2-27
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
IEEE-754 Floating Point Formats
Single precision
Sign (1 bit)
Exponent Fraction
8 bits 23 bits
Double precision
Exponent Fraction
11 bits 52 bits
32 bits
64 bits
Chapter 2: Data Representation2-28
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
IEEE-754 Examples
(a) +1.101 × 25
Value
0
Sign Exponent Fraction
Bit Pattern
1000 0100 101 0000 0000 0000 0000 0000
(b) −1.01011 × 2−126 1 0000 0001 010 1100 0000 0000 0000 0000
(c) +1.0 × 2127 0 1111 1110 000 0000 0000 0000 0000 0000
(d) +0 0 0000 0000 000 0000 0000 0000 0000 0000
(e) −0 1 0000 0000 000 0000 0000 0000 0000 0000
(f) +∞ 0 1111 1111 000 0000 0000 0000 0000 0000
(g) +2−128 0 0000 0000 010 0000 0000 0000 0000 0000
(h) +NaN 0 1111 1111 011 0111 0000 0000 0000 0000
(i) +2−128 0 011 0111 1111 0000 0000 0000 0000 0000 00000000 0000 0000 0000 0000 0000 0000
Chapter 2: Data Representation2-29
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
IEEE-754 Conversion Example• Represent -12.625 10 in single precision IEEE-754 format.
• Step #1: Convert to target base. -12.625 10 = -1100.1012
• Step #2: Normalize. -1100.101 2 = -1.1001012 × 23
• Step #3: Fill in bit fields. Sign is negative, so sign bit is 1. Expo-nent is in excess 127 (not excess 128!), so exponent is repre-sented as the unsigned integer 3 + 127 = 130. Leading 1 ofsignificand is hidden, so final bit pattern is:
1 1000 0010 . 1001 0100 0000 0000 0000 000
Chapter 2: Data Representation2-30
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Effect of Loss of Precision• According to
the General Ac-counting Officeof the U.S. Gov-ernment, a lossof precision inconverting 24-bit integers into24-bit floatingpoint numberswas responsiblefor the failure ofa Patriot anti-missile battery.
Range Gate Area
Missile
Search action locates missile somewhere within beam
Validation action
Missile outside of range gate
Patriot Radar System
Chapter 2: Data Representation2-31
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
ASCII Character Code• ASCII is a 7-bit code, com-
monly stored in 8-bitbytes.
• “A” is at 41 16. To convertupper case letters tolower case letters, add2016. Thus “a” is at 41 16 +2016 = 6116.
• The character “5” at posi-tion 35 16 is different thanthe number 5. To convertcharacter-numbers intonumber-numbers, sub-tract 30 16: 3516 - 3016 = 5.
00 NUL01 SOH02 STX03 ETX04 EOT05 ENQ06 ACK07 BEL08 BS09 HT0A LF0B VT0C FF0D CR0E SO0F SI
10 DLE11 DC112 DC213 DC314 DC415 NAK16 SYN17 ETB18 CAN19 EM1A SUB1B ESC1C FS1D GS1E RS1F US
20 SP21 !22 "23 #24 $25 %26 &27 '28 (29 )2A *2B +2C ´ 2D -2E .2F /
30 031 132 233 334 435 536 637 738 839 93A :3B ;3C <3D =3E >3F ?
40 @41 A42 B43 C44 D45 E46 F47 G48 H49 I4A J4B K4C L4D M4E N4F O
50 P51 Q52 R53 S54 T55 U56 V57 W58 X59 Y5A Z5B [5C \5D ]5E ^5F _
60 `61 a62 b63 c64 d65 e66 f67 g68 h69 i6A j6B k6C l6D m6E n6F o
70 p71 q72 r73 s74 t75 u76 v77 w78 x79 y7A z7B {7C |7D }7E ~7F DEL
NULSOHSTXETXEOTENQACKBEL
NullStart of headingStart of textEnd of textEnd of transmissionEnquiryAcknowledgeBell
BSHTLFVT
BackspaceHorizontal tabLine feedVertical tab
FFCRSOSIDLEDC1DC2DC3DC4NAKSYNETB
Form feedCarriage returnShift outShift inData link escapeDevice control 1Device control 2Device control 3Device control 4Negative acknowledgeSynchronous idleEnd of transmission block
CANEMSUBESCFSGSRSUSSPDEL
CancelEnd of mediumSubstituteEscapeFile separatorGroup separatorRecord separatorUnit separatorSpaceDelete
Chapter 2: Data Representation2-32
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
EBCDICCharacter
Code• EBCDIC is an 8-bit
code.
STX Start of text RS Reader Stop DC1 Device Control 1 BEL BellDLE Data Link Escape PF Punch Off DC2 Device Control 2 SP SpaceBS Backspace DS Digit Select DC4 Device Control 4 IL IdleACK Acknowledge PN Punch On CU1 Customer Use 1 NUL NullSOH Start of Heading SM Set Mode CU2 Customer Use 2ENQ Enquiry LC Lower Case CU3 Customer Use 3ESC Escape CC Cursor Control SYN Synchronous IdleBYP Bypass CR Carriage Return IFS Interchange File SeparatorCAN Cancel EM End of Medium EOT End of TransmissionRES Restore FF Form Feed ETB End of Transmission BlockSI Shift In TM Tape Mark NAK Negative AcknowledgeSO Shift Out UC Upper Case SMM Start of Manual MessageDEL Delete FS Field Separator SOS Start of SignificanceSUB Substitute HT Horizontal Tab IGS Interchange Group SeparatorNL New Line VT Vertical Tab IRS Interchange Record SeparatorLF Line Feed UC Upper Case IUS Interchange Unit Separator
00 NUL 20 DS 40 SP 60 – 80 A0 C0 { E0 \01 SOH 21 SOS 41 61 / 81 a A1 ~ C1 A E1 02 STX 22 FS 42 62 82 b A2 s C2 B E2 S03 ETX 23 43 63 83 c A3 t C3 C E3 T04 PF 24 BYP 44 64 84 d A4 u C4 D E4 U05 HT 25 LF 45 65 85 e A5 v C5 E E5 V06 LC 26 ETB 46 66 86 f A6 w C6 F E6 W07 DEL 27 ESC 47 67 87 g A7 x C7 G E7 X08 28 48 68 88 h A8 y C8 H E8 Y09 29 49 69 89 i A9 z C9 I E9 Z0A SMM 2A SM 4A ¢ 6A ‘ 8A AA CA EA 0B VT 2B CU2 4B 6B , 8B AB CB EB 0C FF 2C 4C < 6C % 8C AC CC EC 0D CR 2D ENQ 4D ( 6D _ 8D AD CD ED 0E SO 2E ACK 4E + 6E > 8E AE CE EE 0F SI 2F BEL 4F | 6F ? 8F AF CF EF 10 DLE 30 50 & 70 90 B0 D0 } F0 011 DC1 31 51 71 91 j B1 D1 J F1 112 DC2 32 SYN 52 72 92 k B2 D2 K F2 213 TM 33 53 73 93 l B3 D3 L F3 314 RES 34 PN 54 74 94 m B4 D4 M F4 415 NL 35 RS 55 75 95 n B5 D5 N F5 516 BS 36 UC 56 76 96 o B6 D6 O F6 617 IL 37 EOT 57 77 97 p B7 D7 P F7 718 CAN 38 58 78 98 q B8 D8 Q F8 819 EM 39 59 79 99 r B9 D9 R F9 91A CC 3A 5A ! 7A : 9A BA DA FA | 1B CU1 3B CU3 5B $ 7B # 9B BB DB FB 1C IFS 3C DC4 5C . 7C @ 9C BC DC FC 1D IGS 3D NAK 5D ) 7D ' 9D BD DD FD 1E IRS 3E 5E ; 7E = 9E BE DE FE 1F IUS 3F SUB 5F ¬ 7F " 9F BF DF FF
Chapter 2: Data Representation2-33
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
UnicodeCharacter
Code
• Unicode is a 16-bit code.
0000000100020003000400050006000700080009000A000B000C000D000E000F0010001100120013001400150016001700180019001A001B001C001D001E001F
NULSTXETX
Start of textEnd of text
ENQACKBEL
EnquiryAcknowledgeBell
BSHTLF
BackspaceHorizontal tabLine feed VT Vertical tab
SOH Start of headingEOT End of transmission
DLE Data link escape
DC1DC2DC3DC4NAKNBSETB
Device control 1Device control 2Device control 3Device control 4Negative acknowledgeNon-breaking spaceEnd of transmission block
EMSUBESCFSGSRSUS
End of mediumSubstituteEscapeFile separatorGroup separatorRecord separatorUnit separator
Null CAN Cancel
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LF 002AVT 002BFF 002CCR 002DSO 002ESI 002FDLE 0030DC1 0031DC2 0032DC3 0033DC4 0034NAK 0035SYN 0036ETB 0037CAN 0038EM 0039SUB 003AESC 003BFS 003CGS 003DRS 003EUS 003F
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CtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrlCtrl
00C000C100C200C300C400C500C600C700C800C900CA00CB00CC00CD00CE00CF00D000D100D200D300D400D500D600D700D800D900DA00DB00DC00DD00DE00DF
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Chapter 3: Arithmetic3-1
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Principles of Computer ArchitectureMiles Murdocca and Vincent Heuring
Chapter 3: Arithmetic
Chapter 3: Arithmetic3-2
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Chapter Contents3.1 Overview3.2 Fixed Point Addition and Subtraction3.3 Fixed Point Multiplication and Division3.4 Floating Point Arithmetic3.5 High Performance Arithmetic3.6 Case Study: Calculator Arithmetic Using Binary Coded Decimal
Chapter 3: Arithmetic3-3
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Computer Arithmetic
• Using number representations from Chapter 2, we will explore fourbasic arithmetic operations: addition, subtraction, multiplication,division.
• Significant issues include: fixed point vs. floating point arithmetic,overflow and underflow, handling of signed numbers, and perfor-mance.
• We look first at fixed point arithmetic, and then at floating pointarithmetic.
Chapter 3: Arithmetic3-4
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Number Circle for 3-Bit Two’sComplement Numbers
• Numbers can be added or subtracted by traversing the numbercircle clockwise for addition and counterclockwise for subtraction.
• Overflow occurs when a transition is made from +3 to -4 while pro-ceeding around the number circle when adding, or from -4 to +3while subtracting.
100
010110
000
111
101 011
001
0
1
2
3
-4
-3
-2
-1
Adding numbers
Subtracting numbers
Chapter 3: Arithmetic3-5
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Overflow• Overflow occurs when adding two positive numbers produces a
negative result, or when adding two negative numbers produces apositive result. Adding operands of unlike signs never produces anoverflow.
• Notice that discarding the carry out of the most significant bit dur-ing two’s complement addition is a normal occurrence, and doesnot by itself indicate overflow.
• As an example of overflow, consider adding (80 + 80 = 160) 10, whichproduces a result of -96 10 in an 8-bit two’s complement format:
01010000 = 80
+ 01010000 = 80
----------
10100000 = -96 ( not 160 because the sign bit is 1.)
Chapter 3: Arithmetic3-6
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Ripple Carry Adder• Two binary numbers A and B are added from right to left, creating
a sum and a carry at the outputs of each full adder for each bit po-sition.
Fulladder
b0 a0
s0
Fulladder
b1 a1
s1
Fulladder
b2 a2
s2
Fulladder
b3 a3
c4
s3
0c0c1c2c3
Chapter 3: Arithmetic3-7
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Constructing Larger Adders• A 16-bit adder can be made up of a cascade of four 4-bit ripple-
carry adders.
s0
b1
a1
s1
b2
a2
s2
b3
a3
c4
s3
04-Bit Adder #0
b0
a0
s12
b13
a13
s13
b14
a14
s14
b15
a15
c16
s15
4-Bit Adder #3
b12
a12
. . .c12 c0
Chapter 3: Arithmetic3-8
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Full Subtractor• Truth table and schematic symbol for a ripple-borrow subtractor:
00110011
01010101
bi bori
00001111
ai
01101001
diffi
01110001
bori+1
Fullsub-
tractor
bi ai
bori
bori+1
diffi(ai – bi)
Chapter 3: Arithmetic3-9
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Ripple-Borrow Subtractor• A ripple-borrow subtractor can be composed of a cascade of full
subtractors.
• Two binary numbers A and B are subtracted from right to left, cre-ating a difference and a borrow at the outputs of each fullsubtractor for each bit position.
b0 a0
diff0
b1 a1
diff1
b2 a2
diff2
Fullsub-
tractor
b3 a3
bor4
diff3
0
Fullsub-
tractor
Fullsub-
tractor
Fullsub-
tractor
bor0
Chapter 3: Arithmetic3-10
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Combined Adder/Subtractor
Fulladder
b0
a0
s0
Fulladder
b1
a1
s1
Fulladder
b2
a2
s2
Fulladder
b3
a3
c4
s3
c0
ADD /SUBTRACT
• A single ripple-carry adder can perform both addition and subtrac-tion, by forming the two’s complement negative for B when sub-tracting. (Note that +1 is added at c0 for two’s complement.)
Chapter 3: Arithmetic3-11
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
One’s Complement Addition• An example of one’s complement integer addition with an end-
around carry:
+
1
10
0
01
0
01
0
10
0
11
0
(–12)10(+13)10
+
0
0
0
0
1
1 (+1)10
End-around carry
• The end-around carry is needed because there are two represen-tations for 0 in one’s complement. Both representations for 0 arevisited when one or both operands are negative.
Chapter 3: Arithmetic3-12
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Number Circle (Revisited)• Number circle for a three-bit signed one’s complement represen-
tation. Notice the two representations for 0.
100
010110
000
111
101 011
001
+0
1
2
3
-3
-2
-1
-0
Adding numbers
Subtracting numbers
Chapter 3: Arithmetic3-13
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
End-Around Carry for Fractions• The end-around carry complicates one’s complement addition for
non-integers, and is generally not used for this situation.
• The issue is that the distance between the two representations of0 is 1.0, whereas the rightmost fraction position is less than 1.
1
01
0
11
0
01
1
10
1
.
.
.
(+5.5)10(–1.0)10
+
(+4.5)10
10
1
+
0
1
0
1
0
.
.
0
1
Chapter 3: Arithmetic3-14
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Multiplication Example• Multiplication of two 4-bit unsigned binary integers produces an
8-bit result.
1 1 0 1
1 0 1 1× 1 1 0 1
1 1 0 10 0 0 0
1 1 0 1
1 0 0 0 1 1 1 1
(11)10
(13)10 Multiplicand M
Multiplier Q
(143)10 Product P
Partial products
• Multiplication of two 4-bit signed binary integers produces only a7-bit result (each operand reduces to a sign bit and a 3-bit mag-nitude for each operand, producing a sign-bit and a 6-bit result).
Chapter 3: Arithmetic3-15
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Serial Multiplier
Multiplicand (M)
m0m1m2m3
a0a1a2a3 q0q1q2q3
Multiplier (Q)
C
4–Bit Adder
Shift and Add Control
LogicAdd
4
4
4
Shift Rightq0
A Register
Chapter 3: Arithmetic3-16
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example of Multiplication UsingSerial Multiplier
C
0
00
10
0
10
0
A
0 0 0
1 1 0 10 1 1 0
0 0 1 11 0 0 1
0 1 0 0
0 0 0 11 0 0 0
1
Q
0 1 1
1 0 1 11 1 0 1
1 1 0 11 1 1 0
1 1 1 1
1 1 1 11 1 1 1
Multiplicand (M):
1 1 0 1Initial values
Add M to AShift
Add M to AShift
Shift (no add)
Add M to AShift
Product
Chapter 3: Arithmetic3-17
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example of Base 2 Division
1 1
0 0 1 0
0 1 1 11 1
0
R 1
1
• (7 / 3 = 2)10 with a remainder R of 1.
• Equivalently, (0111/ 11 = 10) 2 with a remainder R of 1.
Chapter 3: Arithmetic3-18
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Serial Divider
Divisor (M)
m0m1m2m3
a0a1a2a3 q0q1q2q3
Dividend (Q)
5–Bit Adder
Shift andAdd / Sub
Control LogicAdd /
Sub
5
5
5
Shift Leftq0
A Register
a4
0
a4
Chapter 3: Arithmetic3-19
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Division Example Using Serial Divider
0
01
00
0
A
0 0 0
0 0 0 01 1 0 1
0 0 1 10 0 0 0
0
Q
1 1 1
1 1 1 01 1 1 0
1 0 0 01 0 0 0
Divisor (M):
0 0 1 1Initial values
Shift leftSubtract M from A
Shift leftSubtract M from A
0 0 0 0 0 1 1 1 0 Restore A (Add M to A)
01
0 0 0 11 1 1 0
1 1 0 01 1 0 0
Shift leftSubtract M from A
0 0 0 0 1 1 1 0 0 Restore A
0 0 0 0 0 1 1 1 0 Clear q0
0 0 0 0 1 1 1 0 0 Clear q0
0 0 0 0 0 1 0 0 1 Set q0
01
0 0 0 11 1 1 0
0 0 1 00 0 1 0
Shift leftSubtract M from A
0 0 0 0 1 0 0 1 0 Restore A0 0 0 0 1 0 0 1 0 Clear q0
Remainder Quotient
0
Chapter 3: Arithmetic3-20
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Multiplication of Signed Integers
1 1 1 1
0 0 0 1× 1 1 1 1
0 0 0 00 0 0 0
0 0 0 0
0 0 0 0 1 1 1 1
(+1)10
(–1)10
(+15)10
(Incorrect; result should be –1)
1 1 1 1
0 0 0 1× 1 1 1 1
0 0 0 00 0 0 0
0 0 0 0
1 1 1 1 1 1 1 1
(+1)10
(–1)10
(–1)10
1 1 1 1
1 1 1 10 0 00 00
• Sign extension to the target word size is needed for the negativeoperand(s).
• A target word size of 8 bits is used here for two 4-bit signed op-erands, but only a 7-bit target word size is needed for the result.
Chapter 3: Arithmetic3-21
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Carry-Lookahead Addition
Gi = aibi and Pi = ai + bi
c0 = 0
c1 = G0
c2 = G1 + P1G0
c3 = G2 + P2G1 + P2P1G0
c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0
• Carries are represented in termsof Gi (generate) and Pi (propagate)expressions.
Chapter 3: Arithmetic3-22
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Carry Lookahead Adder
Fulladder
s0
Fulladder
s1
Fulladder
s2
Fulladder
s3
0c0
b3 a3b3 a3 b2 a2 b1 a1 b0 a0
G0P1G1P2G2
c1c2c3
P3G3
c4
• Maximum gate delayfor the carry genera-tion is only 3. Thefull adders introducetwo more gate de-lays. Worst casepath is 5 gate de-lays.
Chapter 3: Arithmetic3-23
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Floating Point Arithmetic• Floating point arithmetic differs from integer arithmetic in that ex-
ponents must be handled as well as the magnitudes of the oper-ands.
• The exponents of the operands must be made equal for additionand subtraction. The fractions are then added or subtracted as ap-propriate, and the result is normalized.
• Ex: Perform the floating point operation: (.101 × 23 + .111 × 24)2• Start by adjusting the smaller exponent to be equal to the larger
exponent, and adjust the fraction accordingly. Thus we have .101× 23 = .010 × 24, losing .001 × 23 of precision in the process.
• The resulting sum is (.010 + .111) × 24 = 1.001 × 24 = .1001 × 25, androunding to three significant digits, .100 × 25, and we have lost an-other 0.001 × 24 in the rounding process.
Chapter 3: Arithmetic3-24
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Floating Point Multiplication/Division• Floating point multiplication/division are performed in a manner
similar to floating point addition/subtraction, except that the sign,exponent, and fraction of the result can be computed separately.
• Like/unlike signs produce positive/negative results, respectively.Exponent of result is obtained by adding exponents for multiplica-tion, or by subtracting exponents for division. Fractions are multi-plied or divided according to the operation, and then normalized.
• Ex: Perform the floating point operation: (+.110 × 25) / (+.100 × 24)2
• The source operand signs are the same, which means that the re-sult will have a positive sign. We subtract exponents for division,and so the exponent of the result is 5 – 4 = 1.
• We divide fractions, producing the result: 110/100 = 1.10.
• Putting it all together, the result of dividing (+.110 × 25) by (+.100 ×24) produces (+1.10 × 21). After normalization, the final result is(+.110 × 22).
Chapter 3: Arithmetic3-25
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Booth Algorithm• Booth multiplication reduces the number of additions for interme-
diate results, but can sometimes make it worse as we will see.
• Positive and negative numbers treated alike.
0 1 0 1
1 1 1 0
1 0 1 1
1
(14)10
(21)10 Multiplicand
Multiplier
(294)10 Product
1
0
0
0
0
1
0 0 −1 0× Booth recoded multiplier
+10
ShiftAdd
ShiftSubtract
Shift
1111
01010
0 0 1 11001000
(−21 × 2)10
(21 × 16)10
1
00
0
0
0
000
Chapter 3: Arithmetic3-26
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Worst Case Booth Example• A worst case situation in which the simple Booth algorithm re-
quires twice as many additions as serial multiplication.
1 1 1 0
0 1 0 1
1 0 0 1
1
(21)10
(14)10 Multiplicand
Multiplier
(294)10 Product
0
1
1
0
0
1
+1 −1 +1 −1× Booth recoded multiplier
−1+1
Add
Subtract
1111
00000
0 0 1 11001000
(−14 × 1)10
(14 × 2)10
1
00
0
0
0
011
1 0 0 1
1
11111
00000 0
0
011
1 0 0 1
1
111
000 0
0
011 0
0
0
0
0
0
0
0
0
0
0
0 (−14 × 4)10
(14 × 8)10
(−14 × 16)10
(14 × 32)10
Chapter 3: Arithmetic3-27
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Bit-Pair Recoding (Modified BoothAlgorithm)
1 1 1 0
0 1 0 1
0
(14)10
(21)10 Multiplicand
Multiplier
(294)10 Product
0
1
0
0
+1 −1 +1 −1× Booth recoded multiplier−1+1
00000
0 0 1 11001000
(14 × 1)1000
0
0111
0 1 1 1
1
00000
10000 0
0
001 0
0
0
0 (14 × 4)10
(14 × 16)10
Bit pair recoded multiplier+1 +1+1
Chapter 3: Arithmetic3-28
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
000
+1+1+1−1−1−1
0+1−1
0+1−1
0+1−1
=========
0+1−1+2–– +1−2−1––
Recoded bit pair (i)
Booth pair(i + 1, i)
Corresponding multiplier bits (i + 1, i, i − 1)
000 or 111001110011
010100101
Coding of Bit Pairs
Chapter 3: Arithmetic3-29
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
ParallelPipelinedArray Mul-
tiplier
. . .
q 0 q 0 q 0 q 0
0 0 0 0 0 0 0 0m0m1m2mw
Multiplicand
0. . .
p 0
q 1 q 1 q 1 q 1
p1
q w q w q w q w
. . .
0
p2w-1
pw+3pw+2 pw+1
0
p w
.
.
.
.
.
.
.
.
.
Multiplier
Product
0
Fulladder
Carry-in
Carry-out
sum
qj
aj bj
m out
mi
mi
PP 0,w PP 0,2 PP 0,1 PP0,0
PP1,w PP1,2 PP1,1 PP1,0
PPw,w PPw,2 PPw,1 PPw,0
FA FA FA FAw+1,0w+1,1w+1,2w+1,wPP PP PP PP
Chapter 3: Arithmetic3-30
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Newton’s Iteration for Zero Finding• The goal is to find where
the function f(x) crossesthe x axis by startingwith a guess xi and thenusing the error betweenf(x i ) and zero to refinethe guess.
• A three-bit lookup tablefor computing x0:
f(x)
xxi+1x i
.100 2 10
B = First three bits of b
Corresponding lookup table entry
Actual base 10 value of 1/B
.101 1 3/5 01
.110 1 1/3 01
.111 1 1/7 01
• The division operation a/bis computed as a × 1/b.Newton’s iteration pro-vides a fast method ofcomputing 1/ b.
Chapter 3: Arithmetic3-31
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Residue Arithmetic• Implements carryless arithmetic (thus fast!), but comparisons are
difficult without converting to a weighted position code.
• Representation of the first twenty decimal integers in the residuenumber system for the given moduli:
Decimal Residue Decimal Residue5794
0 0000 10 0312
5794
1 1111 11 14232 2222 12 25303 3333 13 36414 4440 14 40525 0551 15 01636 1662 16 12707 2073 17 23818 3180 18 34029 4201 19 4513
Chapter 3: Arithmetic3-32
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Examples of Addition and Multiplica-tion in the Residue Number System
Decimal Residue5794
29 412127 260356 1020
29 + 27 = 56
Decimal Residue5794
10 031217 2381
170 0282
10 × 17 = 170
Chapter 3: Arithmetic3-33
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
16-bit Group Carry Lookahead Adder• A16-bit GCLA is composed of four 4-bit CLAs, with additional logic
that generates the carries between the four-bit groups.
GG0 = G3 + P3G2 + P3P2G1 + P3P2P1G0
GP0 = P3P2P1P0
c4 = GG0 + GP0c0
c8 = GG1 + GP1c4 = GG1 + GP1GG0 + GP1GP0c0
c12 = GG2 + GP2c8 = GG2 + GP2GG1 + GP2GP1GG0 +
GP2GP1GP0c0
c16 = GG3 + GP3c12 = GG3 + GP3GG2 + GP3GP2GG1 +
GP3GP2GP1GG0 + GP3GP2GP1GP0c0
Chapter 3: Arithmetic3-34
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
16-Bit Group Carry Lookahead Adder
• In the GCLL section, GG and GP signals are generated in 3 gatedelays; carry signals are generated in 2 more gate delays, result-ing in 5 gate delays to generate the carry out of each GCLA groupand 10 gates delays on the worst case path (which is s15 – not c 16).
c16Group Carry Lookahead Logic
CLA0
4
a0 – a3
4
b0 – b3
4
s0 – s3
GG0GP0
CLA1
4
a4 – a7
4
b4 – b7
4
s4 – s7
GG1GP1
CLA2
4
a8 – a11
4
b8 – b11
4
s8 – s11
GG2GP2
CLA3
4
a12 – a15
4
b12 – b15
4
s12 – s15
GG3GP3
c4c8c12
c0
• Each CLAhas a long-est path of5 gate de-lays.
Chapter 3: Arithmetic3-35
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
HP 9100 Series Desktop Calculator• Source: http://www.teleport.com/ ~dgh/91003q.jpg.
• Uses binary coded decimal (BCD) arithmetic.
Chapter 3: Arithmetic3-36
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Addition Example Using BCD• Addition is performed digit by digit ( not bit by bit), in 4-bit
groups, from right to left.
• Example (255 + 63 = 318) 10:
0 0 0 0
(0)10
0 0 1 0
(2)10
0 1 0 1
(5)10
0 1 0 1
(5)10
(+255)10
0 0 0 0
(0)10
0 0 0 0
(0)10
0 1 1 0
(6)10
0 0 1 1
(3)10
(+63)10+
0 0 0 0
(0)10
0 0 1 1
(3)10
0 0 0 1
(1)10
1 0 0 0
(8)10
(+318)10
0 1 0 0 Carries
Chapter 3: Arithmetic3-37
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Subtraction Example Using BCD• Subtraction is carried out by adding the ten’s complement nega-
tive of the subtrahend to the minuend.
• Ten’s complement negative of subtrahend is obtained by adding 1to the nine’s complement negative of the subtrahend.
• Consider performing the subtraction operation (255 - 63 = 192) 10:
0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 (+255)10
1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 (−63)10+
0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 (+192)10
1 0 1 0 Carries1
1
Discard carry
9 9 9 90 0 6 3
9 9 3 6
−
9 9 3 60 0 0 1
9 9 3 7
+
Chapter 3: Arithmetic3-38
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Excess 3 Encoding of BCD Digits
• Using anexcess 3encodingfor eachBCD digit,the leftmostbit indi-cates thesign.
0011001100110011
0101010101010101
0000111100001111
0123456789dddddd
0000000011111111
BCD Bit Pattern
Normal BCD value
Positive numbers
ddd0123456789ddd
Excess 3 value
Negative numbers
Chapter 3: Arithmetic3-39
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A BCD Full Adder• Circuit adds
two base 10digits repre-sented inBCD. Adding5 and 7(0101 and0111) resultsin 12 (0010with a carryof 1, and not1100, whichis the binaryrepresenta-tion of 12 10).
Fulladder
b0 a0
Fulladder
b1 a1
Fulladder
b2 a2
Fulladder
b3 a3
c4
0c0
Fulladder
s0
Fulladder
s1
Fulladder
s2
Fulladder
s3
01
Chapter 3: Arithmetic3-40
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Ten’s Complement Subtraction• Compare: the traditional signed magnitude approach for adding
decimal numbers vs. the ten’s complement approach, for(21 - 34 = -13)10:
+
0
9
9
0
9
9
2
6
8
1
6
7
Ten’s Complement
−−
0
0
0
0
0
0
2
3
1
1
4
3
Signed Magnitude
Chapter 3: Arithmetic3-41
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
BCD Floating Point Representation• Consider a base 10 floating point representation with a two digit
signed magnitude exponent and an eight digit signed magnitudefraction. On a calculator, a sample entry might look like:
-.37100000 × 10-12
• We use a ten’s complement representation for the exponent, and abase 10 signed magnitude representation for the fraction. A sepa-rate sign bit is maintained for the fraction, so that each digit cantake on any of the 10 values 0–9 (except for the first digit, whichcannot be zero). We should also represent the exponent in excess50 (placing the representation for 0 in the middle of the expo-nents, which range from -50 to +49) to make comparisons easier.
• The example above now looks like this (see next slide):
Chapter 3: Arithmetic3-42
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
BCD Floating Point Arithmetic• The example in the previous slide looks like this:
Sign bit: 1
Exponent: 0110 1011
Fraction: 0110 1010 0100 0011 0011 0011 0011 0011 0011
• Note that the representation is still in excess 3 binary form, with atwo digit excess 50 exponent.
• To add two numbers in this representation, as for a base 2 floatingpoint representation, we start by adjusting the exponent and frac-tion of the smaller operand until the exponents of both operandsare the same. After adjusting the smaller fraction, we convert ei-ther or both operands from signed magnitude to ten’s comple-ment according to whether we are adding or subtracting, andwhether the operands are positive or negative, and then performthe addition or subtraction operation.
Chapter 4: The Instruction Set Architecture4-1
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Princip ios de Arquitectura de Computadoras
Capítulo 4: La Arquitectura delConjunto de Instrucciones
Chapter 4: The Instruction Set Architecture4-2
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Contenidos de Capítulo4.1Componentes de Hardware de la Arquitectura del Set de Instrucciones 4.2 ARC, Una Computadora RISC4.3 Pseudo Operaciones4.4 Ejempl os de Programas en Langua je Ensamblador4.5 Acce diendo a Datos en Memor ia—Modos de Direccionamiento4.6 Enlaces a Subrutin as y Punteros4.7 Entreada y Salida en Lenguaje Ensamblador
Chapter 4: The Instruction Set Architecture4-3
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
La Arquitectura del Set de Instrucciones• La Vista de la Arquitectur a del Set Instrucciones (ISA) de una máquina corre s-
pond e al nivel de : lenguaje ensamblador / lenguaje de máquina
• Un compil ador traduce un lenguaje de alto nivel, que es independientede la arquitectura, a lenguaje ensamblador, el cual es dependien-te de la arquitectura.
• Un ensambl ador traduce programas en lenguaje assemb ler a códigosbinarios ejecutable s.
• Para lenguajes compilados como C y Fortran, los códigos binariosson ejecutados directamente por la máquina. Java para la traducióna nivel de byte. La máquina virtual Java, que está a nivel de lenguajeensamblador, interpret a directamente los byte s (hay implementacio-nes de hardware de la JVM, en las que el código de byte Java es ejecutado directamente.)
Chapter 4: The Instruction Set Architecture4-4
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Revisión del Modelo de Bus de Sistema• Un programa compilado es copiado desde el disco duro en la memoria.
La CPU lee las instrucciones y los datos desde la memoria, ejecutalas instrucciones y almacena los resultados nuevamente en la me-moria.
Syst
em B
us
Bus de Datos
Bus de Direcciones
Bus de Control
(ALU, Registros,
y Control)
Memoria Entrada y Salida (I/O)
CPU
Chapter 4: The Instruction Set Architecture4-5
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Tamaños más comunes de los datos • Un byte está comp uesto de 8 bits. Dos nibbles forman un byte.
• Los datos de media palabra, palabra, palabra doble y cuádrupleestán compuestos por bytes como se ve a continuación:
Bit
Nibble
Byte
16-bit word (halfword)
32-bit word
64-bit word (double)
0
0110
10110000
11001001 01000110
10110100 00110101 10011001 01011000
01011000 01010101 10110000 1111001111001110 11101110 01111000 00110101
128-bit word (quad) 01011000 01010101 10110000 1111001111001110 11101110 01111000 0011010100001011 10100110 11110010 1110011010100100 01000100 10100101 01010001
Chapter 4: The Instruction Set Architecture4-6
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Formatos Big-Endian y Little-Endia n• En una máquina direccionable por byte el dato más pequeño que se
puede buscar en memoria es el byte. Las palabras multi bytes se almacenancomo secuenc ias de bytes, y se direccionan a partir del byte menossignificativo de la palabra almacenada.
• Cuando se utilizan palabras de mas de un byte, hay dos alternativasen la forma de almacenar sus bytes en memoria: el byte mas significativose almacena en la dirección mas baja de memoria (big-endia n). El byte menos significativo se almacena en la dirección mas baja (little-endia n).
Big-Endian
x x+1 x+2 x+3
31 Little-Endian
x+3 x+2 x+1 x
0
La dirección de la palabra es x para ambos formatos.
0 31
Byte
← MSB LSB → ← MSB LSB →
Chapter 4: The Instruction Set Architecture4-7
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Mapa de Memoria para ARC• Las direcciones
de memoria estanordenadas en forma consecutiv a. Cada locaciónnum erada corres-ponde a una palabraen ARC.El único númeroque identifica a cada palabrase conoce comosu dirección.
Reservado para sistema operativo
Espacio del Usuario
Espacio I/O
0
2048
Puntero de pilaPila del Sistema
Tope de la pila
Final de la pila
DiscoTerminal
Impresora
232 – 4
231 – 4
32 bits
Direccion es Datos
232 – 1byte
MEMORIA
Dirección Control
Salida de Datos
Entradade datos
Chapter 4: The Instruction Set Architecture4-8
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Vista Abstract a de una CPU La CPU consist e de una sección de datos que contiene registros y una
ALU, y una sección de control, que interpret a las instruction es y realiza las transferencias entre registr os. La sección de datos seconoce como "camino de datos" o "datapath".
Unidad Control
Sección de Control
Registros
ALU
Datapath(Sección deDatos)
Sistema
Chapter 4: The Instruction Set Architecture4-9
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
El Ciclo Fetch-E jecución
• Los pasos que sigue una unidad de control para ejecutar un program ason:
(1) Buscar de la memoria la siguiente instrucción a ejecutar.
(2) Decod ificar el opcode (código de operación).
(3) Leer operand o(s) desde la memor ia principal, si hubiera alguno.
(4) Ejecut ar la instruc ción y almacenar result ados.
(5) Ir al paso 1.
Esto se conoce como el ciclo fetch-e jecución.
Chapter 4: The Instruction Set Architecture4-10
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Trayectoria de Datos"Datapath "
• El datapath de ARC está formado por una colec ción de registr os conocidosel archivo de registros y la unidad arit metic o lógic a (ALU).
Conjunto de Registros
ALU
Desde el Bus de Datos
Al Bus de Datos
Al Bus de Direcciones
Registro Fuente 1
(rs1)
Registro Fuente 2
(rs2)
Al Registro de Destino (rd)
La Unidad de Control selecciona funcionesen Registros y ALU
Estado a la Unidad de Control
Chapter 4: The Instruction Set Architecture4-11
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Arquitectura de las Instrucciones ARC • La ISA de ARC es un subconjunto de la ISA de SPARC.
ld Cargar registro desde la memoria
Nemonico Significado
st
sethi
andcc
addcc
call
jmpl
be
orcc
orncc
Almacenar un registro en la memoria
Cargar los 22 bits mas significativos de un registro
Operación lógica AND bit a Bit
Sumar
Bifurcación o Salto por desborde u "overflow"
Salto ó Llamado a subrutina
Salto y Enlace (retorno de subrutina)
Bifurcación o Salto por igual
Operación lógica OR bit a bit
Operación lógica NOR bit a bit
bneg
bcs
Bifurcación o Salto por negativo
Bifurcación o Salto por acarreo
srl Desplazar a derecha (lógico)agrega ceros a la izq.
bvs
ba Bifurcación o Salto incondicional
Memoria
Lógicas
Aritmeticas
Control
Chapter 4: The Instruction Set Architecture4-12
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Formato de lenguaje ensamblador ARC• El formato de lenguaje ensamblador ARC es el mismo del lenguaje
ensamblador SPARC.
lab_1: addcc %r1, %r2, %r3 !Ejemplo código assembler
Etiqueta NemónicoOperandos fuentes Destino Comentario
Operandos
Chapter 4: The Instruction Set Architecture4-13
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Registros ARC visibles por el usuarioRegistro 00 %r0 [= 0]
Registro 01 %r1
Registro 02 %r2
Registro 03 %r3
Registro 04 %r4
Registro 05 %r5
Registro 06 %r6
Registro 07 %r7
Registro 08 %r8
PSR %psr PC %pc
Registro 09 %r9
Registro 10 %r10
Registro 11 %r11
Registro 12 %r12
Registro 13 %r13
Registro14 %r14 [%sp]
Registro 15 %r15 [link]
32 bits 32 bits
Registro 16 %r16
Registro 17 %r17
Registro 18 %r18
Registro 19 %r19
Registro 20 %r20
Registro 21 %r21
Registro 22 %r22
Registro 23 %r23
Registro 24 %r24
Registro 25 %r25
Registro 26 %r26
Registro 27 %r27
Registro 28 %r28
Registro 29 %r29
Registro 30 %r30
Registro 31 %r31
Chapter 4: The Instruction Set Architecture4-14
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Instrucciones ARC y Formatos PSR
op3 (op=10)
010000010001010010010110100110111000
addccandccorccornccsrljmpl
00010101011001111000
cond
bebcsbnegbvsba
salto
010100
op2
branchsethi
Inst.
00011011
op
SETHI/BranchCALLAritméticasMemoria
Format
000000000100
ldst
op3 (op=11)
op
Formato de llamada a subrutina disp30
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0 1
Formato SETHI imm22
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rd
disp220 cond
0 0
0 0Formato de salto
op2
op2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rs11 op3
simm131 op3
1
Formatos de Memoria 1
rd
rd rs1
0
1
0 0 0 0 0 0 0 0 rs2
Formatos Aritméticos
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rs11 op3
simm131 op3
0
0
rd
rd rs1
0
1
0 0 0 0 0 0 0 0 rs2
i
PSR31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
z v cn
Chapter 4: The Instruction Set Architecture4-15
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Formatosde Datos ARC
Signed Integer Byte s7 6 0
Signed Integer Halfword s15 14 0
Signed Integer Word s31 30 0
Signed Integer Double s63 62 32
31 0
Signed Formats
Unsigned Integer Byte7 0
Unsigned Integer Halfword15 0
Unsigned Integer Word31 0
Unsigned Integer Double63 32
31 0
Unsigned Formats
Floating Point Single
Floating Point Double
Floating Point Quad
31 0
s127 126 96
95 64
Floating Point Formats
Tagged Word31 0
Tag
12
s31 30 0
exponent fraction23 22
s63 62 32
exponent fraction
fraction
63 32
31 0
exponent fraction
52 51
113112
fraction
fraction
fraction
Chapter 4: The Instruction Set Architecture4-16
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Pseudo-Op eraciones ARC
• Las pseudo-ops son instruc cion es del assemble r. No son partede la ISA (Instruction Set Architecture).
Pseudo-Op Uso Significado
.equ .equ #10 Asignar a X el valor (10)16
.begin .begin Comienzo de traducción
.end .end Fin de traduccción
.org .org 2048 Cambiar contador de posicion a 2048
.dwb .dwb 25 Reservar un bloque de 25 palabras
X
.global .global Y Y se usa en otro modulo
.extern .extern Z Z está definido en otro modulo
.macro .macro M a, b, ...
formales: a, b, ...
.endmacro .endmacro Fin de definición de Macro
.if .if <cond> Ensamblar si <cond> es cierta
.endif .endif Fin estructura condicional
Definir macro M con parametros
Chapter 4: The Instruction Set Architecture4-17
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Ejemplo de Programa ARC Un programa ARC en lenguaje assembl er que suma dos enteros:
! Este programa suma dos numeros enteros
.org 2048ld [x], %r1 !Carga x en %r1ld [y], %r2 !Carga y en %r2addcc %r1, %r2, %r3 !%r3 ← %r1 + %r2
jmpl %r15 + 4, %r0 !Retorna de subrutinax: 15y: 9
.end
.begin
prog1:
z: 0
st %r3, [z] !Guarda %r3 en z
Chapter 4: The Instruction Set Architecture4-18
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Un ejemplode programa
masComplejo
• Un programa ARCque suma cinco enteros.
! %r5 – Contiene un elemento de a
.begin ! Comienzo del ensamblado
.org 2048 ! Inicio del programa en 2048
be done ! Fin alizar cuando length=0
addcc %r1, -4, %r1 ! Decrementar longitud arreglo
ld %r4, %r5 ! %r5 ← Memoria[%r4]
addcc %r3, %r5, %r3 ! Sumar nuevo elemento en r3
ba loop ! Repe tir lazo.
done: jmpl %r15 + 4, %r0 ! Reorno a rutina de llamada
length: 20 ! 5 numeros (20 bytes) en a
.org a_start ! Inicio del arreglo a
a: 25 ! length/4 valores siguientes
– 10
33
– 5 7
.end ! Fin ensamblado
! %r4 – Puntero dentro del arreglo a
! %r3 – La Suma parcial
! %r2 – Dirección de inicio del arreglo a
! Uso de los Registros: %r1 – Longitud del arreglo a
! Este programa suma LENGTH numeros
loop: andcc %r1, %r1, %r0 ! Test # re stantes elementos andcc %r3, %r0, %r3 ! %r3 ← 0 ld [address],%r2 ! %r2 ← dirección de a ld [length], %r1 ! %r1 ← long. del arreglo a
addcc %r1, %r2, %r4 ! Dirección próximo elemento
a_start .equ 3000 ! Dirección del arreglo a
address: a_start
Chapter 4: The Instruction Set Architecture4-19
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Máquinas de Una, Dos y Tres Direcciones• Consideremos como la Expresión A = B*C + D puede evaluarse por
instrucciones de una, dos y tres direcciones.
• Asumimos que: Las palabras de Direcciones y datos son de 2 bytes.Los Opcodes son de 1 byte. Los operandos se mueven desde y haciala memoria de a una palabra (dos bytes) por vez.
• Instruciones de Tres-Direcciones: En este tipo de instrucciones, laexpresión A = B*C + D puede ser codificada como:
mult B, C, A
add D, A, A
Esto es, multiplicar B por C y guardar el resultado en A. ( mult y add son operaciones genéricas; no son instrucciones ARC.)Sumar D con A y guardar el resultado en la dirección A. El tamaño delprograma es 7×2 = 14 bytes. El tráfico de memoria es 14 + 2×(2×3) = 26 bytes.
Chapter 4: The Instruction Set Architecture4-20
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Máquinas de una, dos y tres direcciones• Instrucciones de dos direcciones: Para instrucciones de dos direc-
ciones uno de los operandos es sobreescrito por el resultado. El código para la expresión A = B*C + D es:
load B, A
mult C, A
add D, A
El tamaño del programa es 3×(1+2×2) ó 15 bytes. El tráfico de memoria:15 + 2×2 + 2×2×3 ó 31 bytes.
Chapter 4: The Instruction Set Architecture4-21
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Máquinas de una, dos y tres direcciones• Instrucciones de una dirección (Acumulador): Aquí se usa un único
registro en la CPU para las operaciones internas conocido comoacumulador . El código para la expresión A = B*C + D es ahora:
load B
mult C
add D
store A
La instrucción load carga B en el acumulador, mult multiplicaC por el acumulador y guarda el resultado en el mismo acumuladory add hace la suma correspondiente. La instrucción store guarda el acumulador en A. El tamaño de programa es ahora:(2+1)×4 ó 12 bytes, y el tráfico de memoria es 12 + 4× 2 ó 20 bytes.
Chapter 4: The Instruction Set Architecture4-22
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Modos de Direccionamientos
• Cuatro modos de calcular la dirección de un valor en memoria: (1) Unvalor constante conocido al momento del ensamble, (2) los contenidosde un registro, (3) la suma de dos registros, (4) suma de un registro y unaconstante. La tabla dá nombres a estos y a otros modos de direccionamientos.
Chapter 4: The Instruction Set Architecture4-23
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Llamado a Subrutina Usando Registros• Llamado a subrutina utilizando registros.
! Rutina Invocante
ld [x], %r1ld [y], %r2call add_1
st %r3, [z]
.
.
.
! Rutina Invocada
addcc %r1, %r2, %r3jmpl %r15 + 4, %r0
add_1:
.
.
.
! %r3 ← %r1 + %r2
53x:10y: 0z:
Chapter 4: The Instruction Set Architecture4-24
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Llamado a subrutina – Area de transferencia de datos• Llamado a subrutina con área de transferencia de datos en un
area separada de memoria. La direción del área de memoria estáen un registro (en este caso: %r5).
! Rutina Invocante
st %r1, [x]st %r2, [x+4]sethi x, %r5
call add_2
x:
ld
.dwb
.
.
.
.
.
.
[x+8], %r3
3
! Rutina Invocada
ld %r5, %r8ld %r5 + 4, %r9addccst
%r8, %r9, %r10%r10, %r5 + 8
add_2:
jmpl %r15 + 4, %r0srl %r5, 10, %r5
!Zona de transf.de datos
! x[2] ← x[0] + x[1]
Chapter 4: The Instruction Set Architecture4-25
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Llamado a Subrutina – Pila• Llamado a subrutina utilizando una pila para guardar los parametros.
! Rutina Invocante
.equ %r14addcc %sp, -4, %spst %r1, %spaddcc %sp, -4, %sp
%sp
stcall
.
.
.
.
.
.
%r2, %spadd_3
! Rutina Invocada
.equ %r14ld %sp, %r8addcc %sp, 4, %spld %sp, %r9addccst
%r8, %r9, %r10%r10, %sp
%sp
jmpl %r15 + 4, %r0
add_3:
ld %sp, %r3addcc %sp, 4, %sp
! Los argumentos estan en la pila! %sp[0] ← %sp[0] + %sp[4]
Chapter 4: The Instruction Set Architecture4-26
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Ejemplode rutinas
encadenadas
• Un programa en Cmostrando llama-dos encadenados
/* Programa en C mostrando llamados encadenados a subrutinas */
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
Linea No.
main()
{
int w, z; /* Variables Locales */
w = func_1(1,2); /* Subrutina a la func_1 */
z = func_2(10); /* Subrutina a la func_2 */
} /* Fin de la rutina principal */
int func_1(x,y) /* Calcula x * x + y */
int x, y; /* Pase de Parametros a func_1 */
{
int i, j; /* Variables Locales */
i = x * x;
j = i + y;
return(j); /* Retorna j a rutina invocante */
}
int func_2(a) /* Calcula a * a + a + 5 */
int a; /* Pase de parametros a func_2 */
{
int m, n; /* Variables Locales */
n = a + 5;
m = func_1(a,n);
return(m); /* Retorna m a rutina invocante */
}
Chapter 4: The Instruction Set Architecture4-27
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Rutinas enca-denadas con
Pilas(continuación)
• (a-f) comportamientode la Pila durante laejecución del programaen C mostrado conanterioridad.
Configuracion Inicial.w y z están disponibles en la
pila. (Linea 00 del programa.)
(a)El llamado a rutina empuja los argumentos en la pila, antes de llamar a func_1.(Linea 03 del programa.)
(b)Despues del Call la rutina
invocada guarda el PC de la rutinainvocante (%r15)en la pila.
(Line 06 del programa.)
(c)
0
232– 4
Free area
%spStack
0
232– 4
Free area
%sp
Stack
0
232– 4
Free area
%sp
12
12
%r15
Beginning of stack frame
Se reserva espacio en la pila parafunc_1, variables locales i
y j. (Line 09 del programa.)
(d)Los valores de Retorno de func_1 se ubican en la
pila, justo antes del retorno.(Line 12 del programa.)
(e)La rutina invocante "extrae" desde la pila los
valores de retorno de func_1 (Line 03 del programa.)
(f)
0
232– 4
Area Libre
Pila
0
232– 4
Area Libre
Pila
0
232– 4
3
Stack
%sp
Stack frame for func_1
%sp
Area Libre
%spStack
12
%r15ij
Chapter 4: The Instruction Set Architecture4-28
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Rutinas encade-nadas con pilas(continuación)
• (g-k) Comportamientode la Pila durante laejecución del programaen C mostrado conanterioridad
Se crea un marco de pila para la func_2 como resultado del llamado a función de la
linea 04 del programa.
(g)Se crea un marco de pila para
la func_1 como resultado del llamado a función de la
linea 19 del programa.
(h)func_1 coloca valores
de retorno en la pila. (Linea 12 del programa.)
(i)
0
232– 4
Area libre
0
232– 4
%sp
Pila
0
232– 4
Area libre
%sp
func_2 coloca valores de retorno en la pila. (Linea 20
del programa.)
(j)Finaliza el programa. La pila se restaura a su configuración. (Lineas
04 y 05 del programa.)
(k)
0
232– 4
Area Libre
0
232– 4
Pila
115%sp
Marco dePila para func_2
Area Libre
%sp Pila
Pila
%sp
10%r15mn
10%r15mn1015%r15ij
Marco de pilapara func_2
func_1 Marco de pila
115
%r15mn
10
Pila
Area Libre
Chapter 4: The Instruction Set Architecture4-29
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Entrada y Salida para
la ISA
• Mapa de memoria parala ARC, mostrando el mapeo de memoria deI/O.
Reservado para rutinas de arranque
y rutinas gráficas
Memoria de video ad. #1
Espacio de I/O
0
216
Puntero de Pila(SP)Pila de Sistema
Tope de la pila
Fondo de la pila
Parpadeo de pantallaTouchscreen xTouchscreen y
224 – 4
223 – 4
32 bits
Dirección Contenido
224 – 1byte
Memoria de video ad. #2217
219
Memoria de trabajo
Zona sin uso
222
FFFFEC16FFFFF0 16FFFFF4 16
Chapter 4: The Instruction Set Architecture4-30
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Pantalla sensible al tacto• Un usuario seleccionando un objeto en una pantalla:
LEDs (Diodos emisores de Luz)
Detector
El Usuario interrumpe el haz
Chapter 4: The Instruction Set Architecture4-31
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras - M. Murdocca y V. Heuring
Diagrama de flujopara dispositivo I/O
• Diagrama que ilustra la estructura de control de unprograma que verifica unapantalla sensible al tacto.
Compare valores X e Y anteriores con los nuevos
Se modificaronX e Y ?
No
S i
Leer registro X Leer registro Y
Parpadeo de pantalla
Actualizar registros X e Y
Chapter 5: Languages and the Machine5-1
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Principios de Arquitectura de ComputadorasMiles Murdocca and V incent Heuring
Capítulo 5: Los Lenguajes y la Máquina
Chapter 5: Languages and the Machine5-5
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
El Proceso de Ensamblado* El proceso de transformar un programa en lenguaje ensamblador en un
programa en lenguaje de máquina se conoce como proceso de ensamblado
* Los ensambladores comerciales proveen las siguientes prestaciones:
-- Permite al programador especificar la ubicación de variables y programas
-- Provee expresiones nemónicas en el lenguaje de programación para todas las instrucciones del lenguaje de máquina y modos de direccio-namientos y traduce sentencias válidas al lenguaje absoluto.
-- Permitir el uso de rótulos simbólicos para representar direcciones y constantes
-- Ofrecerle al programador cificar la direcci¤n de inicio de un programa, si existiera.
-- Incluir un mecanismo que permita la definición de variables en un pro-grama escrito en lenguaje simbólico y el uso de las mismas en otro pro-grama ensamblado por separado.
-- Proveer la expansión de macro rutinas (se definen una sola vez).
Chapter 5: Languages and the Machine5-6
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Ejemplo de ensamblado• Exploraremos como el proceso de ensamblado genera un programa ARC
a través del proceso de "Ensamblado a Mano".
! Este programa suma dos números
.org 2048ld [x], %r1 ! Carga x en %r1ld [y], %r2 ! Carga y en %r2addcc %r1, %r2, %r3 ! %r3 ← %r1 + %r2
jmpl %r15 + 4, %r0 ! Retornox: 15y: 9
.end
.begin
main:
z: 0
st %r3, [z] ! Almacena %r3 en z
Chapter 5: Languages and the Machine5-7
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Formatode instruc-ciones yformato del PSRpara unamáquinaARC
op3 (op=10)
010000010001010010010110100110111000
addccandccorccornccsrljmpl
00010101011001111000
cond
bebcsbnegbvsba
branch
010100
op2
branchsethi
Inst.
00011011
op
SETHI/BranchCALLArithmeticMemory
Format
000000000100
ldst
op3 (op=11)
op
CALL format disp30
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0 1
SETHI Format imm22
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rd
disp220 cond
0 0
0 0Branch Format
op2
op2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rs11 op3
simm131 op3
1
Memory Formats1
rd
rd rs1
0
1
0 0 0 0 0 0 0 0 rs2
Arithmetic Formats
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rs11 op3
simm131 op3
0
0
rd
rd rs1
0
1
0 0 0 0 0 0 0 0 rs2
i
PSR31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
z v cn
Chapter 5: Languages and the Machine5-8
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Código Ensamblado
ld [x], %r1 1100 0010 0000 0000 0010 1000 0001 0100
ld [y], %r2 1100 0100 0000 0000 0010 1000 0001 1000
addcc %r1,%r2,%r3 1000 0110 1000 0000 0100 0000 0000 0010
st %r3, [z] 1100 0110 0010 0000 0010 1000 0001 1100
jmpl %r15+4, %r0 1000 0001 1100 0011 1110 0000 0000 0100
15 0000 0000 0000 0000 0000 0000 0000 1111
9 0000 0000 0000 0000 0000 0000 0000 1001
0 0000 0000 0000 0000 0000 0000 0000 0000
Chapter 5: Languages and the Machine5-9
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Referencia Previa• Un ejemplo de Referencia Previa
call sub_r
sub_r: st %r1, [w]...
.
.
.
.
.
.
! La subrutina es invocada aquí
! La subrutina se define aquí
Chapter 5: Languages and the Machine5-10
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Creando unaTabla de Símbolos
Símbolo Valor
length 2092
loop 2060
done 2088
a 3000
(b)
S Value
a_start 3000
(a)
length ––
a_start 3000
address 2096
! %r5 – contiene un elemento de a
.begin ! comienzo de traducción
.org 2048 !comienzo de programa en 2048
be done ! Fin aliza cuando length=0
addcc %r1, -4, %r1 ! Decrementar tamaño arreglo
ld %r4, %r5 !%r5 ← dirección Memoria[%r4]
addcc %r3, %r5, %r3 ! Sumar nuevo elemento en r3
ba loop ! Repe tir lazo.
done: jmpl %r15 + 4, %r0 ! Retorno a rutina principal
length: 20 ! 5 numeros (20 bytes) en a
.org a_start ! Comienzo del arreglo a
a: 25 ! length/4 valores siguientes
– 10
33
– 5 7
.end ! Fin de traducción
! %r4 – Puntero al arreglo a
! %r3 – La suma Parcial
! %r2 – Dirección de inicio del arreglo a
! Uso del Registro: %r1 – Longitud del arreglo a
! Este programa suma tantos numeros como indica "LENGTH"
loop: andcc %r1, %r1, %r0 ! Ver # elementos restantes andcc %r3, %r0, %r3 ! %r3 ← 0 ld [address],%r2 ! %r2 ← dirección de a ld [length], %r1 ! %r1 ← long. del arreglo a
addcc %r1, %r2, %r4 ! Dirección próximo elemento
a_start .equ 3000 ! Dirección del arreglo a
address: a_start
Símbolo Valor
a_start 3000
(a)
length ––
Chapter 5: Languages and the Machine5-11
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
ProgramaEnsamblado
.begin
.org 2048
a_start .equ 3000
ld [length],%r1 11000010 00000000 00101000 00101100 ld [address],%r2 11000100 00000000 00101000 00110000 andcc %r3,%r0,%r3 10000110 10001000 11000000 00000000loop: andcc %r1,%r1,%r0 10000000 10001000 01000000 00000001 be done 00000010 10000000 00000000 00000110 addcc %r1,-4,%r1 10000010 10000000 01111111 11111100 addcc %r1,%r2,%r4 10001000 10000000 01000000 00000010 ld %r4,%r5 11001010 00000001 00000000 00000000
addcc %r3,%r5,%r3 10000110 10000000 11000000 00000101 ba loop 00010000 10111111 11111111 11111011
done: jmpl %r15+4,%r0 10000001 11000011 11100000 00000100length: 20 00000000 00000000 00000000 00010100
.org a_start
a: 25 00000000 00000000 00000000 00011001 -10 11111111 11111111 11111111 11110110 33 00000000 00000000 00000000 00100001 -5 11111111 11111111 11111111 11111011
Código ObjetoInstrucciónContador de posición
2048
2052
2056
2060
2064
2068
2072
2076
2080
2084
2088
3004
3000
3008
3012
3016
2092
.end
7 00000000 00000000 00000000 00000111
address: a_start 00000000 00000000 00001011 101110002096
Chapter 6: Datapath and Control6-1
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Principios de Arquitectura de ComputadorasMiles Murdocca and Vincent Heuring
Capítulo 6: Datapath y Control
Chapter 6: Datapath and Control6-2
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Contenido del capítulo6.1 Elementos básicos de Microarquitectura6.2 Una Microarquitectura para la máquina ARC6.3 Control Cabledo
Chapter 4: The Instruction Set Architecture4-9
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
El Ciclo Fetch-E jecución
• Los pasos que sigue una unidad de control para ejecutar un program ason:
(1) Buscar de la memoria la siguiente instrucción a ejecutar.
(2) Decod ificar el opcode (código de operación).
(3) Leer operand o(s) desde la memor ia principal, si hubiera alguno.
(4) Ejecut ar la instruc ción y almacenar result ados.
(5) Ir al paso 1.
Esto se conoce como el ciclo fetch-e jecución.
Chapter 6: Datapath and Control6-4
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Una Microarquitectura en Alto Nivel
U.de Control
Sección de Control
Registros
ALU
Datapath(Sección de Datos)
BUS DE SISTEMA
Una microarquitectura consiste de la unidad de control y de los regis-tros visibles por el programador, unidades funcionales como la ALU,y todo registro adicional que requiera la Unidad de Control.
Chapter 4: The Instruction Set Architecture4-11
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Subconjunto de Instrucciones ARC
ld Cargar registro desde la memoria
Nemonico Significado
st
sethi
andcc
addcc
call
jmpl
be
orcc
orncc
Almacenar un registro en la memoria
Cargar los 22 bits mas significativos de un registro
Operación lógica AND bit a Bit
Sumar
Bifurcación o Salto por desborde u "overflow"
Salto ó Llamado a subrutina
Salto y Enlace (retorno de subrutina)
Bifurcación o Salto por igual
Operación lógica OR bit a bit
Operación lógica NOR bit a bit
bneg
bcs
Bifurcación o Salto por negativo
Bifurcación o Salto por acarreo
srl Desplazar a derecha (lógico)agrega ceros a la izq.
bvs
ba Bifurcación o Salto incondicional
Memoria
Lógicas
Aritmeticas
Control
Chapter 4: The Instruction Set Architecture4-14
© 1999 M. Murdocca and V. HeuringPrincipios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
Instrucciones ARC y Formatos PSR
op3 (op=10)
010000010001010010010110100110111000
addccandccorccornccsrljmpl
00010101011001111000
cond
bebcsbnegbvsba
salto
010100
op2
branchsethi
Inst.
00011011
op
SETHI/BranchCALLAritméticasMemoria
Format
000000000100
ldst
op3 (op=11)
op
Formato de llamada a subrutina disp30
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0 1
Formato SETHI imm22
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rd
disp220 cond
0 0
0 0Formato de salto
op2
op2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rs11 op3
simm131 op3
1
Formatos de Memoria 1
rd
rd rs1
0
1
0 0 0 0 0 0 0 0 rs2
Formatos Aritméticos
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
rs11 op3
simm131 op3
0
0
rd
rd rs1
0
1
0 0 0 0 0 0 0 0 rs2
i
PSR31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
z v cn
Chapter 6: Datapath and Control6-7
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Datapath ARC
%r0A bus B busC bus
F1F2
ALU
32
32
4
%r1
64-to-32 MUX
C Bus MUX
n, z, v, c
F0
C Decoder %r5
%pc
%temp0
%r2
%r3
%r4
%r6
%r7
%r8
%r9
%r10
%r30
%r31
B Decoder
F3
6
c1
c37
37 38 b0
b37
6
A Decoder
38 a0
a37
6
Dat
a Fr
om M
ain
Mem
ory
MUX Control Line (From
Control Unit)
%temp1
%temp2
%temp3
%ir
Data T
o Main
Mem
ory
Add
ress
To
Mai
n M
emor
y
CLOCK UNIT
0
1
2
3
4
5
6
7
8
9
10
30
31
32
33
34
35
36
37
32
From Control
Unit
From Control Unit
Set Condition Codes (SCC)
32
32
.
.
.
To Control Unit
24
Chapter 6: Datapath and Control6-8
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Operaciones ARC de la ALU
0011001100110011
0101010101010101
F1 F0
ANDCC (A, B)
ORCC (A, B)
NORCC (A, B)
ADDCC (A, B)
SRL (A, B)
AND (A, B)
OR (A, B)
NOR (A, B)
ADD (A, B)
LSHIFT2 (A)
LSHIFT10 (A)
SIMM13 (A)
SEXT13 (A)
INC (A)
INCPC (A)
RSHIFT5 (A)
Operación
0000111100001111
F2 Cambia Código Condición
si si si sinononononononononononono
0000000011111111
F3
Chapter 6: Datapath and Control6-14
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Microarqui-tectura de
ARC
32
A b
us
B b
us
C b
us
2048 palabras de Control × 41 bit Almacenamiento
CS Address MUX
Jump
Control branch
logic (CBL)
F1F2ALU
Microcode Instruction
Register (MIR)
CLOCK UNIT
41
11
11
Memoria PrincipalWRRD
Sección de Datos (Datapath)
32
Address
Data In
00 = Next01 = Jump10 = Inst. Dec.
4
8
2
Decode
1 0 0
4
232 byte address space
32
3
Data Out
64-to-32 MUX
C Bus MUX
%psr
n, z, v, c
F0
Next
11
Control Store Address Incrementer (CSAI)
Acknowledge (ACK)
To C Decoder
%ir
C MUX
0, rd
Sección de Control
A MUX
0, rs1
To B Decoder
B MUX
0, rs2
F3
4
1
IR[30,31,19-24]
6 5
6
MIR C field
Sel
ect
MIR A field
MIR B field
6
6
5 6
Select
Select
Area de trabajo
To A Decoder
rd rs2 rs1 ops
IR[13]
5 6
Set Condition Codes
%ir
RD
WRCA B JUMP ADDRALU COND
AMUX
BMUX
CMUX
Chapter 6: Datapath and Control6-15
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Formato de Microcódigo
RD
WRCA B JUMP ADDRALU COND
AMUX
BMUX
CMUX
Chapter 6: Datapath and Control6-16
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Valores para el campo COND dela Microcódigo
00110011
01010101
C1 C0
Usar NEXT ADDRUsar JUMP ADDR if n = 1Usar JUMP ADDR if z = 1Usar JUMP ADDR if v = 1Usar JUMP ADDR if c = 1Usar JUMP ADDR if IR[13] = 1Usar JUMP ADDRDECODE
Operación
00001111
C2
Chapter 6: Datapath and Control6-17
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Formato DECODE para la Direcciónde la Microinstrucción
op
1 0 0
op2
op3
31 30 24 23 22 21 20 19IR bits
Chapter 6: Datapath and Control6-19
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Microprogramaparcial ARC
0000: R[ir] ← AND(R[pc],R[pc]); READ; / Read an ARC instruction from main memory0001: DECODE; / 256-way jump according to opcode00// / sethi1152: R[rd] ← LSHIFT10(ir); GOTO 2047; / Copy imm22 field to target register00// / call1280: R[15] ← AND(R[pc],R[pc]); / Save %pc in %r151281: R[temp0] ← ADD(R[ir],R[ir]); / Shift disp30 field left1282: R[temp0] ← ADD(R[temp0],R[temp0]); / Shift again1283: R[pc] ← ADD(R[pc],R[temp0]); / Jump to subroutine GOTO 0; 0//0 / addcc1600: IF R[IR[13]] THEN GOTO 1602; / Is second source operand immediate?1601: R[rd] ← ADDCC(R[rs1],R[rs2]); / Perform ADDCC on register sources GOTO 2047; 1602: R[temp0] ← SEXT13(R[ir]); / Get sign extended simm13 field1603: R[rd] ← ADDCC(R[rs1],R[temp0]); / Perform ADDCC on register/simm13 GOTO 2047; / sources00// / andcc1604: IF R[IR[13]] THEN GOTO 1606; / Is second source operand immediate?1605: R[rd] ← ANDCC(R[rs1],R[rs2]); / Perform ANDCC on register sources GOTO 2047; 1606: R[temp0] ← SIMM13(R[ir]); / Get simm13 field1607: R[rd] ← ANDCC(R[rs1],R[temp0]); / Perform ANDCC on register/simm13 GOTO 2047; / sources 00// / orcc1608: IF R[IR[13]] THEN GOTO 1610; / Is second source operand immediate?1609: R[rd] ← ORCC(R[rs1],R[rs2]); / Perform ORCC on register sources GOTO 2047; 1610: R[temp0] ← SIMM13(R[ir]); / Get simm13 field1611: R[rd] ← ORCC(R[rs1],R[temp0]); / Perform ORCC on register/simm13 sources GOTO 2047;00// / orncc1624: IF R[IR[13]] THEN GOTO 1626; / Is second source operand immediate?1625: R[rd] ← NORCC(R[rs1],R[rs2]); / Perform ORNCC on register sources GOTO 2047; 1626: R[temp0] ← SIMM13(R[ir]); / Get simm13 field1627: R[rd] ← NORCC(R[rs1],R[temp0]); / Perform NORCC on register/simm13 GOTO 2047; / sources 00// / srl1688: IF R[IR[13]] THEN GOTO 1690; / Is second source operand immediate?1689: R[rd] ← SRL(R[rs1],R[rs2]); / Perform SRL on register sources GOTO 2047; 1690: R[temp0] ← SIMM13(R[ir]); / Get simm13 field1691: R[rd] ← SRL(R[rs1],R[temp0]); / Perform SRL on register/simm13 sources GOTO 2047;00// / jmpl1760: IF R[IR[13]] THEN GOTO 1762; / Is second source operand immediate?1761: R[pc] ← ADD(R[rs1],R[rs2]); / Perform ADD on register sources GOTO 0;
Address Operation Statements Comment
Chapter 6: Datapath and Control6-20
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
MicroprogramaParcial ARC(continuación)
1762: R[temp0] ← SEXT13(R[ir]); / Get sign extended simm13 field1763: R[pc] ← ADD(R[rs1],R[temp0]); / Perform ADD on register/simm13 sources GOTO 0;00// / ld1792: R[temp0] ← ADD(R[rs1],R[rs2]); / Compute source address IF R[IR[13]] THEN GOTO 1794; 1793: R[rd] ← AND(R[temp0],R[temp0]); / Place source address on A bus READ; GOTO 2047; 1794: R[temp0] ← SEXT13(R[ir]); / Get simm13 field for source address1795: R[temp0] ← ADD(R[rs1],R[temp0]); / Compute source address GOTO 1793;00// / st1808: R[temp0] ← ADD(R[rs1],R[rs2]); / Compute destination address IF R[IR[13]] THEN GOTO 1810; 1809: R[ir] ← RSHIFT5(R[ir]); GOTO 40; / Move rd field into position of rs2 field 40: R[ir] ← RSHIFT5(R[ir]); 41: R[ir] ← RSHIFT5(R[ir]); 42: R[ir] ← RSHIFT5(R[ir]); 43: R[ir] ← RSHIFT5(R[ir]); 44: R[0] ← AND(R[temp0], R[rs2]); / Place destination address on A bus and WRITE; GOTO 2047; / place operand on B bus1810: R[temp0] ← SEXT13(R[ir]); / Get simm13 field for destination address1811: R[temp0] ← ADD(R[rs1],R[temp0]); / Compute destination address GOTO 1809;00// / Branch instructions: ba, be, bcs, bvs, bneg1088: GOTO 2; / Decoding tree for branches 2: R[temp0] ← LSHIFT10(R[ir]); / Sign extend the 22 LSB’s of %temp0 3: R[temp0] ← RSHIFT5(R[temp0]); 4: R[temp0] ← RSHIFT5(R[temp0]); / bits. RSHIFT5 does sign extension. 5: R[ir] ← RSHIFT5(R[ir]); / Move COND field to IR[13] by 6: R[ir] ← RSHIFT5(R[ir]); 7: R[ir] ← RSHIFT5(R[ir]); 8: IF R[IR[13]] THEN GOTO 12; / Is it ba? R[ir] ← ADD(R[ir],R[ir]); 9: IF R[IR[13]] THEN GOTO 13; / Is it not be? R[ir] ← ADD(R[ir],R[ir]); 10: IF Z THEN GOTO 12; / Execute be R[ir] ← ADD(R[ir],R[ir]); 11: GOTO 2047; / Branch for be not taken 12: R[pc] ← ADD(R[pc],R[temp0]); / Branch is taken GOTO 0; 13: IF R[IR[13]] THEN GOTO 16; / Is it bcs? R[ir] ← ADD(R[ir],R[ir]); 14: IF C THEN GOTO 12; / Execute bcs 15: GOTO 2047; / Branch for bcs not taken 16: IF R[IR[13]] THEN GOTO 19; / Is it bvs? 17: IF N THEN GOTO 12; / Execute bneg 18: GOTO 2047; / Branch for bneg not taken 19: IF V THEN GOTO 12; / Execute bvs 20: GOTO 2047; / Branch for bvs not taken2047: R[pc] ← INCPC(R[pc]); GOTO 0; / Increment %pc and start over
/ by shifting left 10 bits, then right 10
/ applying RSHIFT5 three times. (The/ sign extension is inconsequential.)
/ by shifting to the right by 25 bits.
Chapter 6: Datapath and Control6-22
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
MicroprogramaARC
Ensamblado
RD
WRCA B JUMP ADDRALU COND
AMUX
BMUX
CMUX
1 000001 00000 001010100101000
11111111111
00 000000 00000 0000000001011110000000000011 010100 00000 000001001010110
00000000000
11521 000001 00000 0111100001010000000000000012801 010101 01010 0000100010000000000000000012811 000101 00010 0000100010000000000000000012821 000001 00010 00000000100011012830 000000 00000 0000000001011011100100001016000 000010 00001 00000100001111016011 010100 00000 0000100011000000000000000016020 000011 00010 00000100001111016030 000000 00000 0000000001011011100100011016040 000010 00001 00000100000011016051 010100 00000 0000100010110000000000000016060 000011 00010 00000100000011016070 000000 00000 0000000001011011100100101016080 000010 00001 00000100000111016091 010100 00000 0000100010110000000000000016100 000011 00010 000001000001110
0
16110 000000 00000 0000000001011011100101101016240 000010 00001 00000100001011016251 010100 00000 0000100010110000000000000016260 000011 00010 0000010000101116270 000000 00000 0000000001010001101001101016880 000010 00001 00000100010011016891 010100 00000 0000100010110000000000000016900 000011 00010 00000100010011016910 000000 00000 0000000001011011101110001017600 000010 00001 0000000010001100000000000017611 010100 00000 0000100011000000000000000017620 000011 00010 000000001000110000000000001763
000010 00001 000010001000101111000000101792
11111111111
11111111111
11111111111
00000000000
11111111111
11111111111
11111111111
11111111111
11111111111
11111111111
11111111111
Microstore Address
0
10001110010001000100010001001111
00000000000000000000000000000000
00000000000000000000000000000000
Chapter 6: Datapath and Control6-23
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
MicroprogramaARC
Ensamblado(continuación)
0 000000 000000 00000000101110201 000000 000001 0000000111011000000000002047
RD
WRCA B JUMP ADDRALU COND
AMUX
BMUX
CMUX
1 000101 000100 000011001011101111111111117931 010100 000001 000100011000000000000000017940 000011 000101 000100010001101110000000117950 000010 000011 000100010001011110001001018081 010100 000001 010100011111100000010100018091 010100 000001 0101000111100000000000000401 010100 000001 0101000111100000000000000411 010100 000001 0101000111100000000000000421 010100 000001 0101000111100000000000000431 000100 000010 0000001010111011111111111441 010100 000001 000100011000000000000000018100 000011 000101 000100010001101110001000118110 000000 000000 000000001011100000000001010881 010100 000001 000100010100000000000000021 000100 000001 000100011110000000000000031 000100 000001 000100011110000000000000041 010100 000001 010100011110000000000000051 010100 000001 010100011110000000000000061 010100 000001 010100011110000000000000071 010101 010001 010100010001010000000110081 010101 010001 010100010001010000000110191 010101 010001 0101000100001000000001100100 000000 000000 00000000101110
11111111111
111 000001 000101 0000000100011000000000000121 010101 010101 0101000100010100000010000130 000000 000000 0000000010110000000001100140 000000 000000 00000000101110150 000000 000000 0000000010110100000010011160 000000 000000 0000000010100100000001100170 000000 000000 00000000101110180 000000 000000 000000001010110000000110019
11111111111
11111111111
11111111111
00 0 00 0 0
0 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 0
0 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 0
Chapter 6: Datapath and Control6-27
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Hardware Description Language
• Secuencia HDL para un contadormódulo 4reiniciable.
MODULE: MOD_4_COUNTER.INPUTS: x.OUTPUTS: Z[2].MEMORY:
0: Z ← 0,0; GOTO {0 CONDITIONED ON x, 1 CONDITIONED ON x}.1: Z ← 0,1; GOTO {0 CONDITIONED ON x, 2 CONDITIONED ON x}.2: Z ← 1,0; GOTO {0 CONDITIONED ON x, 3 CONDITIONED ON x}.3: Z ← 1,1; GOTO 0.
END SEQUENCE.END MOD_4_COUNTER.
Preámbulo
Sentencias
Epílogo
Chapter 6: Datapath and Control6-28
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Circuito Derivado a partir de HDL• Diseño lógico para un contador módulo 4 descripto en HDL.
CLK
QD0
x
QD QD QD1 2 3
Z[1]
Z[0]
SECCION de CONTROL
SECCION de DATOS
Chapter 6: Datapath and Control6-29
HDL for ARC
• Descripción HDL de laUnidad de control ARC.
MODULE: ARC_CONTROL_UNIT.
INPUTS:
OUTPUTS: C, N, V, Z. ! Fijadas por la ALU
MEMORY: R[16][32], pc[32], ir[32], temp0[32], temp1[32], temp2[32],
temp3[32].
0: ir ← AND(pc, pc); Read ← 1; ! Búsqueda de la Instrucción ! Decodificar el campo op
1: GOTO {2 CONDITIONED ON ir[31]× ir[30], ! formato Branch/sethi: op=00 4 CONDITIONED ON ir[31]× ir[30], ! formato Call: op=01 8 CONDITIONED ON ir[31]× ir[30], ! formato Aritmetico : op=10 10 CONDITIONED ON ir[31]× ir[30]}. ! formato de Memoria: op=11 ! Decodficar campo op2
2: GOTO 19 CONDITIONED ON ir[24]. ! si es formato de salto ir a 19
3: R[rd] ← ir[imm22]; ! sethi GOTO 20.
4: R[15] ← AND(pc, pc). ! call:Guardar pc en registro 155: temp0 ← ADD(ir, ir). ! desplazar campo disp30 a izq.6: temp0 ← ADD(ir, ir). ! desplazar nuevamente7: pc ← ADD(pc, temp0); GOTO 0. ! Saltar a subrutina ! Colocar el segundo operando origen en temp0 para el formato Aritmetico
8: temp0 ← { SEXT13(ir) CONDITIONED ON ir[13]× NOR(ir[19:22]), ! addcc R[rs2] CONDITIONED ON ir[13]× NOR(ir[19:22]), ! addcc SIMM13(ir) CONDITIONED ON ir[13]× OR(ir[19:22]), ! Remaining R[rs2] CONDITIONED ON ir[13]× OR(ir[19:22])}. ! Instrucciones Aritméticas ! Decodificar el campo op3 para el formato Aritmetico
9: R[rd] ← { ADDCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010000), ! addcc
ANDCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010001), ! andcc
ORCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010010), ! orcc
NORCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010110), ! orncc
SRL(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 100110), ! srl
ADD(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 111000)}; ! jmpl
GOTO 20.
! cargar en temp0 el segundo operando fuente si es formato de Memoria
10: temp0 ← {SEXT13(ir) CONDITIONED ON ir[13], R[rs2] CONDITIONED ON ir[13]}.
11: temp0 ← ADD(R[rs1], temp0). ! Decodificar el campo op3 field para el formato de Memoria
GOTO {12 CONDITIONED ON ir[21], ! ld
13 CONDITIONED ON ir[21]}. ! st
12: R[rd] ← AND(temp0, temp0); Read ← 1; GOTO 20.13: ir ← RSHIFT5(ir).
Chapter 6: Datapath and Control6-30
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
HDL para ARC(continuación)
14: ir ← RSHIFT5(ir).15: ir ← RSHIFT5(ir).16: ir ← RSHIFT5(ir).17: ir ← RSHIFT5(ir).18: r0 ← AND(temp0, R[rs2]); Write ← 1; GOTO 20.19: pc ← { ! Instrucciones de salto (Branch) ADD(pc, temp0) CONDITIONED ON ir[28] + ir[28]× ir[27]× Z + ir[28]× ir[27]× ir[26]× C + ir[28]× ir[27]× ir[26]× ir[25]× N + ir[28]× ir[27]× ir[26]× ir[25]× V, INCPC(pc) CONDITIONED ON ir[28]× ir[27]× Z + ir[28]× ir[27]× ir[26]× C + ir[28]× ir[27]× ir[26]× ir[25]× N + ir[28]× ir[27]× ir[26]× ir[25]× V}; GOTO 0.
20: pc ← INCPC(pc); GOTO 0.END SEQUENCE.
END ARC_CONTROL_UNIT.
Chapter 6: Datapath and Control6-31
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
CircuitoHDL-ARC
• La sección de controlcableada de ARC:generación de señalesde control.
CLK
QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7
QD8
QD9
QD10
QD11
QD12
QD13
QD14
QD15
QD16
QD17
QD18
QD19
IR[31]
IR[30] IR[24]
IR[21]
QD20
CS0 CS3
CS4
CS5
CS6
CS0
CS8
CS9
CS10CS11
CS12
CS13 CS14
CS15
CS16 CS17CS18
CS19
CS20
Chapter 6: Datapath and Control6-32
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
• Sección de controlcableado de ARC:Señales desdela sección dedatos de la uni-dad de control a latrayectoria de datos.
AMUXCS9
CS11
WriteCS18
CMUXCS3
CS9CS12
ReadCS0
CS12
BMUX
CS18IR[13]
CS10
CS8
IR[1
9] IR[2
2]IR
[20]
IR[2
1]ALU[3]
CS9
IR[19]IR[20]
IR[24]
IR[23]
IR[22]IR[21]
CS20CS19
CS8
CS5CS6CS7
CS16CS14
CS15
CS17
CS11
CS13
ALU[2]
CS20CS18
CS4
CS10
CS12
CS16
CS14
CS15
CS1
CS13CS17
CS2
CS3
CS8
IR[13]
IR[19]IR[20]
IR[22]IR[21]
CS9
IR[2
4]IR
[23]
IR[19]IR[20]IR
[22]
IR[21]
CS19IR[28]
IR[28]IR[27]
IR[26]IR[25]
C
IR[28]IR[27]
IR[26]IR[25] N
IR[28]IR[27]
IR[26]C
IR[28]
IR[27]Z
CS2CS3IR[24]
ALU[0]
ALU[1]
CS20CS16
CS14CS15
CS13
CS17
IR[20]IR[21]
CS19
CS8
IR[13]IR[19]
IR[22]
IR[20]
IR[21]
CS9
IR[1
9]IR
[22]
IR[24]IR[23]
CS4 CS1
CS0
IR[13]CS8
IR[22]IR[21]
IR[19]
IR[23]
B[5]
B[2]
B[3]
B[4]
B[0]
B[1]
C[3]
C[4]
C[5]
IR[13]
IR[13]
A[1]
A[3]
A[4]
0
0
0
A[0]
CS5CS6
CS16CS14
CS15
CS17
CS13
CS12CS8
CS10
CS18
A[2]
A[5]CS4
CS0
CS20CS19
CS7
C[0]
C[1]
C[2]
Circuito HDL-ARC (continuación)
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