novel packaging methods for ultra-thin monolithic sensors ladders construction

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

1

Novel packaging methods for ultra-thin monolithic sensors ladders construction

Wojciech DulinskiWojciech Dulinski11

on behalf of on behalf of PLUMEPLUME, , SERVIETTESERVIETTE and and PLUMETTEPLUMETTE Collaboration Collaboration

11IPHC/IN2P3 Strasbourg, FranceIPHC/IN2P3 Strasbourg, France55University of Bristol, UKUniversity of Bristol, UK

66DESY, Hamburg, GermanyDESY, Hamburg, Germany77University of Oxford, UKUniversity of Oxford, UK22IMEC, Leuven, BelgiumIMEC, Leuven, Belgium

33CMST, University of Gent, BelgiumCMST, University of Gent, Belgium44IFK, Goethe University, Frankfurt/M, GermanyIFK, Goethe University, Frankfurt/M, Germany

88CERN, GenevaCERN, Geneva

Outline Short status of MAPS development at IPHC PLUME: the lightweight ladder based on standard flex PCB Embedding in plastics projects (two different process approach) Conclusions and prospects

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

2

Monolithic Active Pixel Sensor: effective use of a thin epitaxial layer (10 – 20 µm) for MIP tracking

IPHC-DUT christine.hu@ires.in2p3.fr 714-18/01/2008

iPHC

Metal layers

Polysilicon

P-Well N-Well P-Well

N+ N+ P+ N+

Dielectric for insulation and passivation

Charged particles

100% efficiency.

Radiation

--

--

--

- ++

+++

++

- +- +- +

P-substrate (~100s m thick)

P-epitaxial layer(up to to 20 m thick)

Potential barriers

epi

sub

N

Nln

q

kTV

R.T.

Fast and more efficient charge collection should be radiation tolerant

past present

Industrial availability of high resistivity substrate (epi) in a standard CMOS

process

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

3

Present status of MAPS: just one example of mature design

Mimosa 26

Binary sparsified readout sensor for EUDET beam telescope: > 2 cm2 active area, 0.7 Mpixel tracker- Medium speed readout (100 µm integration 10 kFrame/s)- Spatial resolution < 4 µm for a pitch of 18.4 µm- Efficiency for MIP > 99.5 %- Fake hit rate < 10-6 - Radiation hardness > 1013 n/cm2 (high resistivity epi substrate)- Easy to use, “off-shell” product: used already in several application

-Recent newcomer : Ultimate sensor for STAR Microvertex upgrade (~4 cm2)

- Radiation hardness: >1014 n/cm2 attainable?

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

4

Can be very thin (~25 µm of silicon in total) and still fully efficient!

Problem: how to handle, interconnect and at the end built a low mass ladder with such a thin device?

One of the main feature of MAPS

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

5

PLUME concept: double-sided ladder (ILC compatible)

-2x6 Mimosa26 sensors-Standard flex PCB: kapton + Cu (two layers)

-SiC foam for spacer between layers

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

6

Expected PLUME material budget: only air flow cooling!

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

7

Current status of PLUME prototype: single sided flex

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

8

PLUME thermal study: M26 parameters

“Rolling shutter”, column parallel processing: only processed pixel row dissipate power!

- Total 730 mW (1/3 for pixel, discri and digital)- 250 mW/cm2 (160 mW/cm2 for STAR Ultimate)- 1.1 µW/pixel (5-10 µW/pixel for time continuous shaping ~1 µs)

- Power dissipation distributed unevenly: hot spots!

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

9

PLUME thermal study: simulationsHot spots with temperature of above 100 °C!

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

10

PLUME thermal study: results

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

11

Effects of temperature distribution on electrical parameters: S-curve of Mimosa 26 on PLUME ladder

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

12

Add heat-spread layer? The best would be based on CVD diamond! Or carbon fibers, excellent also for mechanics…

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

13

- Partner restricted PTW Oct. 2010 - HUMAN++

Stands for :

ULTRA THIN FILM CHIP PACKAGING

Polyimide 1

Polyimide 2

In short : Off-the-shelf die

Thinned down to ± 20-30 µm

Packaged between two polyimide foils

Metallisation : fan-out

Circuit contact through vias

Result : Flexible package

Thin : 50-70 m

Embeddable in commercial flexible PCB

SERVIETTE: use of UTCP by IMEC…

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

14

•Placement (face up) of IC

• Polyimide on rigid carrier with release layer (KCl)

• Dispense/spin of BCB

• Chip thinning

• Metallization: TiW (50nm) + Cu(1µm)

• Electroplating : Cu (5µm)

• Lithography to pattern metal• Encapsulation polyimide spinning• Release from carrier

•Photo definable polyimide spinning (20µm))

• Opening vias using lithography• Cleaning of contact pads

UTCP flow: overview

60 m

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

15

First results: Mimosa18 mechanical grade sample

Submitted for fabrication more thana year ago, very slow progress since…

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

16

PLUMETTE: “standard” PCB process for chip embedding in plastic foils (R. de Oliveira, CERN)

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• Gluing between two kapton foils

• Metallization: Al (5-10 µm)

• Lithography to pattern metal

• Opening vias using lithography

• Gluing of another kapton foil for deposition of second metal layer

• Single module: intermediate tests

• Complete ladder assembling, laser cut along sensor edges

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

17

PLUMETTE: details of 1st, “redistribution” metal layer

If too difficult for PCB-standard lithography (too small feature size), this post-processing step can be provided by CMOS foundry (discussion with AMS, 5th metal in 0.35 µm process)

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

18

PLUMETTE: details of 4 metal layer flex

Impedance of readout lines (last metal, 100 µm width, 100 µm gap) as a function of kapton thickness: 100 Ω

for 60 µm thick kapton (last layer)

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

19

Future techniques: stitching (“one die per wafer”)

Maximum length of monolithic ladder (8’ wafer): 10 –15 cm

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

20

On going work and future plans: use of Vertical Integration Process (3D Electronics)

3-tiers, heterogeneous CMOS, ultra-thin and edgeless MAPS

Bonding pads

20 µm

Sensor comprised of several active silicon layers: sensor,

analog processing, digital processing, memory,

optoelectronics layer…

Total thickness of this stack is still ~50 µm!

- Possible decrease of power per pixel (by order of magnitude):see Yavuz Degerli talk from FEE-2009

- Elimination of some “hot spots”

Wojciech.Dulinski@ires.in2p3.fr

FEE-2011, Bergamo University

21

- Ultra thin packaging technology seems to be interesting option for ultra light sensor ladders construction

- It is the must, if one wants to take full profit from MAPS tracking performances (front-end mechanics is as important as front-end electronics)

Conclusions

Outlook

- Double-sided PLUME ladder by autumn 2011, followed by beam tests

- Delivery of working Mimosa18 sensors embedded at IMEC: June/July ?

- Delivery of single Mimosa26 embedded at CERN in June, full PLUME compatible ladder (six M26) in September/October

- Stitching exercise next year?