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IBM Labs in Haifa © 2005 IBM Corporation

Path Based System Level Stimuli GenerationShady Copty, Itai Jaeger, Yoav Katz

Yoav KatzSimulation-Based Verification MethodsIBM Haifa Labs

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BackgroundDesign Complexity

Designer Productivity

Productivity Gap1990 2000 2005

System-on-a-Chip (SoC)Methodology

Time-to-Market Trend

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System Verification

System verification is aimed at validating the integration of several

previously verified cores in a relatively short time.

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Challenges in System Level Stimuli Generation

� Specifying system level scenarios in an abstract form�While generating requiredlow level stimuli

� Generating coordinated stimuli between cores

� Reusing of test specification and verification environment code

� Quickly adapting to configuration topology changes

� Adapting to new cores

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Approach #1: Combining Lower Level Drivers

IP1

Driver

IP2

Driver

IP2

Driver

Driver Driver Driver BUS

� Advantages�Simple�Quickly adapts to new cores�Reuse of core VIP

� Disadvantages�Not system level verification

�No coordinated stimuli�No system level scenarios

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Approach #2: Transaction Based Verification

IP1

Transactor

BUS

IP2 IP2

Test

� Advantages� System level abstraction� Allows complex coordinated

stimuli � Allows reuse of test specification

� Disadvantages� Transactor code is monolithic� Difficult to adapt to configuration

changes� Difficult to adapt to new

components / changedfunctionality

Transactor

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X-Gen

� IBM’s state-of-the-art system-level stimuli generator� Focus on the system as a whole, including

� Processors� Memory sub-system� Complex interconnect (bridges, clustering)� I/O

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X-Gen Overview

Test Specification X-Gen Engine

Interactions(Transactions) Configuration

(Toplogy)

Components (Cores)

Abstract System Model

Test Case

CSP Solver

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Component (Core) Behavior

I/O Bridge

PLBPort

PHBPort

SA

D D

IA

AddressTranslation

Register

O O

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A DMA Interaction

Interactions (Transactions)

� Interaction: Acts, Actors

� A CPU stores to the doorbell register of the DMA engine

PLB

CPU#4CPU#3CPU#2CPU#1

DMAEngine

BridgeInterrupt

ControllerMemory

PHB

IO BFM#2

IO BFM#1

� The data is moved from the IOport to memory

� The DMA engine interrupts the initiating CPU

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Configuration

PLB

CPU#4CPU#3CPU#2CPU#1

DMAEngine

BridgeMemory

PHB

IO BFM#2

IO BFM #1

� Represents the physical and logical connection between components

InterruptController

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X-Gen Generation Scheme

� For each interaction in the test specification1. Select the participating components and the path(s) between them2. Select the values of relevant properties of the participating

components (e.g. io_address, system_address, data)3. Initialize the relevant test case resources

(data memory, translation tables, processor instructions, BFM commands)

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X-Gen Generation Scheme – Path selection

� Example interaction: CPU_to_BFM_MMIO

PLB

CPU#2

Bridge#2

IO BFM#2

CPU#4CPU#3CPU#1

DMAEngine

Memory

PHB #1

IO BFM #1

Bridge #1

PossibleInitiators

PossibleTargets

PHB #2

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X-Gen Generation Scheme – Property Selection

IO

BFM

#2

PLB

#2

Brid

ge#2

PLB

CP

U#2

SA

SA

D D

EA

SA

D

SA

D D D

IA IA

D

IA

D

IA

PPPP

=

=

=

= = =

==

Reg

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Advantages

� Adapts well to configuration changes

New interaction +Modify components

New transactor New system level interaction

New component

Modify component

Change configuration

X-Gen changes

Modify multiple transactors

New component with same interactions

Modify multiple transactors

Changes to existing component

Modify multiple transactors

New component of existing type

Pure transaction modelling change

DUT change

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More Advantages�

� Coordinated stimuli between interactions� Generation state is maintained in the components

� Scalable CSP solution� Can handle dozens of components and thousands of possible paths

� Disadvantages� Modeling requires expertise� CSP partitioning limitations

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X-Gen’s Track Record

� Used in IBM’s state of the art systems verification�Low to high end PowerPC servers

�Dozens of processors�IO interfaces (e.g. PCIX/E, HyperTransport)�Complex clustering architectures (e.g. Infiniband)

�Gaming Technologies�PowerPC and propriety processors�Dedicated DMA engines

� Assisted in discovery of hundreds of hardware bugs