pex 8311rdk hardware reference manual
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PEX 8311RDK Hardware Reference Manual
PEX 8311RDK Hardware Reference Manual
Version 0.90
December 2005
Website: http://www.plxtech.com Support: http://www.plxtech.com/support
Phone: 408 774-9060 800 759-3735
Fax: 408 774-2169
© 2005 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX8311-RDK-HRM-P1-0.90
Printed in the USA, December 2005
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. v
CONTENTS 1. General Information ............................................................................................................................... 1
1.1 PEX 8311 Features ......................................................................................................................... 2 1.2 PEX 8311RDK Features.................................................................................................................. 2
2. PEX 8311RDK System Architecture ...................................................................................................... 3 3. PEX 8311RDK Hardware Architecture .................................................................................................. 4
3.1 PEX 8311 PCI Express Bridge Device............................................................................................ 4 3.2 Serial EEPROM............................................................................................................................... 4
3.2.1 SPI EEPROM............................................................................................................................ 5 3.2.2 Microwire Serial EEPROM........................................................................................................ 5
3.2.2.1 Microwire Serial EEPROM Contents ............................................................................... 6 3.3 Local and PCI Express Hardware Elements ................................................................................... 7
3.3.1 Local Clock................................................................................................................................ 8 3.3.2 Synchronous Burst SRAM ........................................................................................................ 8 3.3.3 Xilinx CPLD............................................................................................................................... 8 3.3.4 Internal Clock ............................................................................................................................ 8 3.3.5 PLX Option Module Connector ................................................................................................. 9 3.3.6 Hardware Memory Map .......................................................................................................... 10
3.4 PCI Express Interface.................................................................................................................... 10 3.4.1 RefClk ..................................................................................................................................... 10 3.4.2 PERST# .................................................................................................................................. 10
3.4.2.1 Reset Circuitry ............................................................................................................... 11 3.5 LED Indicators ............................................................................................................................... 11 3.6 PEX 8311RDK Power.................................................................................................................... 11
3.6.1 PEX 8311 Bridge Device Power ............................................................................................. 11 3.6.2 PEX 8311 Power Jumpers and Resistor options.................................................................... 12
3.7 Power Management Signaling....................................................................................................... 13 3.7.1 Wakeup ................................................................................................................................... 13
3.8 Endpoint/Root Complex operation ................................................................................................ 13 4. Mechanical Architecture....................................................................................................................... 15
4.1 Monitoring Points, Test headers, Indicators, Control, and DIP Switch Summary ......................... 16 4.1.1 Monitoring Points .................................................................................................................... 16 4.1.2 Headers................................................................................................................................... 16
4.1.2.1 Test Headers ................................................................................................................. 16 4.1.2.2 JTAG Headers ............................................................................................................... 16
4.1.3 Indicators................................................................................................................................. 17 4.1.4 Controls................................................................................................................................... 17
4.2 PEX 8311RDK Layout Information................................................................................................ 17 4.2.1 Trace Routing Design Rules ................................................................................................... 17 4.2.2 Power Decoupling................................................................................................................... 17 4.2.3 PCB Stackup........................................................................................................................... 18
4.3 MidBus LAI Footprints ................................................................................................................... 19 4.4 Prototyping Area............................................................................................................................ 19
4.4.1 Surface Mount Footprints........................................................................................................ 19 4.4.2 Uncommitted FPGA footprint .................................................................................................. 20
4.4.2.1 Uncommitted FPGA connections .................................................................................. 20 4.4.2.2 Uncommitted FPGA to PEX 8311 local bus .................................................................. 20 4.4.2.3 Programming the uncommitted FPGA........................................................................... 24 4.4.2.3.1 Programming the FPGA through the JTAG interface................................................ 24 4.4.2.3.2 Programming the FPGA through the GPIO............................................................... 27 4.4.2.3.3 Programming the uncommitted FPGA from the configuration PROM....................... 28
4.4.2.4 Uncommitted FPGA power supplies.............................................................................. 29 4.4.2.5 Uncommitted FPGA Pull-ups/downs ............................................................................. 30 4.4.2.6 Increasing the number of unused uncommitted FPGA I/O ........................................... 30
5. RDK Mode Configuration ..................................................................................................................... 31 6. Examples of Testing the OnBoard 32Kx32 SBSRAM with PLXMon ................................................... 33 7. CPLD Verilog Code.............................................................................................................................. 35
PEX 8311RDK Hardware Reference Manual, Version 0.90 vi © 2005 PLX Technology, Inc. All rights reserved.
7.1 Verilog Code.................................................................................................................................. 35 8. References........................................................................................................................................... 39 9. Bill of Materials / Schematics ............................................................................................................... 41
FIGURES Figure 1-1. PEX 8311RDK – Component Side View.................................................................................... 1 Figure 3-1. PEX 8311RDK Hardware Architecture ...................................................................................... 4 Figure 4-1. PEX 8311RDK Component Placement.................................................................................... 15 Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints..................................................................... 18 Figure 4-3. PEX 8311RDK Stackup ........................................................................................................... 18
TABLES Table 3-1. Long Serial EEPROM Load Registers ........................................................................................ 6 Table 3-2. Extra Long Serial EEPROM Load Registers............................................................................... 7 Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map .................................................................. 10 Table 3-4. PEX 8311RDK LED Indicators.................................................................................................. 11 Table 3-5. PEX 8311RDK Power supply currents...................................................................................... 12 Table 3-6. PEX 8311RDK Power jumper and resistor options................................................................... 12 Table 4-1. PEX 8311RDK Default Jumper Settings ................................................................................... 17 Table 4-2. Layer thickness ......................................................................................................................... 19 Table 4-3. Six (6) Surface Mount Footprints .............................................................................................. 19 Table 4-4. Uncommitted FPGA resistor configuration................................................................................ 21 Table 4-5. Altera Uncommitted FPGA JTAG interconnections .................................................................. 25 Table 4-6. Xilinx Uncommitted FPGA JTAG interconnections ................................................................... 26 Table 4-7. Programming the Altera Uncommitted FPGA through the GPIO.............................................. 27 Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO............................................... 28 Table 4-9. Platform Flash to Xilinx interconnect......................................................................................... 29 Table 5-1. RDK Board Mode Configuration................................................................................................ 31 Table 9-1. PEX 8311RDK Bill Of Materials ................................................................................................ 41
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. vii
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this document is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8311RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8311RDK, the PEX 8311 Rapid Development Kit, from a hardware perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for the creation of software for this product. This manual also includes a complete bill of materials and schematics.
REVISION HISTORY
Date Version Comments
December 2005 0.90 Initial Blue Book Release
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 1
1. General Information
The PLX PEX 8311RDK is a Rapid Development Kit based on the PEX 8311, a single-lane, PCI Express-to-local bus bridge device. The PEX 8311RDK provides a complete hardware and software development platform to facilitate getting designs up and running quickly, lowering risk and reducing time-to-market. The PEX 8311RDK allows the upstream PCI Express port of the PEX 8311 device to be connected to a host system slot by way of a standard PCI Express edge connector (the PEX 8311RDK is designed to plug into a PCI Express motherboard slot). On board Synchronous burst SRAM allows testing of data transfers and DMA operation.
The PEX 8311RDK is shipped pre-configured for de-multiplexed generic address/data bus (C mode) operation, but is very easily reconfigured for multiplexed address/data bus (J mode) applications. The RDK provides 5 surface mount QFP/SOIC/SSOP footprints and for hardware designers to easily add processors, DSPs, ASICs, FPGAs, memory, and I/O devices to test, simulate, and debug their designs without fabricating their own boards, saving considerable of time in the development process and reducing time to market. The PEX 8311RDK’s software, hardware and registers are backward-compatible with the PCI 9056RDK-LITE and PCI 9656RDK-LITE, simplifying the migration of existing PCI designs into PCI Express products.
LED7LED6
LED5LED4
PLX Technology , Inc .PEX8311 RDKCOPYRIGHT 2005
J3
JP1
U4
Regulator
J4
5VP
ower
Con
nect
or
POM Module Connector
PEX-MCM
JP2JP3JP4JP5
JTAGHeader
PEX8311
J5
Midbus
CPLD SYN_SRAM
66MHzOscillator forLocalClock
Socket
FPGAPQFP
SSOP
SSOP
Socket
1
Eeprom
Soc
ket
1
Eeprom
U9
Regulator
Test Headers +12V+5V
PEXC
LK
PERST#
LED 1
LED 2
LED 3
LED 4
PERST#
J1
U2
U5
U8
U3
Regulator
LAH1
LAH5
LAH2
LAH3 LAH6 LAH4
Prototyping Area
U6
SOIC
SSOP
J9
J7
J8
JTAGHeader J2
TP11
TP10
TP5
TP8
TP9
TP4
TP2
TP3
TP7
TP1
TP6
Figure 1-1. PEX 8311RDK – Component Side View
PEX 8311RDK Hardware Reference Manual, Version 0.90 2 © 2005 PLX Technology, Inc. All rights reserved.
1.1 PEX 8311 Features
Compliant to PCI Express Base Specification, Revision 1.0a
Local bus and register compatibility with PCI 9056 and PCI 9656 allows systems to migrate to PCI Express and leverage software compatibility
Integrated single PCI Express port and interface with x1 link, dual-simplex 2.5 Gbps SerDes
Configurable local bus supporting 8, 16 and 32 bit local bus architectures
Multiplexed and non-multiplexed local bus operation
Powerful high performance DMA engine supporting block, scatter gather, ring management and demand mode
Supports Endpoint and Root Complex Modes
Small package, enabling compact design
Low power consumption
3.3V I/O and 5V tolerant local bus
Serial EEPROMs used for optional boot configuration with Serial Peripheral Interface (SPI) and Microwire Interface
8-KB general-purpose shared RAM
1.2 PEX 8311RDK Features
PLX PCI Express-to-PCI bridge device in a 21 x 21 mm, 337-ball PBGA package
Single x1 PCI Express Edge connector for insertion into standard PCI Express slot of x1 or greater link width
Supports 32-bit C (default) or J mode Processor/Local Bus operation with speeds up to 66MHz
128KB synchronous burst SRAM with the CPLD memory controller demonstrates the PEX 8311 continuous burst feature
Jumpers for PEX 8311 hardware configuration
Socketable SPI and Microwire serial EEPROMs (3.3V devices supported)
Onboard probing points and logic analyzer connections
LEDs for link status visual inspection and power supply operation
Auxiliary ATX hard disk connector for additional power requirement support
Prototyping area with five (5) surface mount footprints, one (1) voltage regulator footprint, and one (1) 20x10, 0.1” through-hole grid
Pushbutton reset module
Socketed oscillator for Processor/Local Bus clock and local logic
PLX J-Bus Option Module (POM) connector for expansion
Option for on board PCI Express reference clock generation
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 3
2. PEX 8311RDK System Architecture
The PEX 8311RDK assists customers in evaluating PLX Technology’s PEX 8311 PCI Express to local bus bridge device, and to facilitate early development of customer designs with the PEX 8311. The board is designed to operate with the PEX 8311 configured in Endpoint mode. This allows bridging between a PCI Express base board and local bus processors or logic. The PEX 8311RDK is designed to showcase many of the PEX 8311 features when operating in Endpoint mode.
The PEX 8311RDK’s form factor is a eight-layer assembled 6.6"L x 8.15"W PC board. The local bus interface supports 8, 16 or 32-bit transfers, at up to 66 MHz. The PCI Express interface supports one lane operating at 2.5 Gbps.
PEX 8311RDK power is generated from the +12VDC and +3.3VDC, provided through the PCI Express edge connector. Additional +5VDC and +12VDC power can be provided using an external power supply plugged into the on board 4-pin ATX header.
PEX 8311RDK Hardware Reference Manual, Version 0.90 4 © 2005 PLX Technology, Inc. All rights reserved.
3. PEX 8311RDK Hardware Architecture
PEX8311PCI Express x1
Link
SerialEEPROMs
Local BusClock Circuit
66MHz
LOCAL BUSUp to 32-bit 66MHz
Address Bus
Data bus
Control Bus
POM Connector Test Headers
SynchronousSRAM
32Kx32
SRAMController
Data Bus
Ready# MemoryAddress
Bus
Controls
PEX 8311 RDK Hardware Block Diagram
7 32
8
SRAM Controller
Arbiter
Chip SelectGenerator
Controls8
Address
Xilinx CPLD
Bterm#
PCI Express100MHz clock
PCI Express100MHz Clock
Circuit(not populated)
MidbusConnector
(notpopulated)
x1
PCI
Express
Card
Edge
PCI ExpressPushbutton
Reset Circuit PrototypingArea &
Footprints
LED's forGPIO's and
powersupplies
Internal ClockCircuit
66MHz (notpopulated)
LocalClock
Figure 3-1. PEX 8311RDK Hardware Architecture
3.1 PEX 8311 PCI Express Bridge Device
The PEX 8311 (U1) is a high-performance PCI Express to local bus device that enables designers to migrate legacy designs to the new, advanced serial PCI Express. This 2-port device is equipped with a single-lane PCI Express port and a parallel local bus segment supporting multiplexed (J mode) and non-multiplexed (C Mode) operating modes. The PEX 8311 is capable of operating as an Endpoint or a Root Complex. The PEX 8311 bridge device is housed in a 21 x 21 mm, 337-ball PBGA package. Ball spacing is 1.0 mm. No additional cooling is required.
The PEX 8311 supports Direct Slave and Direct Master data transfers; in addition there are two DMA channels, and an Intelligent Messaging Unit. For more detailed information about the PEX 8311 please see the PEX 8311 data book.
3.2 Serial EEPROM
The PEX 8311 bridge device has two EEPROM’s associated with it. These EEPROM’s can be used to load configuration data on power-up.
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 5
3.2.1 SPI EEPROM
The SPI EEPROM (U2) is the Express Configuration EEPROM. This is largely used to control PCI Express performance and is not normally required to bring up the PEX 8311. The SPI EEPROM (U2) can also be used to pre-configure the on-chip 8K shared memory.
The SPI EEPROM (U2) is connected to an 8-pin DIP socket to allow removal and programming with external PROM programmer if required. The EEPROM can also be programmed through the PEX 8311 using the utilities provided. A pull-up resistor (R4) on the EERDDATA ball produces a value of FFh if there is no serial EEPROM installed.
The PEX 8311 supports up to 16 MB SPI serial EEPROM’s, utilizing 1, 2, or 3-byte addressing. The PEX 8311 automatically determines the appropriate addressing mode. The SPI operates at up to 25 MHz and can directly interface with the PEX 8311. The Atmel AT25640 device as used in the PEX 8311RDK is recommended. Other compatible 128-byte serial EEPROM’s include the Atmel AT25010A, Catalyst CAT25C01, and ST Microelectronics M95010W.
The SPI EEPROM on the PEX 8311RDK is blank when shipped.
3.2.2 Microwire Serial EEPROM The socketed 2Kbit Microwire serial EEPROM (U6) is the Local Configuration EEPROM and is used to control local bus behavior and assign appropriate address ranges. It is connected directly to the PEX 8311 and provides the configuration data to initialize the device after the system reset is removed. The EEPROM image is compatible with those of the PLX PCI 9x56 devices and may be loaded with those images to speed development. The Microwire EEPROM will be required for most designs to ensure that the correct address space ranges are assigned. A pull-up on EEDI/EEDO (R36) ensures that the RDK will boot if a blank EEPROM is installed. If no EEPROM is installed then a pull-down will be required on EEDI/EEDO (R39) to ensure that the device boots correctly.
PEX 8311RDK Hardware Reference Manual, Version 0.90 6 © 2005 PLX Technology, Inc. All rights reserved.
3.2.2.1 Microwire Serial EEPROM Contents
Table 3-1. Long Serial EEPROM Load Registers Serial
EEPROM Offset
Serial EEPROM Hex Value
Description Register Bits Affected
0h 86E1 Device ID PCIIDR[31:16] 2h 10B5 Vendor ID PCIIDR[15:0] 4h 0680 Class Code PCICCR[23:8] 6h 00AA Class Code, Revision of the PEX 8311 PCICCR[7:0] / PCIREV[7:0] 8h 0000 Maximum Latency, Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] Ah 0100 Interrupt Pin, Interrupt Line Routing PCIIPR[7:0] / PCIILR[7:0] Ch 0000 MSW of Mailbox 0 (User Defined) MBOX0[31:16] Eh 0000 LSW of Mailbox 0 (User Defined) MBOX0[15:0] 10h 0000 MSW of Mailbox 1 (User Defined) MBOX1[31:16] 12h 0000 LSW of Mailbox 1 (User Defined) MBOX1[15:0] 14h FFFE MSW of Range for PCI-to-Local Address Space 0 LAS0RR[31:16] 16h 0000 LSW of Range for PCI-to-Local Address Space 0 LAS0RR[15:0]
18h 0000 MSW of Local Base Address (Re-map) for PCI-to-Local Address Space 0 LAS0BA[31:16]
1Ah 0001 LSW of Local Base Address (Re-map) for PCI-to-Local Address Space 0 LAS0BA[15:0]
1Ch 0120 MSW of Mode/DMA Arbitration Register MARBR[31:16] 1Eh 0000 LSW of Mode/DMA Arbitration Register MARBR[15:0]
20h 2030 Local Miscellaneous Control Register 2 / Serial EEPROM Write-Protected Address Boundary
LMISC2[7:0] / PROT_AREA[7:0]
22h 8500 Local Miscellaneous Control Register 1 / Processor/Local Bus Big/Little Endian Descriptor Register
LMISC1 [7:0] / BIGEND [7:0]
24h 0000 MSW of Range for PCI-to-Local Expansion ROM EROMRR[31:16] 26h 0000 LSW of Range for PCI-to-Local Expansion ROM EROMRR[15:0]
28h 0000 MSW of Local Base Address (Re-map) for PCI-to-Local Expansion ROM EROMBA[31:16]
2Ah 0000 LSW of Local Base Address (Re-map) for PCI-to-Local Expansion ROM EROMBA[15:0]
2Ch 4343 MSW of Bus Region Descriptors for PCI-to-Local Address Space 0 and Expansion ROM LBRD0[31:16]
2Eh 00C3 LSW of Bus Region Descriptors for PCI-to-Local Address Space 0 and Expansion ROM LBRD0[15:0]
30h 0000 MSW of Range for Direct Master-to-PCI DMRR[31:16] 32h 0000 LSW of Range for Direct Master-to-PCI DMRR[15:0] 34h 6000 MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] 36h 0000 LSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[15:0]
38h 5000 MSW of Processor/Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16]
3Ah 0000 LSW of Processor/Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[15:0]
3Ch 0000 MSW of PCI Base Address (Re-map) for Direct Master-to-PCI DMPBAM[31:16]
3Eh 0000 LSW of Processor/Local Bus Address for Direct Master-to-PCI Memory DMPBAM[15:0]
40h 0000 MSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration DMCRGA[31:16]
42h 0000 LSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration DMCFGA[15:0]
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 7
Table 3-2. Extra Long Serial EEPROM Load Registers Serial
EEPROM Offset
Serial EEPROM Hex Value
Description Register Bits Affected
44h 8311 Subsystem ID PCISID[15:0] 46h 10B5 Subsystem Vendor ID PCISVID[15:0] 48h FFFE MSW of Range for PCI-to-Local Address Space 1 LAS1RR[31:16] 4Ah 0000 LSW of Range for PCI-to-Local Address Space 1 LAS1RR[15:0]
4Ch 0000 MSW of Local Base Address (Re-map) for PCI-to-Local Address Space 1 LAS1BA[31:16]
4Eh 0001 LSW of Local Base Address (Re-map) for PCI-to-Local Address Space 1 LAS1BA[15:0]
50h 0000 MSW of Bus Region Descriptors for PCI-to-Local Address Space 1 LBRD1[31:16]
52h 01C3 LSW of Bus Region Descriptors for PCI-to-Local Address Space 1 LBRD1[15:0]
54h 0000 Hot Swap Control/Status Register Reserved
56h 4C06 Hot Swap Control/Status Register / Hot Swap Next Capability Pointer HS_NEXT[7:0] / HS_CNTL[7:0]
58h 0000 Reserved Reserved 5Ah 0000 PCI Arbiter Control PCIARB[15:4] / PCIARB[3:0] 5Ch 7A02 Power Management Capabilities PMC[15:9,2:0]
5Eh 4801 Power Management Next Capability Pointer / Power Management Capability ID (the LSB is reserved)
PMNEXT[7:0] / PMCAPID[7:0]
60h 0000 Power Management Data / PMCSR Bridge Support Extensions (the LSB is reserved)
PMDATA[7:0]/ PMCSR_BSE[7:0]
62h 0000 Power Management Control/Status (Bits 15, 7:2, and 1:0 are reserved) PMCSR[15:0]
3.3 Local and PCI Express Hardware Elements As shown in Figure 3-1, the RDK hardware contains:
• PEX 8311 PCI Express I/O Accelerator • Four PEX 8311 Local Bus components (Local clock distribution, CPLD, SBSRAM, Test Headers,
and POM connector) • LED’s for GPIO and power supply status • Small prototyping area – including an uncommitted FPGA footprint • PCI Express Reset Circuitry (see section 3.4.2.1 Reset Circuitry) • A hardware development module for PCI Express clock generation (see section 3.4.1 RefClk) • A hardware development module for the PEX 8311 internal reference clock (see section 3.3.4
Internal Clock) The RDK’s Local Bus is pre-configured for non-multiplexed address and data bus operation (C mode), but it is user-configurable to allow multiplexed address and data operation (J Mode). (See Section 5 RDK Mode Configuration for details on re-configuring the RDK hardware for J Mode operation.) Once the board is correctly installed into a PC computer system, a host, such as the motherboard’s processor, can perform single cycle memory read/write cycles, multiple memory read/write cycles, and burst memory read/write cycles from/to the on-board SBSRAM in Direct Slave mode. The host can also program the PEX 8311 to perform DMA data transfers between the PCI Express bus and the SBSRAM.
PEX 8311RDK Hardware Reference Manual, Version 0.90 8 © 2005 PLX Technology, Inc. All rights reserved.
3.3.1 Local Clock
The PEX 8311 has a local clock input which is required for normal operation. The Cypress Semiconductor CY2305 Zero Delay 1-to-5 clock buffer (U7) provides onboard local clock distribution to the PEX 8311, SBSRAM, CPLD, test headers and the POM connector. The CY2305 input is sourced by the socketed onboard oscillator (U8). The socketed oscillator (U8) can be changed to allow PEX 8311 local bus operation at any frequency from 10 to 66MHz. The 10MHz minimum is a restriction of the CY2305, the local bus of the PEX 8311 can run at any frequency from 0 to 66MHz.
3.3.2 Synchronous Burst SRAM A 100-pin, 7.5ns, 32K x 32 Micron Synchronous Burst SRAM (U11) is used for Processor/Local Bus data storage on the RDK. During Direct Slave memory burst cycles, the SBSRAM performs continuous back-to-back single read cycles or single write cycles. The Xilinx CPLD SBSRAM controller (U10) does all of the timing conversion and generates the lower 8 address bits to the SBSRAM. The SBSRAM takes 7 upper address lines (LA16-LA10) directly from the PEX 8311 and 8 lower address lines (MA[9:2]) from the SBSRAM controller. The data lines of the SBSRAM are directly connected to the PEX 8311 local data bus (LD31-LD0).
3.3.3 Xilinx CPLD A 5ns Xilinx XC9572XL-5TQ100C CPLD (U10) is used as the SBSRAM controller, external Processor/Local Bus arbiter, and chip select generator. The SBSRAM controller in the CPLD generates the lower 8-bit memory address (MA[9:2]), SBSRAM chip select (SRAMCS#), SBSRAM output enable (SRAMOE#), and SBSRAM byte write enables (SRAM_BW_[3:0]) to the SBSRAM. It latches the starting address signals (LA[9:2] for C mode and LAD[9:2] for J mode), and uses its built-in internal address counter to advance the addresses to the SBSRAM. The SBSRAM controller also generates the active low ready signal (READY#) to terminate normal PEX 8311 memory cycles and also generates the active low (BTERM#) input to the PEX 8311 to break the continuous burst memory cycle when its internal address counter reaches the final count (FFh). The external Processor/Local Bus arbiter in the CPLD accepts the Processor/Local Bus request signals (LBR [1:0]) from Processor/Local Bus masters, if there are any, and the bus request from the PEX 8311 (LHOLD). It generates bus grant signals LBG [1:0] to the Processor/Local Bus masters and LHOLDA to the PEX 8311. The chip select generator in the CPLD generates the SBSRAM chip select (SRAMCS#) and four additional active low chip selects for the Processor/Local Bus devices. The chip select signals are partially decoded from the upper four address lines (LA31-LA28) on the Processor/Local Bus. They can be re-programmed by altering the CPLD Verilog code.
3.3.4 Internal Clock The PEX 8311 requires an internal clock source in addition to the PCI Express clock and the local clock. When the PEX 8311 is operating in Endpoint mode the PEX 8311 will generate the internal clock itself. The internal clock output (CLKOUT, ball A8) is fed directly to the internal clock input (CLKIN, ball A15) via the 0 ohm series resistor R53. When the PEX 8311 is operating in Root Complex mode then the internal clock must be provided from an external source. While the PEX 8311RDK is not designed to operate in Root Complex mode provision has been made for an external clock oscillator to provide the internal clock to the PEX 8311. The components for the external clock are not assembled nor do they appear on the BOM. Customers who require this feature must source and assemble the components themselves. PLX takes no responsibility for boards damaged during this operation If the external oscillator is to be used remove R53 and assemble R52, R150, C96, C97 and U13. The maximum operating frequency for U13 should be 66MHz.
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 9
3.3.5 PLX Option Module Connector The PLX Option Module Connector (J3) assumes that the Local Bus is configured for 32-bit multiplexed address/data bus (J mode) operation. (See Section 5 - RDK Mode Configuration - for details on re-configuring the RDK hardware for J Mode operation.) It can be used for expansion and prototyping. Both/either a master and/or slave devices may be connected to this connector, which resides at Local Bus address range 1000 0000 – 1FFF_FFFFh. The external arbiter in the CPLD uses CS0# to select the POM module. Schematic sheet 6 provides the connector signal details. The connector to mate to J3 can be purchased from AMP distributors the part number is: 6-104652-0
PEX 8311RDK Hardware Reference Manual, Version 0.90 10 © 2005 PLX Technology, Inc. All rights reserved.
3.3.6 Hardware Memory Map The PEX 8311RDK Local Bus memory map is shown in Table 3-3.
Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map
Hex Address Range Device Chip Select Comments
FFFF FFFF 5000 0000 Unused _ Available
4FFF FFFF 4000 0000
Uncommitted FPGA (FP2) CS3# Available &
Re-programmable
3FFF FFFF 3000 0000 Unused CS2# Available &
Re-programmable
2FFF FFFF 2000 0000 Unused CS1# Available &
Re-programmable
1FFF FFFF 1000 0000 J mode POM connector CS0# 32-bit, multiplexed
address/data bus
0FFF FFFF 0002 0000 Unused _ Available
0001 FFFF 0000 0000
Synchronous burst SRAM 32Kx32
SRAMCS# 8-, 16-, or 32-bit access
3.4 PCI Express Interface
The PCI Express interface is a male card edge connector, based on the PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a for an x1 interface. In addition to the PCI Express TX/RX pairs the card edge provides +12 VDC and +3.3 VDC, RefClk, and PERST#. The PCI Express TX/RX signals are laid out as 100-Ohm, controlled-impedance, microstrip-differential pairs. Trace length mismatch within signal pairs is not greater than 0.005".
3.4.1 RefClk
PCI Express RefClk enters the PEX 8311RDK through the PCI Express card edge (male) connector. RefClk is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch is not greater than 0.005".
Land is provided for the PCI Express RefClk to be generated onboard by an optional clock synthesizer (U12), using a 25-MHz crystal for the seed frequency. The PEX 8311RDK can use the IC557G-03 part from Integrated Circuit systems, Inc., though any comparable synthesizer is sufficient. RefClk is routed to the PEX 8311. An unused 100MHz reference clock (REFCLK2) is also available from (U12). RefClk routing is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch within this pair is less than 0.005". When using the optional on board clock generator R12 and R13 should be removed to ensure that the locally generated clock is not driven to the PCI Express edge connector (P1). In addition, R1 and R2 should be populated to route the on board clock to the PEX 8311. The components for the on-board PCI Express clock circuitry are not assembled nor do they appear on the BOM. Customers who require this feature must source and assemble the components themselves. PLX takes no responsibility for boards damaged during this operation.
3.4.2 PERST#
PERST# is the fundamental Reset signal to the PEX 8311, from the PCI Express edge connector.
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3.4.2.1 Reset Circuitry The reset pushbutton (SW1) allows the user to force the PEX 8311 PERST# signal low. This causes a full reset of the device and the local bus logic. Pressing the reset button causes LRESET# to be asserted and will cause all EEPROM values to be re-loaded. Pressing the pushbutton reset will also clear all configuration registers including the PCI Express configuration registers. The PEX 8311 will have to be re-enumerated by the host before it will respond to PCI Express memory transactions.
3.5 LED Indicators
The PEX 8311RDK provides several LED indicators, including power-on indication and programmable PEX 8311 GPIO lane status indication. Table 3-4 provides a quick explanation of each LED indicators.
By default GPIO[3:1] are configured as inputs and pulled high and GPIO0 shows the link status. By changing GPIOCTL[13:12] in the SPI EEPROM (U2) the GPIO lines can be reconfigured to reflect the lower four bits of the LTSSM state machine. See the PEX8311 data book for additional details.
Table 3-4. PEX 8311RDK LED Indicators
Indicator Type Location LED ON LED5 PCI Express 12V power on LED6 3.3V power is on Board Power Indication LED8 2.5V power is on
GPIO0 LED1 Output
OFF (0) – Link Down ON (1) – Link Up
GPIO1 LED2 ON, GPIO1 = Input by default GPIO2 LED3 ON, GPIO2 = Input by default GPIO3 LED4 ON, GPIO3 = Input by default
3.6 PEX 8311RDK Power
The PEX 8311RDK has two sources for DC power. The first source is the card edge connector (P1). This x1 connector provides up to 500 mA at +12VDC, and 3.0A at +3.3VDC. Card edge power is intended to power only PEX 8311RDK components.
The second source, the ATX 4-pin connector (J4), provides +12VDC, and the +5VDC power supplied to the POM connector.
The electronic devices on the RDK require +1.5V, +2.5V, and +3.3V DC power. A 5A LDO regulator (U4) is used to convert the PCI Express +12 VDC to +3.3 VDC, a 2.5A LDO regulator (U9) is used to convert the PCI Express +3.3 VDC to +2.5 VDC and a 250mA regulator (U3) is used to convert the PCI Express +3.3 VDC to +1.5 VDC power for the on board devices. As long as the output current from the voltage converter remains less than the maximum current outputs from the LDOs, the RDK board will function correctly.
3.6.1 PEX 8311 Bridge Device Power
The PEX 8311 bridge device power requires the following:
VDD Core +1.5 VDC ±10%
+2.5 VDC ±10%
VDD I/O +3.3 VDC ±10%
Care must be taken to ensure that the power sequencing requirements of the PEX 8311 are met – please refer to the PEX 8311 data book for further details.
As shipped the absolute maximum current required for the PEX 8311RDK supplies is detailed in Table 3-5.
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Table 3-5. PEX 8311RDK Power supply currents
Power Supply Maximum required by the RDK Maximum available from the Regulator
+1.5 VDC 240mA 250mA
+2.5 VDC 220mA 2.5A
+3.3 VDC 450mA 5A1
Note 1: A maximum of 1.8A is available when U4 is fed from the 12V supply of a 10W PCI Express connector.
When using the 1.5V supply to provide power to the uncommitted FPGA it may be necessary to change U3 to a larger regulator to ensure sufficient power supply current is available.
3.6.2 PEX 8311 Power Jumpers and Resistor options
Various power jumpers and resistor options are available on the PEX 8311 RDK to allow the power consumption of the PEX 8311 to be measured under different operating conditions.
Table 3-6 details the jumper and resistor settings for the main power options. For the uncommitted FPGA power options please see section 4.4.2.4 Uncommitted FPGA power supplies.
Table 3-6. PEX 8311RDK Power jumper and resistor options
Jumper Factory Setting Description J7 CLOSED +3.3V supply to PEX 8311 J8 CLOSED +1.5V supply to PEX 8311 J9 CLOSED +2.5V supply to PEX 8311
R21 ASSEMBLED Link PCI Express 12V supply to U4 (+3.3V regulator) R22 NOT ASSEMBLED Link ATX (J4) 12V supply to U4 (+3.3V regulator) R23 ASSEMBLED U4 (3.3V Regulator) provides +3.3V supply to RDK R27 NOT ASSEMBLED PCI Express 3.3V supply (P1) provides +3.3V supply to RDK
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3.7 Power Management Signaling
Local devices assert the PMEIN# pin to signal a Power Management event. The PEX 8311 converts the PMEIN# signal to PCI Express Power Management Event (PME) messages. There are no internal events that cause a PME message to be sent upstream.
When the PME message is sent to the host, the PWRMNGCSR register PME Status bit is set and a 100-ms timer is started. If the status bit is not cleared within 100 ms, another PME message is sent.
When the upstream device is powering down the downstream devices, it first places all devices into the D3hot state. It then sends a PCI Express PME_Turn_Off message. After the PEX 8311 receives this message, it stops sending PME messages upstream. The PEX 8311 then sends a PME_TO_Ack message to the upstream device and places its link into the L2/L3 Ready state. The downstream device is now ready to be powered down. If the upstream device changes the PEX 8311 power state back to D0, PME messages are re-enabled. The PCI Express PME_Turn_Off message terminates at the PEX 8311, and is not communicated to the PCI devices. The PEX 8311 does not issue a PM_PME message on behalf of a downstream PCI device while its upstream link is in the L2/L3 non-communicating state.
To avoid loss of PME# assertions in the conversion of the level-sensitive PMEIN# signal to the edge- triggered PCI Express PM_PME message, the PMEIN# signal is polled every 256 ms by the PEX 8311 and a PCI Express PM_PME message is generated if PME# is asserted.
The PMEIN# signal is used only when the PEX 8311 is in Endpoint Mode.
3.7.1 Wakeup
The PEX 8311 asserts the WAKEOUT# signal or sends a PCI Express beacon for the following:
PMEIN# pin is asserted while link is in L2 state
PCI Express beacon is received while link is in L2 state
PCI Express PM_PME Message is received
A beacon is transmitted if the following are true:
PMEIN# pin is asserted while link is in L2 state
DEVSPECCTL register Beacon Generate Enable bit is set
PWRMNGCSR register PME Enable bit is set
The WAKEOUT# signal is used only when the PEX 8311 is in Endpoint mode.
3.8 Endpoint/Root Complex operation
The PEX 8311 RDK has been designed to demonstrate the operation of the PEX 8311 in Endpoint Mode. While the PEX 8311 RDK has not been designed for Root Complex mode operation it is possible to achieve limited Root Complex mode functionality. The following notes indicate how this may be achieved. PLX has not tested operation of the board in Root Complex mode so customers who require this feature do so at their own risk and must source and assemble the components themselves. PLX takes no responsibility for boards damaged during this operation
To operate the PEX 8311 in Root Complex mode the PEX 8311 ROOT_COMPLEX# input should be pulled low by removing R6 and adding R7. In Root Complex mode the local bus of the PEX 8311 will be the upstream bus so some local intelligence will need to be added to act as the system host and enumerate any downstream device. Local intelligence may be added by attaching a suitable processor to either the POM (J3) connector, the test headers (LAH1-6) or by using the prototyping footprints.
When operating in Root Complex mode the internal clock (CLKIN) of the PEX 8311 must be supplied by an external clock source. To use the clock source on the RDK remove R53 and assemble R52, R150, C96, C97 and U13. The maximum operating frequency for U13 should be 66MHz.
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As the PEX 8311 is now the upstream device it may be necessary for the PEX 8311 RDK to source the PCI Express clock. This can be achieved by populating the onboard PCI Express clock circuit – see sheet 7 of the schematics. To route the PCI Express clocks to the PEX 8311 remove R12 and R13 and insert R1 and R2.
When operating in Endpoint mode the power for the PEX 8311RDK is normally provided by the PCI Express edge connector. If power is unavailable from this connector other means must be used to provide the +12V and +3.3V required by the board. It is possible to use the ATX connector (J4) to provide +12V to the 3.3V regulator U4 by removing R21 and populating R22 with a 0 ohm jumper. The PCIE3.3VCC can then be provided by U4 by populating R27 with a 0 ohm jumper. Extreme care must be taken to ensure that the power sequencing requirements of the PEX 8311 are still met when using the supplies in this manner. If there is any doubt with regards to power sequencing use one or more of J7, J8 and J9 to provide the supplies to the PEX 8311 from properly sequenced external sources.
The PCI Express edge connector is obviously designed for use in Endpoint mode as an adapter card. A suitable converter will be required to allow other PCI Express devices/cards to be plugged into the RDK. In addition, it may be necessary to provide a downstream PCI Express clock. The spare REFCLK2 may be used for this function although care will be required with regards to the routing of this to the downstream device.
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4. Mechanical Architecture
Figure 4-1 illustrates the PEX 8311RDK and component placement.
Figure 4-1. PEX 8311RDK Component Placement
The PEX 8311RDK’s form factor is based on the PCI Express CEM specification. The board is an eight-layer 6.6"L x 8.15"W PC board. The board height is greater than that noted in the PCI Express CEM specification and care must be taken to ensure that the board will fit within the target PC. It may be necessary to leave the case of the PC open or use an open chassis PC when using the PEX 8311 RDK. If this is the case then appropriate heath and safety measures should be taken when using the system in this manner.
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4.1 Monitoring Points, Test headers, Indicators, Control, and DIP Switch Summary
This section summarizes the interfaces available on the PEX 8311RDK for controlling and monitoring PEX 8311 performance.
4.1.1 Monitoring Points
Six ground test points (TP3-8), are scattered across the PEX 8311RDK to provide probe reference points
Voltages to the PEX 8311 can be monitored at the following locations:
J8 (1.5 VCC)
J9 (2.5 VCC)
J7 (3.3 VCC)
Three 3.3 VCC test points (TP9-11), are scattered across the PEX 8311RDK to allow voltage monitoring.
TP1 is connected to the PEX 8311 PWR_OK output
TP2 can be used to monitor the PEX8311 internal clock
External power can be monitored at the ATX connector (J4)
J1 provides access to the PEX 8311 JTAG port; TCK, TDI, TDO, and TMS
LAH 1-6 Logic analyzer test headers to connect to monitor local bus activity, see Section 4.1.2.1 Test Headers
4.1.2 Headers
4.1.2.1 Test Headers
The RDK board has six (6) 0.1”, 2x10 logic analyzer headers (LAH1-6) that follow the HP format and can be used for probing or prototype area extension. All PEX 8311 Local Bus signals, configuration and status signals are well arranged within these headers. Headers LAH2 and LAH3 contain Local Bus address signals. Headers LAH4 to LAH6 contain Local Bus data signals. Headers LAH1 and LAH5 contain Local Bus control and status signals. These headers do not provide any power source. Schematic page 5 provides the connector signal details.
4.1.2.2 JTAG Headers
There are two independent JTAG test ports on the PEX 8311 RDK. J1 is a 0.1”, 6 x 1 header which allows access to the PEX 8311 JTAG interface. This can be used to check connectivity of the device and to allow customers to develop their own test programs. With the exception of BSDL models PLX does not provide any additional boundary scan test software for the PEX 8311 or the PEX 8311 RDK.
J2 is a 0.1” 9 x 1 header which is connected directly to the Xilinx CPLD (U10). This header allows the CPLD to be re-programmed by the user at any time. PLX does not provide the programming software or the lead to allow re-programming of the CPLD.
By reprogramming the CPLD the user can change the functionality of the board. However, customers who re-program the CPLD do so at their own risk. PLX takes no responsibility for boards damaged or rendered inoperable while re-programming the CPLD.
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4.1.3 Indicators By default GPIO[3:1] are configured as inputs and pulled high. GPIO0 (and LED0) shows the link status. By changing GPIOCTL[13:12] in the SPI EEPROM (U2) the GPIO[3:0] lines and LED[3:0] can be reconfigured to reflect the lower four bits of the LTSSM state machine. See the PEX8311 data book for additional details. The other LED’s on the PEX 8311 indicate operation of the power supplies as detailed in Table 3-4. PEX 8311RDK LED Indicators
4.1.4 Controls
Table 4-1. PEX 8311RDK Default Jumper Settings
Jumper Factory Setting Description JP1 OPEN Pull down BAR0ENB# when closed JP2 OPEN GPIO0 drives LED1 JP3 1-2 Pull GPIO1 high JP4 1-2 Pull GPIO2 high JP5 1-2 Pull GPIO3 high J7 CLOSED +3.3V supply to PEX 8311 J8 CLOSED +1.5V supply to PEX 8311 J9 CLOSED +2.5V supply to PEX 8311
4.2 PEX 8311RDK Layout Information
4.2.1 Trace Routing Design Rules
The characteristic trace impedances are within the PCI Express specification (100 Ohm ±5%) for the differential, and within the PCI specification (55 Ohm ±10%) for the single-ended.
4.2.2 Power Decoupling
Power decoupling is provided by two means – plane capacitance (provided by the PCB stackup) and discrete decoupling capacitors. Plane capacitance filters noise above approximately 100 MHz. The footprints for the discrete decoupling capacitors are designed such that the inductance between the pad and plane is reduced by careful via placement. (Refer to Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints)
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Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints
4.2.3 PCB Stackup
The PEX 8311RDK is an 8-layer, 60-mil thick PCB. The target signal impedance for all routing layers is 55 Ohms ±10% single-ended impedance and 100 Ohms ±5% differential. Figure 4-3 details the layers used in the PCB manufactuer. The thickness of the various layers is detailed in Table 4-2. Layer thickness.
SOLDERMASK
PREPEG
LAMINATE
PREPEG
LAMINATE
PREPEG
LAMINATE
PREPEG
SOLDERMASKL8, SIGNAL 4
L1, SIGNAL 1
L2, GROUND
L3, SIGNAL 2
L4, POWER
L5, POWER
L6, SIGNAL 3
L7, GROUND
Controlled Impedance
Controlled Impedance
Controlled Impedance
Controlled Impedance
Figure 4-3. PEX 8311RDK Stackup
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Table 4-2. Layer thickness
Layer Type Thickness (mils)L1 0.60
Prepeg 4.00 L2 1.20
Core 5.00 L3 1.20
Prepeg 10.00 L4 2.60
Core 10.00 L5 2.60
Prepeg 10.00 L6 1.20
Core 5.00 L7 1.20
Prepeg 4.00 L8 0.60
4.3 MidBus LAI Footprints
The PEX 8311RDK has one half-size MidBus LAI footprint site (J5), which can be used to probe the high-speed PCI Express serial lanes, or populated with a shroud to allow third-party PCI Express logic analyzers to view the serial data.
The board is not shipped with the shroud assembled nor does the shroud appear on the BOM. Customers who require this feature must source and assemble the shroud themselves. PLX takes no responsibility for boards damaged during this operation.
4.4 Prototyping Area The RDK board contains a small prototyping area with various surface-mount footprints and a 20 x 10 0.1” pitch through-hole grid.
4.4.1 Surface Mount Footprints The prototyping area of the PEX 8311 RDK has six (6) surface mount footprints; see Table 4-3 for details. These footprints can accommodate a variety of devices. Although FP2 is deigned to accommodate FPGA’s other devices may be assembled on this footprint.
Table 4-3. Six (6) Surface Mount Footprints
Package Qty Pin Pitch Schematic Reference Example Applications
SOT-223 1 0.1” U14 Voltage Regulator
20-pin SSOP 1 0.05" FP1 Discrete Logic, Configuration Memory
28-pin SOIC 1 0.05" FP3 Discrete Logic
48-pin SSOP 2 0.025" FP4, FP5 Discrete Logic, data transceivers
144-pin PQFP 1 0.5mm FP2 FPGA’s, CPLDs, TI C542/KC542/LC548/ LC549/VC549, SH7604, IDT RC32364
PEX 8311RDK Hardware Reference Manual, Version 0.90 20 © 2005 PLX Technology, Inc. All rights reserved.
4.4.2 Uncommitted FPGA footprint The footprint FP2 has been designed to accept either a 100 pin Altera Cyclone FPGA such as the EP1C3T144 or a 100 pin Xilinx Spartan-3E FPGA. Although care has been taken to ensure that the configurable resistor options and connections comply with these devices it is recommended that the user carefully checks the latest documentation from the FPGA manufacturer in case of product changes subsequent to the publication of this document. In addition to the devices noted above other parts may also be assembled onto FP2. However, it is up to the user to determine the appropriate connections between the device and the PEX 8311 local bus. It should be noted that PLX does not provide FPGA code examples. Section 7 - CPLD Verilog Code – details the code which is used in the on board CPLD and this may be used as a guide.
4.4.2.1 Uncommitted FPGA connections The following modules can be used in conjunction with the uncommitted FPGA footprint:
• Unpopulated configuration Resistors • Configuration PROM • JTAG headers • User VCC • Through hole pads
Depending on the application one or more of these can be used to interconnect the FPGA to the existing circuitry on the PEX 8311 RDK, to set up FPGA configuration and/or to link to other uncommitted elements on the FPGA
4.4.2.2 Uncommitted FPGA to PEX 8311 local bus The uncommitted FPGA can be connected to the PEX 8311 local bus in two ways: a) Using the resistor options b) Wiring between the through hole pads (PF1 to PF144) and the test headers (LAH1 to LAH6) Any combination of the above can be used. Table 4-4 shows the resistor options used to connect the Altera Cyclone or the Xilinx Spartan-3E arrays to the PEX 8311 local bus.
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Table 4-4. Uncommitted FPGA resistor configuration
FPGA Pin No.
Xilinx Pin Name
Altera Pin Name
Local Signal
Bus No.
Xilinx link resistor
Xilinx Voltage R
Xilinx Capacitor
Altera link resistor
Altera Voltage R
Altera Capacitor
1 PROG_B INIT_DONENote 1 A1 180 User IO2 I/O I/O LD0 A2 182 1823 I/O I/O LD1 A3 186 1864 I/O I/O LD2 A4 191 1915 I/O I/O LD3 A5 196 1966 IP I/O LBG1 A6 198 1987 I/O I/O LD4 A7 200 2008 I/O 3.3V LA2_X A8 203 176 1029 1.2V GND A9 209 190 103 209 195
10 IP I/O BREQo A10 214 21411 GND I/O LA2_A A11 220 262 21912 IP I/O (nCS0) LA20 A12 225 22513 3.3V DATA0 USERo A13 231 201 104 Note 214 I/O nCONFIG GPIO0 A14 User IO 23415 I/O 1.5V LA4_X A15 237 239 210 10416 I/O CLK0 LCLK_T A16 User IO 24117 I/O CLK1 LA5_X A17 244 NC18 IP GND A18 User IP 249 23519 GND GND A19 178 235 178 23520 I/O nCEO USERi A20 User IO Note 221 I/O nCE LA6_X A21 183 Note 222 I/O MSEL0 LA7_X A22 187 Note 223 I/O MSEL1 LA8_X A23 192 Note 224 IP DCLK GPIO1 A24 User IP Note 225 I/O I/O LD5 A25 199 19926 I/O I/O LD6 A26 202 20227 GND I/O LA4_A A27 207 265 20528 3.3V I/O LA5_A A28 212 267 112 21129 IP 3.3V LA21_X A29 216 218 251 10730 2.5V GND A30 224 256 107 223 27231 I/O I/O LD7 A31 228 22832 I/O I/O LD8 A32 233 23333 I/O I/O LD9 A33 236 23634 I/O I/O LD10 A34 240 24035 I/O I/O LD11 A35 242 24236 IP I/O LINTo# A36 246 24637 GND I/O LA6_A B1 278 275 27738 IP I/O LSERR# B2 282 28239 I/O I/O LD12 B3 287 28740 INIT_B I/O Note 1 B4 292 User IO41 IP I/O CS_3# B5 294 29442 3.3V I/O LA7_A B6 300 281 115 29843 I/O GND LA9_X B7 305 307 29144 I/O 3.3V LA10_X B8 312 313 354 12345 1.2V GND B9 320 311 116 320 31846 GND 1.5V B10 323 380 323 374 12447 IP I/O LA16 B11 328 32848 IP I/O LA17 B12 333 33349 3.3V I/O LA8_A B13 327 117 33650 I/O I/O LD15 B14 338 338
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FPGA Pin No.
Xilinx Pin Name
Altera Pin Name Local Signal Bus
No.Xilinx link resistor
Xilinx Voltage R
Xilinx Capacitor
Altera link resistor
Altera Voltage R
Altera Capacitor
51 I/O I/O LD16 B15 340 34052 I/O I/O LD17 B16 343 34353 I/O I/O LD18 B17 346 34654 I/O I/O LD19 B18 349 34955 GND I/O LA9_A B19 344 27656 IP I/O LA18 B20 279 27957 IP I/O LA19 B21 283 28358 I/O I/O LD22 B22 289 28959 I/O I/O LD23 B23 293 29360 I/O I/O LD24 B24 295 29561 GND I/O LA10_A B25 303 366 30162 I/O I/O LD25 B26 308 30863 DIN GND Note 1 B27 315 317 36664 3.3V 1.5V B28 321 368 126 321 376 12665 2.5V GND B29 326 357 121 326 36366 I/O 3.3V LA11_X B30 329 330 369 12767 I/O I/O LD26 B31 334 33468 I/O I/O LD27 B32 337 33769 IP I/O DACK0# B33 339 33970 I/O I/O LD28 B34 342 34271 CCLK I/O Note 1 B35 345 User IO72 DONE I/O Note 1 B36 347 User IO73 GND I/O LA11_A C1 387 384 38674 I/O I/O LD29 C2 391 39175 I/O I/O LD30 C3 394 39476 I/O I/O LD31 C4 397 39777 I/O I/O ADS# C5 400 40078 IP I/O DACK1# C6 403 40379 3.3V I/O LA12_A C7 407 392 129 40580 1.2V GND C8 410 471 136 411 40181 I/O 3.3V LA15_X C9 416 417 408 13082 I/O I/O BIGEND# C10 422 42283 I/O I/O BLAST# C11 427 42784 IP I/O LA31/DT/R# C12 430 43085 I/O I/O LA29/ALE C13 433 43386 I/O CONF_DOGPIO2 C14 User IO Note 287 I/O nSTATUS GPIO3 C15 User IO Note 288 I/O TCK F_TCK C16 User IO 44289 IP TMS F_TMS C17 User IP 44590 GND TDO F_TDO C18 452 455 45091 I/O I/O BREQi C19 385 38592 I/O CLK3 LA12_X C20 388 NC93 I/O CLK2 PMEIN#_X C21 393 NC94 I/O I/O BTERM# C22 396 39695 IP TDI F_TDI C23 User IP 39996 I/O I/O CCS# C24 402 40297 I/O I/O DMPAF/EOT C25 404 40498 I/O I/O DREQ0# C26 409 40999 GND I/O LA13_A C27 415 474 413
100 3.3V I/O LA14_A C28 420 480 139 419
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FPGA Pin No.
Xilinx Pin Name
Altera Pin Name Local Signal Bus
No.Xilinx link resistor
Xilinx Voltage R
Xilinx Capacitor
Altera link resistor
Altera Voltage R
Altera Capacitor
101 IP GND LA22_X C29 424 426 475102 2.5V 3.3V C30 429 463 134 428 481 140103 I/O I/O DP0 C31 432 432104 I/O I/O DP1 C32 435 435105 I/O I/O DP2 C33 438 438106 I/O I/O DP3 C34 441 441107 IP I/O LA30/DEN# C35 444 444108 TMS I/O LA3_A C36 172 449109 TDO I/O LA15_A D1 171 493110 TCK I/O LA21_A D2 170 497111 IP I/O LA23 D3 502 502112 I/O I/O DREQ1# D4 507 507113 I/O I/O LBR1 D5 510 510114 IP I/O LA24 D6 513 513115 1.2V 3.3V D7 520 509 142 520 501 142116 I/O GND LA13_X D8 523 524 598117 I/O 1.5V LA14_X D9 530 532 536 143118 GND GND D10 538 547 537 620119 IP I/O LA25 D11 542 542120 IP I/O LA26 D12 548 548121 3.3V I/O LA22_A D13 562 144 554122 I/O I/O LD13 D14 558 558123 I/O I/O LINTi# D15 563 563124 I/O I/O LRESET# D16 568 568125 I/O I/O LBE0# D17 573 573126 I/O I/O LBE1# D18 578 578127 GND I/O D19 594 User IO128 GCLK8 I/O LCLK_T D20 496 User IO129 IP I/O D21 User IP User IO130 I/O I/O LW/R# D22 505 505131 I/O I/O LD14 D23 508 508132 I/O I/O READY# D24 511 511133 GND I/O LA28_A D25 518 615 516134 I/O I/O WAIT# D26 521 521135 I/O 1.5V LA3_X D27 526 528 605 150136 IP GND LA28_X D28 533 534 621137 2.5V 3.3V D29 540 585 146 540 580 146138 3.3V GND D30 545 603 153 545 618139 I/O I/O LD20 D31 551 551140 I/O I/O LD21 D32 555 555141 IP I/O LA27 D33 559 559142 I/O I/O LBE2# D34 564 564143 I/O I/O LBE3# D35 569 569144 TDI I/O PMEIN#_A D36 173 574
Notes:
1) The resistors used for the Xilinx programming pins will depend on the programming method used. Refer to Table 4-6, Table 4-8 and Table 4-9 for further details.
2) The resistors used for the Altera programming pins will depend on the programming method used. Refer to Table 4-5, Table 4-7 for further details.
With the exception of the resistors noted in Table 4-5, Table 4-6, Table 4-7, Table 4-8 and Table 4-9 the resistor value will normally be 0 ohms. Depending on the I/O of the FPGA some additional signal noise may be seen. If this is the case then the value of the resistors used to link to the local bus signals may be increased to form a series termination resistor. The value required will depend on the loading but will typically be in the range of 30 to 100 ohms.
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The power supplies for the FPGA’s normally require 2 resistors to be populated. One resistor is used to link the FPGA to a Vx bus (see the “…Link Resistor” column) and the second resistor is used to select the appropriate voltage (see the “…voltage R” column. In addition to the resistors it is recommended that the appropriate decoupling capacitor noted in the “…Capacitor” column is also assembled. The value required will be FPGA specific but is typically 10nF.
4.4.2.3 Programming the uncommitted FPGA There are three methods of programming or configuring the uncommitted FPGA:
a) Program through the JTAG interface b) Program using the PEX 8311 GPIO c) Program using the Configuration PROM
Of the above options (a) and (b) are available for both the Altera and Xilinx devices. Option (c) is only available for the Xilinx device.
4.4.2.3.1 Programming the FPGA through the JTAG interface Table 4-5 shows the resistor options and jumpers used to connect the 0.1”, 1 x 10 header JP6 to an Altera Cyclone array. JP6 can be used with programmers from Altera such as the ByteBlaster II, MasterBlaster etc. Depending on the programmer used pins 4 and 10 of JP6 may need to be pulled to the appropriate voltage, see notes 1 and 2 below and the appropriate Altera documentation.
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Table 4-5. Altera Uncommitted FPGA JTAG interconnections
FPGA JTAG program option
Connector [pin]
JTAG signal
Link Resistor (value) FPGA signal [pin] Pull-up resistor
or jumper Pull-down resistor or
jumper JP6 [1] F_TCK R442 (0) TCK [88] - R637 (10K)
JP6 [2] GND - - - -
JP6 [3] F_TDO R450 (0) TDO [90] - -
JP6 [4] VCC1 - - - -
JP6 [5] F_TMS R445 (0) TMS [89] R631 (10K) -
JP6 [6] VIO (3.3V) - - - -
JP6 [7] NC - - - -
JP6 [8] NC - - - -
JP6 [9] F_TDI R399 (0) TDI [95] R630 (10K) -
JP6 [10] NC2 - - - -
- - R185 (0) nCE [21] - R250 (0)
- - R439 (0) nSTATUS [87]3 JP5 [1-2] or
JP5 NC + R117 (10K)
-
- - R436 (0) CONF_DONE [86]4 JP4 [1-2] or
JP4 NC + R116 (10K)
-
- - R234 (0) nCONFIG [14]5,6 JP2 [1-2] or
JP2 NC + R114 (10K)
-
- - R189 (0) MSEL0 [22] 5 - R250 (0)
- - R194 (0) MSEL1 [23] 5 - R250 (0)
- - R230 (0) DATA0 [13] 5 - R266 (0)
Altera FPGA using ByteBlaster II,
MasterBlaster or ByteBlas 10 pin
header.
- - R197 (0) DCLK [24] 5,7 - JP3 [2-3]
Notes:
1) This pin is connected to TP20. Connect this pin to the same supply voltage as the download cable.
2) For some programmers it may be necessary to tie this pin to GND. 3) nSTATUS is connected to GPIO3. During configuration ensure that GPIO3 is an input. This is the
default condition for GPIO3. 4) CONF_DONE is connected to GPIO2. During configuration ensure that GPIO2 is an input. This is
the default condition for GPIO2. 5) The connections for these pins assume only JTAG configuration is being used. When supporting
non-JTAG configuration schemes see section 4.4.2.3.2. 6) nCONFIG is connected to GPIO0. The low to high transition begins configuration. If GPIO0 is
programmed to be an output configuration can be enabled using this signal. 7) DCLK is connected to GPIO1. When JP3 is in position 2-3 GPIO1 is strapped to GND and must
always be configured as an input. In addition to the above resistors the appropriate power supply and ground resistors must also be populated.
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Table 4-6 shows the resistor options and jumpers used to connect the 14 pin Target Interface connector (e.g. Molex part no. 87831-1420) JP7 to an Xilinx Spartan-3E array. JP7 can be used with appropriate programmers from Xilinx to configure the device using the JTAG interface. Table 4-6 also assumes that JP7 is connected directly to the Xilinx FPGA. It is also possible to create a scan chain with the configuration PROM (FP1) if used. This is detailed further in section 4.4.2.3.3. Depending upon the device, care should be taken with HSWAP_EN (pin 143). This pin configures the internal pull-up resistors. By default pin 143 will be connected to LBE3# (via R569) and is pulled high using RN2. This will disable the internal pull-ups. If the internal pull-ups are required this pin needs to be pulled low using R571 and R597.
Table 4-6. Xilinx Uncommitted FPGA JTAG interconnections
FPGA JTAG program option
Connector [pin]
JTAG signal
Link Resistor (value) FPGA signal [pin] Pull-up resistor
or jumper Pull-down resistor or
jumper JP7 [2] Vref (2.5V) - - - -
JP7 [4] F_TMS R172 (100Ω)1 TMS[108] - -
JP7 [6] F_TCK R170 (100Ω) 1 TCK [110] - -
JP7 [8] F_TDO R171 (0) 1 TDO [109] - -
JP7 [10] F_TDI R173 (100Ω) 1 TDI [144] - -
JP7 [12,14] NC - - - - JP7
[1,3,5,7,9, 11,13]
GND - - - -
- - R180 (0 or 56 Ω) 1,2 PROG_B [1] JP5 [1-2] or
JP5 NC -
- - R348 (0) DONE [72] R358 (330 Ω) 3 -
- - R292 (0) INIT_B [40] JP4 [1-2] or
JP4 NC + R116 (4K7) 4
R250 (0)
- - R309 (0) M0 [62] R368 (10K) -
- - R297 (0) M1 [60] - R361 (10K)
Xilinx Spartan-3E array using 14 pin Target Interface
Connector
- - R284 (0) M2 [57] 5 - R367 (10k)
Notes: 1) The value of the series current limiting resistor may vary depending on the programmer
and the programming voltage used. If using 3.3V programming then 56Ω is typically used. Refer to the appropriate Xilinx application notes for further information.
2) PROG_B is connected to GPIO3. GPIO3 is an input by default. 3) The resistor options shown pull DONE to 3.3V. Depending on the programming option
selected DONE can be pulled to 2.5V using R358. 4) INIT_B is connected to GPIO2. GPIO2 is an input by default. 5) If this pin is connected to LA19 through R283 then R284 and R367 are not required as
this pin is pulled high using RN11. In addition to the above resistors the appropriate power supply and ground resistors must also be populated.
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4.4.2.3.2 Programming the FPGA through the GPIO Table 4-7 shows the resistor options and jumper configurations required to interface the Altera cyclone FPGA programming pins to the PEX 8311 GPIO pins. The FPGA may then be configured by sending appropriate commands and data through the PEX 8311 GPIO to the FPGA programming pins. It should be noted that PLX does not provide software to program the FPGA. The SDK shipped with the PEX 8311 RDK provides .api calls to allow access to and changing of the GPIO pins. It is up to the user to develop software to program the FPGA used in their design. Table 4-7 assumes that programming of the Altera FPGA uses the Passive Serial Configuration method.
Table 4-7. Programming the Altera Uncommitted FPGA through the GPIO
PEX 8311 signal
Link Resistor (value) FPGA signal [pin] Pull-up resistor or
jumper Pull-down resistor or
jumper USERo R229 (0) DATA0 [13] - - GPIO0 R234 (0) nCONFIG [14] JP2 NC + R1141 - GND R185 (0) nCE [21] - R250 (0) VCC R188 (0) MSEL0 [22] 2 R254 (0) - GND R194 (0) MSEL1 [23] - R250 (0)
GPIO1 R197 (0) DCLK [24] JP3 NC3 - GPIO2 R436 (0) CONF_DONE [86] JP4 NC + R116 (10K) - GPIO3 R439 (0) nSTATUS [87] JP5 NC + R117 (10K) -
Notes:
1) Depending on the device used, the pull-up R114 may not be required. GPIO0 should be configured to be an output.
2) For some devices MSEL0 should be pulled to ground. If this is required remove R254 and add R264
3) GPIO1 must be configured to be an output. In addition to the above resistors the appropriate power supply and ground resistors must also be populated. Table 4-8 shows the resistor options and jumper configurations required to interface the Xilinx Spartan-3E FPGA programming pins to the PEX 8311 GPIO pins. The FPGA may then be configured by sending appropriate commands and data through the PEX 8311 GPIO to the FPGA programming pins. It should be noted that PLX does not provide software to program the FPGA. The SDK shipped with the PEX 8311 RDK provides .api calls to allow access to and changing of the GPIO pins. It is up to the user to develop software to program the FPGA used in their design. Table 4-8 assumes that programming of the Xilinx FPGA uses the Slave Serial Configuration method. Depending upon the device, care should be taken with HSWAP_EN (pin 143). This pin configures the internal pull-up resistors. By default pin 143 will be connected to LBE3# (via R569) and is pulled high using RN2. This will disable the internal pull-ups. If the internal pull-ups are required this pin needs to be pulled low using R571 and R597. If HSWAP_EN needs to be pulled low and LBE3# is required then connect R571 (0) and R597(4K7) and lift pin 4 or pin 5 of RN2. Depending on the device and power supplies used it may be necessary to add a resistor from the 2.5V rail to ground to manage reverse current. Typically this resistor would be 118Ω or 110Ω and would only be required if the 2.5V supply for the FPGA was sourced from the USRVCC – see the Xilinx application notes for further details regarding reverse currents.
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Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO
PEX 8311 signal
Link Resistor (value) FPGA signal [pin] Pull-up resistor
or jumper Pull-down resistor or
jumper GPIO3 R180 (56 Ω) PROG_B [1] JP5 NC -
USERi R347 (0) DONE [72] R348 (0) + R358 (330 Ω) 1 -
GPIO2 R292 (0) INIT_B [40] JP4 NC + R116 (4K7) -
VCC R309 (0) M0 [62] R368 (10K) -
VCC R297 (0) M1 [60] R350 (10K) -
VCC R284 (0) M2 [57] 2 R367 (10K) -
GPIO1 R315 (0) DIN [63] JP3 NC -
GPIO0 R345 (56 Ω) CCLK [71] JP2 NC -
Notes:
1) R348 and R353 are only required if BitGen option DriveDONE = No – see the appropriate Xilinx data sheet for more details. Ideally pin 3 or pin 6 of RN10 should be lifted if R348 and R353 are used.
2) If LA19 is connected to this pin through R283 then R284 and R367 are not required as this pin is pulled high using RN11.
In addition to the above resistors the appropriate power supply and ground resistors must also be populated.
4.4.2.3.3 Programming the uncommitted FPGA from the configuration PROM Xilinx FPGA’s can be configured using Platform Flash In-System Programmable Configuration PROMs. FP1 is designed to accept the VO20/VOG20 packaged versions of the XCFxxS platform flash PROMs. Table 4-9 details the resistor configurations required to interface a platform flash assembled on FP1 to a Xilinx Spartan-3E array assembled on FP2. It also details the resistor options for connecting the platform flash JTAG interface to JP7 to allow the platform flash to be programmed using the JTAG interface. JP7 is the 14 pin Target Interface connector (e.g. Molex part no. 87831-1420) and can be used with appropriate programmers from Xilinx to configure the device using the JTAG interface. The programming method detailed in Table 4-9 is master serial mode. Other programming modes may also be selected using the appropriate resistor options. The JTAG TDO output from the platform flash is routed to the TDI input of the Xilinx FPGA. If the JTAG interface is not required the resistors marked with a † in Table 4-9 may be removed. Depending on the device and power supplies used it may be necessary to add a resistor from the 2.5V rail to ground to manage reverse current. Typically this resistor would be 118Ω or 110Ω and would only be required if the 2.5V supply for the FPGA was sourced from the USRVCC – see the Xilinx application notes for further details regarding reverse currents.
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Table 4-9. Platform Flash to Xilinx interconnect
Connector [pin]
JTAG Signal
Plaftorm Flash Signal [pin]
Link Resistor (value)
FPGA signal [pin]
Pull-up resistor or jumper
Pull-down resistor or
jumper JP7 [2] Vref (2.5V) - - - - - JP7 [4] F_TMS TMS [5] R164 (0) - - - JP7 [6] F_TCK TCK [6] R165 (0) - - - JP7 [8] F_TDO - R171 (0) † TDO [109] - - JP7 [10] F_TDI TDI [4] R163 (0) - - -
JP7 [12,14] NC - - - - - JP7 [1,3,5,7,9,
11,13] GND - - - - -
- - D0 [1] R161 (0) DIN [63] - - - - CLK [3] R162 (0) CCLK [71] - -
- - CF# [7] R166 (0) PROG_B [1] JP5 NC + R180 (0) +R117 (4K7) 1 -
- - OE/RESET# [8] R167 (0) INIT_B [40] JP4 NC + R292 (0) +R116 (4K7) 2
- - CE# [10] R169 (0) DONE [72] R348 (0) + R358 (330 Ω) 3
- - GND [11] R168 (0) - - - - TDO [17] R159 (56 Ω)†,5 TDI [144] - - - - VCCINT [18] R157 (0) - - - - - VCCO [19] R154 (0) 4 - - - - - VCCJ [20] R151(0) 4 - - -
JP7 [6] F_TCK TCK [6] R170 (56 Ω)† TCK [110] JP7 [4] F_TMS TMS [5] R172 (56 Ω)† TMS[108]
R309 (0) M0 [62] - R379 (10K) R297 (0) M1 [60] - R361 (10K) R284 (0) M2 [57] - R375 (10K)
Notes:
1) If GPIO3 is to be used JP5 can be connected to position [1-2]. Care must be taken to avoid accidentally placing the FPGA into programming mode or resetting the device.
2) If GPIO2 is to be used JP4 can be connected to position [1-2]. Care must be taken to avoid accidentally placing the FPGA into programming mode or resetting the device.
3) R348 and R353 are only required if BitGen option DriveDONE = No – see the appropriate Xilinx data sheet for more details. Ideally pin 3 or pin 6 of RN10 should be lifted if R348 and R353 are used.
4) R154 and R151 are used when 3.3V programming is required. Other programming voltages are possible but will require pull’s on the Xilinx array to be modified appropriately. See the Xilinx data sheets for further details.
5) If the Xilinx FPGA is not linked to the scan chain then remove R159 and add R158 (0). This will link the TDO of the Platform Flash to the JTAG connector TDO pin (F_TDO).
As noted above, in Table 4-9 the JTAG TDO output from the platform flash is routed to the TDI input of the Xilinx FPGA i.e. the Program Flash is the first device in the chain. The scan chain can also be configured so that Xilinx device is the first device in the chain by removing R159, R163 and R171 and populating R158 (0), R160 (0) and R173 (56 Ω).
4.4.2.4 Uncommitted FPGA power supplies The device mounted onto FP2 may require a voltage level not provided by the voltage regulators assembled on the RDK. To accommodate this, the uncommitted USRVCC circuit can be populated with an appropriate voltage regulator. Although the schematics show U14 to be a 2.5V regulator any comparable regulator which can fit the SOT-223 layout can be used.
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The uncommitted regulator can be fed from either the PCIE3.3VCC rail (populate R175) or from the 5V supply provided by the ATX connector J4 (populate R174). The uncommitted USRVCC could also be used to provide an additional 1.5VCC as there is relatively little spare current available from U3. It should be noted that not all power rails are available for all the Vx bus resistor options associated with FP2 and it may be necessary to wire directly from the regulator to the appropriate PFx hole under some circumstances.
4.4.2.5 Uncommitted FPGA Pull-ups/downs Many of the pins associated with the uncommitted FPGA footprint can be pulled high or low. These pulls are set up using the appropriate resistor to link to a Vx bus and then selecting the voltage the pin should be pulled to using a second resistor. FPGA pins which are connected to LA or control pins of the PEX 8311 will not normally require additional pulls as these are already pulled to the correct value – see sheet 3 of the schematics.
4.4.2.6 Increasing the number of unused uncommitted FPGA I/O The vast majority of the I/O of the FPGA’s are used in connecting to the PEX 8311. The settings detailed in section 4.4.2.2 show the FPGA connected to the PEX 8311 in C mode using a 32 bit data bus. In addition every feature of the PEX 8311 is connected to the FPGA. For some applications more FPGA I/O will be required for user circuitry attached to the FPGA. There are several ways in which additional I/O can be released:
1) C mode of J mode When operating in C mode both the address and data buses have to be routed to the FPGA. If the board is re-configured to operate in J mode (see section 5) those signals which were previously allocated to the LA bus are no longer required and can be used as additional I/O.
2) Data bus width The data bus is currently configured to be a 32 bit bus. The LBRDx registers can be reconfigured to allow operation in 8 or 16 bit mode, thereby releasing the I/O which are connected to the unused data lines. It may be useful to only change LDRD1 to a different bus width. This will allow 32 bit accesses to the SBSRAM using local address space 0. It should be noted that if the FPGA is to access any of the PEX 8311 registers that access must be a 32 bit wide access so reducing the bus width is really only a solution for slave designs.
3) Bus Mastering or Slave only designs If the FPGA is only going to be used as a slave device then it may not be necessary to link all of the local bus control signals to the FPGA.
4) Address bus subset CS3# is routed to the FPGA and can be used as a chip select for the device. If only a small number of addresses are going to be decoded by the FPGA the upper portion of the LA bus can be left unconnected releasing FPGA I/O.
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5. RDK Mode Configuration
The RDK hardware’s Processor/Local Bus is pre-configured for non-multiplexed data and address (C Mode) Processor/Local Bus operation. It can be reconfigured for multiplexed data and address Processor/Local Bus operation (J Mode). Several resistors configure the RDK hardware’s Processor/Local Bus for C or J Mode. The specific resistors to install and remove for each mode are detailed in Table 5-1. (‘X’ means installed; no ‘X’ means removed.)
Table 5-1. RDK Board Mode Configuration
Resistors Value C Mode (Default) J Mode
Mode Pins Configuration
R32 1/10w, 10K ohm, 5% X R33 1/10w, 10K ohm, 5% R34 1/10w, 0 ohm, 5% X R35 1/10w, 0 ohm, 5% X X
Data/Address Pins Configuration
R74 1/10w, 0 ohm, 5% X R75 1/10w, 0 ohm, 5% X R76 1/10w, 0 ohm, 5% X R77 1/10w, 0 ohm, 5% X R84 1/10w, 0 ohm, 5% X R85 1/10w, 0 ohm, 5% X R87 1/10w, 0 ohm, 5% X R88 1/10w, 0 ohm, 5% X R93 1/10w, 0 ohm, 5% X R94 1/10w, 0 ohm, 5% X R95 1/10w, 0 ohm, 5% X R96 1/10w, 0 ohm, 5% X R97 1/10w, 0 ohm, 5% X
R100 1/10w, 0 ohm, 5% X R103 1/10w, 0 ohm, 5% X R106 1/10w, 0 ohm, 5% X R108 1/10w, 0 ohm, 5% X R109 1/10w, 0 ohm, 5% X R110 1/10w, 0 ohm, 5% X R111 1/10w, 0 ohm, 5% X R112 1/10w, 0 ohm, 5% X R113 1/10w, 0 ohm, 5% X
LA29/ALE
R50 1/10w, 10K, 5% X R51 1/10w, 4.7K ohm, 5% X
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6. Examples of Testing the OnBoard 32Kx32 SBSRAM with PLXMon
1) Single read/write from/to on board SBSRAM
a) At the lower command line window of PLXMon, type in the following commands to perform single 32bit, 16bit and 8bit memory read/write transfers from/to the on board SBSRAM. dl s0 1 <= read one 32-bit long word from address s0 el s0 88888888 <= write 32-bit data, 88888888h, to address s0 dw s0 1 <= read one 16-bit word from address s0 ew s0 8888 <= write 16-bit data, 8888h, to address s0 db s0 1 <= read a byte from address s0 eb s0 88 <= write 8-bit data, 88h, to address s0
2) DMA burst read/write from/to on board SBSRAM:
a) At the lower pane of the PLXMon, type Vars to obtain the addresses for HBuf, 60K-byte DMA scratch buffer located in the PC’s main memory. For example, assume the HBuf has physical address starting at 01F80000h.
b) Enter 8 long words of test data to the SBSRAM. For example, el s0 11111111 el s0+4 22222222 el s0+8 33333333 el s0+c 44444444 el s0+10 55555555 el s0+14 66666666 el s0+18 77777777 el s0+1c 88888888
c) Click the DMA button on PLXMon to open the DMA registers window.
d) Configure DMA CH0 for burst transfer and the transfer direction is from Local-to-PCI. The settings on DMA channel 0 would be similar to the following Mode (80h): 143 PCI address (84h): 01F80000 Local address (88h): 00000000 Transfer size (8ch): 100 Descriptor pointer (90h): 8 Check the box for data transfer enable
e) Click on the [Start Transfer] button to transfer data from on Board SBSRAM to DMA scratch
buffer.
f) Compare the data from step ‘b’ by typing the dl HBuf commend.
g) Change the contents of the DMA scratch buffer el HBuf 99999999 el HBuf+4 88888888 el HBuf+8 77777777 el HBuf+c 66666666 el HBuf+10 55555555 el HBuf+14 44444444 el HBuf +18 33333333 el HBuf+1c 22222222
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h) Change the direction of the DMA transfer to PCI-to-Local for DMA CH0, by modifying the Descriptor Pointer (90h) value from 8 to 0.
i) Click the [Start Transfer] button to perform a DMA transfer again
j) Type in dl s0 to compare the data from step G.
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7. CPLD Verilog Code
7.1 Verilog Code //============================================================== // // 8/8/2005 // // Synchronous SRAM controller for PLX PEX 8311 mode C and J. // 128K byte (32K x 32 bit) synchronous SRAM is used. // The memory map for the sync. SRAM is 0000_0000 - 0001_FFFFh. // A partial memory decode is used. The decode is only involved // address lines A31 to A28 (or A31-A29 and LD28 in J mode) // // //=============================================================== `timescale 1ns/100ps module sramctr82xx ( clk,adsn,blastn,lwdrdn,lhold,lbr,lben,adds_in,adds_4msb,
readyn,btermn,sramcsn,sramoen,lholda,lbg,sram_adds, sram_bwn,csn);
input clk,adsn,blastn,lwdrdn,lhold; input [1:0] lbr; input [3:0] lben; input [9:2] adds_in; input [31:28] adds_4msb; output readyn,btermn,sramcsn,sramoen,lholda; output [1:0] lbg; output [9:2] sram_adds; output [3:0] sram_bwn; output [3:0] csn; reg [9:2] sram_adds; reg [1:0] lbg; reg sramcsn,sramoen,lholda; tri readyn,btermn; // internal veriables reg [3:0] a31_28; reg [1:0] state; reg oer,oeb; BUFE tt1(.O(readyn),.E(!oer),.I(oer)); BUFE tt2(.O(btermn),.E(!oeb),.I(oeb)); // chip selects // Four uppermost address lines, A31-A28, are used to generate four // chip select signals for the board. They are CS[3:0] with addresses // // csn_0: 1000_0000h // csn_1: 2000_0000h // csn_2: 3000_0000h // csn_3: 4000_0000h wire [3:0] csn = (adds_4msb == 4'b0001) ? 4'b1110: (adds_4msb == 4'b0010) ? 4'b1101:
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(adds_4msb == 4'b0011) ? 4'b1011: (adds_4msb == 4'b0100) ? 4'b0111: 4'b1111; // byte enable encode for SRAM write cycles wire [3:0] sram_bwn =(lwdrdn,a31_28=='b1_0000) ? lben[3:0] : 4'b1111; // store the upper address LA31 - LA28 always @ (posedge clk) if (!adsn & (adds_4msb==4'b0000)) a31_28[3:0] <= adds_4msb[31:28]; // SRAM control state machine parameter s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; always @ (posedge clk) casex (state) s0: begin sramoen <=1; oeb <='b1; if (!adsn && !adds_4msb) begin sram_adds[9:2] <= adds_in[9:2]; sramcsn <= 0; if (lwdrdn) oer <= 'b0; else oer <= 'b1; state <= s1; end else begin oer <= 'b1; sramcsn <= 1; state <= s0; end end s1: if (lwdrdn && (!blastn)) begin sram_adds[9:2] <=sram_adds[9:2]+1; sramoen <=1; sramcsn <=1; oer <='b1; oeb <='b1; state <= s0; end else if (lwdrdn && blastn) begin if (sram_adds[9:2]== 'hfe)
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 37
begin oeb <='b0; sram_adds[9:2] <= sram_adds[9:2]+1; state <= s3; end else begin sram_adds[9:2] <= sram_adds[9:2]+1; sramoen <=1; sramcsn <=0; oer <='b0; oeb <='b1; state <=s1; end end else begin sram_adds[9:2] <=sram_adds[9:2]+1; sramoen <=0; sramcsn <=0; oer <='b0; oeb <='b1; state <= s2; end s2: if ((!lwdrdn) && (!blastn)) begin sramoen <=1; sramcsn <=1; oer <='b1; oeb <='b1; state <=s0; end else begin if (sram_adds[9:2]=='hff) begin oeb <='b0; sram_adds[9:2] <= sram_adds[9:2]+1; state <=s3; end else begin sram_adds[9:2] <= sram_adds[9:2]+1; sramoen <=0; sramcsn <=0; oer <='b0; oeb <='b1; state <=s2; end end s3: begin
PEX 8311RDK Hardware Reference Manual, Version 0.90 38 © 2005 PLX Technology, Inc. All rights reserved.
sramcsn <=1; oer <='b1; oeb <='b1; state <=s0; end default: state <=s0; endcase always @(posedge clk) begin if (lhold) lholda <= lhold; else lholda <= 0; if (!lhold && lbr[1]) lbg[1] <= lbr[1]; else lbg[1] <= 0; if (!lhold && !lbr[1] && lbr[0]) lbg[0] <= lbr[0]; else lbg[0] <= 0; end endmodule
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 39
8. References
The following is a list of documentation to provide further details.
PLX Technology, Inc. 870 Maude Ave. Sunnyvale, CA 94085 USA Tel: 408-774-9060 Tel: 800-759-3735 Fax: 408 774-2169 http://www.plxtech.com
PEX 8311 Data Book, Version xx or higher
PEX 8311RDK Hardware Reference Manual
PCI Special Interest Group (PCI-SIG) 5440 SW Westgate Drive #217 Portland, OR 97221 USA Tel: 503-291-2569 Fax: 503-297-1090 http://www.pcisig.com
PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a
PCI Express-to-PCI Bridge Specification 1.0
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 41
9. Bill of Materials / Schematics
The following pages contain the PEX 8311RDK bill of materials and schematics.
Table 9-1. PEX 8311RDK Bill Of Materials Item
# Qty Man Man's Part # Des Package Type Schematic Reference Subcon. Subcon.
Part # SURFACE MOUNT COMPONENTS
1 8 Panasonic ECJ1VB1H102K Cap, Ceramic, 0.001 uF, 10%, 50V, X7R 0603 C16, C18, C20, C26, C28, C30,
C32, C200 Taiyo-Yuden UMK107B102KZ-T
2 24 Kemet C0603C103M5UAC
Cap, Ceramic, 0.01 uF, 50 V, 20% 0603
C6, C10, C46, C48, C52, C54, C56, C58, C60, C62, C64, C66, C68, C70, C72, C74, C79, C83, C84, C85, C89, C90, C91, C155
3 47 Panasonic
ECJ1VB1E104K Cap, Ceramic, 0.1 uF, 10%, 16V, X7R
0603 C1, C2, C3, C8, C12, C14, C15, C17, C19, C22, C23, C24, C25, C27, C29, C31, C36, C37, C38, C39, C40, C41, C42, C44, C45, C47, C49, C50, C53, C55, C57, C59, C61, C63, C65, C67, C69, C71, C73, C75, C77, C80, C81,
C82, C86, C87, C88
4 2 Panasonic ECJ1VB1C105K, ECJ1VF105Z
Cap, Ceramic, 1.0 uF, 16 V 0603 C5, C11 Taiyo-Yuden EMK107BJ105M
A-B
5 10 Kemet T494B106K016AT
Cap, Tantalum, 10 uF, 16V CASE B C4, C7, C9, C21, C33, C34, C35,
C51, C76, C78 AVX TAJ B 106M016R
6 2 Kemet T491D474M016AT
Cap, Tantalum, 47uF,16V CASE D C13, C43 AVX TAJ C476M020R
7 6 Samtec TSM-110-01-T-DV
Header, 10 x 2 pins, 0.1", SMT SMT LAH1, LAH2, LAH3, LAH4,
LAH5, LAH6
8 1 AMP 6-104655-1 Header, 50 x 2
pins, .25mm, SMT, Shrouded
SMT J3
9 4 Chicago CMD17-21VRC/TR8 LED, SMT, Red 0805 LED1, LED2, LED3, LED4
10 3 Chicago CMD17-21VGC/TR8 LED, SMT, Green 0805 LED5, LED6, LED8
11 1 Steward L10805E400R Ferrite chip, 47 uH, 500mA 0805 L1
12 1 CTS Corp 742C083271JTR Resistor Array, x4,
270 Ohms, 5%, 0.1W
0603x4 RN1 NIC Compnents
NSRN06I4G271TRF
13 13 CTS Corp 742C083103JTR Resistor Array, x4,
10K Ohms, 5%, 0.1W
0603x4 RN2, RN3, RN4, RN5, RN6,
RN7, RN8, RN9, RN10, RN11, RN12, RN13, RN14
NIC Components
NSRN06I4J103TRF
14 30 Panasonic ERJ3GEY0R00V Resistor, 0 ohms (Jumper), 5%, 0.1 W 0603
R9, R10, R11, R12, R13, R34, R35, R53, R63, R66, R74, R76,
R84, R88, R94, R96, R100, R106, R109, R111, R113, R122, R123, R129, R130, R131, R132,
R133, R134, R135
NIC Components NRC06Z0
15 2 Panasonic ERJ6GEY0R00V Resistor, 0 ohms (Jumper), 5%. 1/8W 0805 R21, R23 NIC
Components NRC10Z0
16 1 Panasonic ERJ3RQF0r180V Resistor, 0.18 ohms, 1%, 0.1W 0603 R24 NIC
Components NRC06F0R18TR
F
17 5 Panasonic ERJ3GEYJ330V Resistor, 33 ohms , 5%, 0.1 W 0603 R54, R55, R56, R57, R58 NIC
Components NRC06J330TRF
18 5 Panasonic ERJ3GEYJ101V Resistor, 100 ohms , 5%, 0.1 W 0603 R28, R29, R30, R31, R127 NIC
Components NRC06J101TRF
19 2 Panasonic ERJ3GEYJ331V Resistor, 330 ohms, 5%, 0.1W 0603 R99, R125 NIC
Components NRC06J331TRF
20 22 Panasonic ERJ3GEYJ102V Resistor, 1K ohms , 5%, 0.1 W 0603
R5, R6, R8, R14, R15, R16, R17, R18, R19, R41, R65, R67, R68, R69, R72, R73, R78, R79, R80,
R81, R82, R639
NIC Components NRC06J102TRF
21 1 Panasonic ERJ3GEYJ122V Resistor, 1.2K ohms , 5%, 0.1 W 0603 R124 NIC
Components NRC06J122TRF
22 26 Panasonic ERJ3GEYJ103V Resistor, 10K ohms , 5%, 0.1 W 0603 R3, R4, R25, R26, R36, R37,
R38, R42, R43, R44, R45, NIC
Components NRC06J103TRF
PEX 8311RDK Hardware Reference Manual, Version 0.90 42 © 2005 PLX Technology, Inc. All rights reserved.
Item # Qty Man Man's Part # Des Package
Type Schematic Reference Subcon. Subcon. Part #
R47, R48, R50, R89, R90, R91, R92, R98, R101, R102,
R104, R105, R107, R638, R1147
23 1 Omron B3S1002 Switch, SPST, momentary, vertical SMT SW1
24 1 PLX
Technology, Inc.
PEX 8311 IC, PEX8311 BGA, 21x21 mm, 20x20 ball, 1.0mm
pitch U1
25 1 National Semiconductor LP2992IM5-1.5 IC, LDO Regulator,
1.5 V, 250 mA NS Package
Number MF05A
U3
26 1 National Semiconductor
LMS1585ACS-3.3
IC, LDO Regulator, 3.3V, 3A U4
27 1 Semtech LT1963AEXT-25 IC, LDO regulator, 2.5V, 1A SOT-223 U9
28 1 Maxim MAX6306UK30D1-T
IC, Reset Controller, MAX6306UK30D1-T SOT-23, 5 pin U5
29 1 Cypress Semiconductor CY2305SC-1 IC, Clock Buffer,
CY2305 SOIC, 8-pin U7
30 1 Xilinx XC9572XL-5TQ100C
IC, CPLD Programmable Logic
XC9572XL-5TQ100C
TQFP, 100 pins (square) U10
31 1 Samsung K7B403625B IC, Synchronous SRAM, 4 Mbit, 128Kx36, Flow-
Through
TQFP, 100 pins, 14x20
mm U11
THROUGH-HOLE COMPONENTS
32 4 Molex 22-28-4020 Header, 2 x 1
pins, 0.1", vert., no shroud
Thru-Hole JP1, J7, J8, J9 AMP
33 4 Molex 22-28-4030 Header, 3 x 1
pins, 0.1", vert., no shroud
Thru-Hole JP2, JP3, JP4, JP5 AMP
34 1 Molex 22-28-4060 Header, 6 x 1
pins, 0.1", vert., no shroud
Thru-Hole J1
35 1 Molex 22-28-4090 Header, 9 x 1
pins, 0.1", vert., no shroud
Thru-Hole J2
36 1 Molex 53109-0410
5.08mm (.200") Pitch Disk Drive
Power ConnectionSystem Header, Right Angle, with Strap Standard Polarization, 4
Circuits
Thru-Hole J4
37 3 Mil-Max 110-93-308-41-001 Socket, 8-pin dip, 0.3", solder tail,
low-profile Thru-Hole U2, U6, U8
COMPONENTS THAT ARE HAND-ASSEMBLED
38 1 CTS Corp MXO45HS-3C-66M6666
OSC, 66.666 MHz clock oscillator,
3.3V, 50ppm, 40-60% duty cycle
Half-size DIP, 8-pin U8 Ecliptek EP1345HSPD-
66.666M
39 1 Atmel AT25640A-10PI-2.7 IC, Serial
EEPROM, SPI, 64K, AT25640
DIP, 8-pin U2
40 1 Atmel AT93C56A-10PU-2.7 IC, Serial
EEPROM, 3-wire, AT93C56/66A
DIP, 8-pin U6
41 1 Keystone 9203 PCI Bracket, Blank BRACKET1
PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved. 43
Item # Qty Man Man's Part # Des Package
Type Schematic Reference Subcon. Subcon. Part #
42 2 Spaenaur 492-100 Phillips, 4-40,
1/4", PH screw (for PCB bracket)
SCREW1, SCREW2
43 6 Jumper shunts, for 0.1" hdr. J7, J8, J9, JP3(1-2),
JP4(1-2), JP5(1-2)
MISCELLANEOUS COMPONENTS
44 1 PEX 8311RDK
PCB, p/n 90-0058-000-A
45 1 Velostat 2100R/8X10 8" x 10" anti-static bag BAG1 FAI
PARTS THAT ARE NOT POPULATED (DO NOT KIT)
46 1 Molex 10-88-1105 Header, 5 x 2 pins, 0.1", vert., no shroud Thru-Hole JP6
47 1 Comm Con 2422-14G2 Header, 7 x 2 pins,
0.1", vert, keyed shrd.
JP7 OUPIIN 3112-14GSB
48 1 Semtech EZ117-2.5 IC, LDO regulator, 2.5V, 1A SOT-223 U14
49 2 Panasonic ERJ6GEY0R00V Resistor, 0 ohms (Jumper), 5%. 1/8W 0805 R22, R27 NIC
Components NRC10Z0
50 3 Kemet T494B106K016AS
Cap, Tantalum, 10 uF, 16V CASE B C96, C98, C100 AVX TAJ B 106M016R
51 1 ICS Tech
(www.icst.com)
ICS557G03 IC, PCI-Express Clock Source,
ICS557-03 TSSOP-16
pins U12
52 1 CTS Corp CB3LV-3C-25M0000 XTAL, 25 MHz, SMD SMT,
3.2x2.5mm Y1
53 1 CTS Corp MXO45HS-3C-66M6666
OSC, 66.666 MHz clock oscillator,
3.3V, 50ppm, 40-60% duty cycle
Half-size DIP, 8-pin U13 Ecliptek EP1345HSPD-
66.666M
54 1 Mil-Max 110-93-308-41-001
Socket, 8-pin dip, 0.3", solder tail, low-
profile Thru-Hole U13
55 1 Panasonic ERJ3GEYJ100V Resistor, 10 ohms , 5%, 0.1 W 0603 R136 NIC
Components NRC06J100TRF
56 4 Panasonic ERJ3GEYJ330V Resistor, 33 ohms , 5%, 0.1 W 0603 R137, R141, R145, R148 NIC
Components NRC06J330TRF
57 4 Panasonic ERJ3EKF49R9V Resistor, 49.9 ohms, 1%, 0.1W 0603 R138, R142, R143, R147 NIC
Components NRC10F49R9TR
F
58 1 Panasonic ERJ3EKF4750V Resistor, 475 Ohms, 1%, 0.1W 0603 R149 NIC
Components NRC10F4750TRF
59 8 Panasonic ERJ3GEYJ103V Resistor, 10K ohms , 5%, 0.1 W 0603 R32, R33, R139, R140, R144,
R146, R147,R641 NIC
Components NRC06J103TRF
60 2 Panasonic ECJ1VC1H100D Cap, Ceramic, 10 pF, 50V, +/- 0.5 pF 0603 C94, C95
61 2 Kemet C0603C103M5UAC
Cap, Ceramic, 0.01 uF, 50 V, 20% 0603 C92, C93
62 1 Panasonic ECJ1VB1E104K Cap, Ceramic, 0.1 uF, 10%, 16V, X7R 0603 C97
63 18 Panasonic ERJ3GEY0R00V Resistor, 0 ohms (Jumper), 5%, 0.1 W 0603
R59, R60, R61, R62, R64, R83, R86, R75, R77, R85, R87, R93, R95, R97, R103, R108, R110,
R112
NIC Components NRC06Z0
64 3 Panasonic ERJ3GEYJ472V Resistor, 4.7K ohms , 5%, 0.1 W 0603 R39, R49, R51 NIC
Components NRC06J103TRF
NOTE: NOT POPULATED NO VALUE COMPONENTS FROM SHEETS 8 TO 12 OF THE SCHEMATICS ARE NOT LISTED. SEE SECTION 4.4.2 FOR COMPONENT VALUES NOTE: OTHER NOT POPULATED COMPONENTS ARE NOT LISTED AT THIS TIME
Customer Name: PLX PLX Part #: 91-0058-000-A Product Name: PEX 8311RDK
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Title
Size Document Number Rev
Date: Sheet of
000
PEX8311RDK-Lite
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
1 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PEX8311RDK-Lite
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
1 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PEX8311RDK-Lite
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
1 15Wednesday, December 14, 2005
www.plxtech.com
On-Board Prototyping Area- 144-pin PLCC Footprint for Altera or Xilinx FPGA- SMD device footprints- Power Regulator circuit (un-populated) - Thru-hole grid, 20x10, 0.1" spacing
Daughter Board Conn.use AMP p/n 6-104652-0
Custom Daughter CardMounting Area
Test Headers
JTAG
Catalyst Mid-Bus LAI Footprint
LCLKOsc.
PCI ExpressClock Gen.(not populated)
LCLK Dist.
ATX HDDPwr. ConnMolex 53109-0410
Power Regulators
JTAG
PEX 8311
+12 V+3.3 V
+12 V+5.0 V
© 2005 PLX Technology, Inc. All rights reserved.PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
+3.3 V+2.5 V+1.8 V
Table Of Contents Block Diagram Revision History
Date Summary of Changes01: Cover Page02: PEX8311 PCI Express Bus03: PLX8311 Local Bus04: CPLD and SBSRAM05: Test Headers
PCIE Clock Gen
06: PLX Option Module Connector07: Catalyst Midbus and
08: FPGA Footprint09: FPGA Side A Option Resistors10: FPGA Side B Option Resistors11: FPGA Side C Option Resistors12: FPGA Side D Option Resistors
15: NC Balls
13: Pads14: Prototype Footprint
PCI Express X1Card-Edge Connector
AT25640ASPI EEPROM (PCIE Config.)
Xilinx XC9572XL CPLD - SBSRAM controller - Chip Selects - Local Bus Arbiter
32bit, 66.666Mhz PLX Local Bus
Samsung K7B403625BSynchronous Burst SRAM(Flow-Through Outputs)512 Kbytes
93CS56/66u-Wire EEPROM(Local Bus Config.)
Daughter Board Header AMP p/n 6-104655-1
On-board Reset Gen.
12-08--05 Release 1.0
91-0058-000-A
This schematic includes minor board errata's which are not implemented in the PCB layout. See PEX8311RDK Errata Rev. 1.0, Dec. 2005 for details.
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
PRSNT
PETp0CPETn0C PERp0
PETn0
PERn0
GPIO0
GPIO2
EERDDATA
L1.5R
ROOT_COMPLEX#PWR_OK
TCKBAR0ENB#
GPIO1
LED3
LED4
LED2
LED1
PERST#
PERST_8311#
PERST_8311#
EECS#EECLK
GPIO3
TMSTMS
TDO
RE
FC
LK-
EEWRDATA
TDI
PETp0
PERST#
RE
FC
LK+
WAKEIN#
WAKEOUT#
BAR0ENB#
ITDO
ITDO
PERp0
PERn0
PETp0
PETn0
PLXT1
PLXT1
GPIO1 5,9,10
GPIO2 5,10,11
GPIO3 5,9,11
GPIO0 5,9,10
PCIE3.3VCCPCIE3.3VCC PCIE12VCC 8311_PLL1.5VCC
1.5VCC
1.5VCC8311_PLL1.5VCC
PCIE3.3VCC
PCIE12VCC
PCIE3.3VCC
PCIE3.3VCCPCIE3.3VCC
PCIE12VCC
PCIE3.3VCC
3.3VCC
3.3VCC 8311_3.3V
8311_3.3V
1.5VCC 8311_1.5V
8311_1.5V
8311_1.5V
8311_3.3V
PCIE3.3VCC
8311_3.3V
PCIE3.3VCC
PCIE3.3VCC
PCIE3.3VCC
PCIE3.3VCC
+12V
PCIE3.3VCC
8311_1.5V
WAKEIN#5
BAR0ENB# 5
REFCLK+7
REFCLK-7
PERp0 7
PERn0 7
PETp0 7
PETn0 7
Title
Size Document Number Rev
Date: Sheet of
000
PEX8311 PCI Express bus
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
2 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PEX8311 PCI Express bus
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
2 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PEX8311 PCI Express bus
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
2 15Wednesday, December 14, 2005
www.plxtech.com
JTAG Port
PLL Filter
PLACE CLOSE TO THE CHIP
250mA Max.
1.8A max.
Place one cap. toeach edge connector's3.3V pin.
Place close to theedge connector
User Accessible Reset Circuit
91-0058-000-A
R15
1K
R15
1K
R70_NP
R70_NP
LED2
LED
LED2
LED
12
C37
0.1uF
C37
0.1uF
R28 100R28 100
LED4
LED
LED4
LED
R18
1K
R18
1K
C10
0.01uF
C10
0.01uF
12
C200
0.001uF
C200
0.001uF
R27
0_NP
R27
0_NP
12
C25
0.1uF
C25
0.1uF
VIN3
GN
D1
VOUT 2
U4LMS1585ACS-3.3U4LMS1585ACS-3.3
12
C41
0.1uF
C41
0.1uF
SCK6CS#1
SI5
WP#3SO 2
HOLD# 7
GND 4
VCC 8U2 AT25640U2 AT25640
R638 10kR638 10k
1 2
J8J8
12
C39
0.1uF
C39
0.1uF
12
R25
10K
R25
10K
1 2
J7J7
R9 0R9 0
+12VB1
+12VB2
RSVDB3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3.3VB8
JTAG1B9
3.3VauxB10
WAKE#B11
RSVDB12
GNDB13
PETp0B14
PETn0B15
GNDB16
PRSNT2#B17
GNDB18
PRSNT1# A1
+12V A2
+12V A3
GND A4
JTAG2 A5
JTAG3 A6
JTAG4 A7
JTAG5 A8
+3.3V A9
+3.3V A10
PERST# A11
GND A12
REFCLK+ A13
REFCLK- A14
GND A15
PERp0 A16
PERn0 A17
GND A18
P1
PCI Express x1 Edge
P1
PCI Express x1 Edge
12
C15
0.1uF
C15
0.1uF1
23
JP3JP3
C3410uFC3410uF
WAKEIN#B2
ROOT_COMPLEX#A18
PLXT2A10 EERDDATA M3
TESTN1
BUNRIF3
BTOND10
SMC V4
TMC E2
TMC1 V3
TMC2 E3
TDI A14
TCK A13
TMS A11
TRST# B14
WAKEOUT#D1
PWR_OKD2
EEWRDATA L3
EECS# K3
EECLK L4
GPIO0 C1
GPIO1 B1
GPIO2 D3
GPIO3 A1
TDO C14
BAR0ENB# E1
REFCLK+H1
REFCLK-H2
PERp0G1
PERn0F2
PERST#C3
PETp0J1
PETn0K2
VS
SA
2
VS
SB
15
VS
SW
3
VS
SW
4
VS
SP
5
VS
SN
5
VS
SM
5
VS
SL5
VS
SK
5
VS
SJ5
VS
SH
5
VS
SG
5
VS
SM
4
VS
SK
4
AV
SS
J3
VS
S_C
F4
VS
S_P
0H
4
VS
S_P
1G
4
VS
S_R
F1
VS
S_R
EG
2
VS
S_T
K1
VD
D3.
3E
16
VD
D3.
3E
17
VD
D3.
3F
16
VD
D3.
3F
17
VD
D3.
3D
8
VD
D3.
3D
9
VD
D3.
3E
9
VD
D3.
3E
15
VD
D3.
3F
15
VD
D3.
3G
15
VD
D1.
5C
9
VD
D1.
5C
13
VD
D1.
5D
6
VD
D1.
5L1
VD
D1.
5L2
VD
D1.
5M
1
VD
D1.
5W
5
AV
DD
G3
VD
D_P
J2
VD
D_R
H3
VD
D_T
J4
VD
D1.
5C
2
VDD3.3D7
VDD3.3E5
VDD3.3F5
VS
SF
11
VS
SF
10
VS
SF
9
VS
SF
8
VS
SF
7
ITDO C15
PLXT1A3
PEX8311
U1A
PEX8311
U1A
123456
J1J1
12
C32
0.001uF
C32
0.001uF
12
C24
0.1uF
C24
0.1uF
12
C23
0.1uF
C23
0.1uF
R5 1KR5 1K
R20 0_NPR20 0_NP
1 2
C2
0.1uF
C2
0.1uF
R30 100R30 100R29 100R29 100
12
C16
0.001uF
C16
0.001uF
1 2
C30.1uFC30.1uF
12
+C13
47uF
+C13
47uF
R14
1K
R14
1K
SW1
SW PUSHBUTTON
SW1
SW PUSHBUTTON
1 2
R24
1.4 (include L1 DC resistance)
R24
1.4 (include L1 DC resistance)
12
R310KR310K
R10 0R10 0
+C7
10uF
+C7
10uF
R17
1K
R17
1K
R23
0
R23
0
12
C51uFC51uF
12
C30
0.001uF
C30
0.001uF
R19
1K
R19
1K
12
C36
0.1uF
C36
0.1uF
R1
0_NP
R1
0_NP
C910uF ceramic
C910uF ceramic
C3510uFC3510uF
12
C14
0.1uF
C14
0.1uF
12
C42
0.1uF
C42
0.1uF
12
C29
0.1uF
C29
0.1uF
12
3
JP4JP4
12
C40
0.1uF
C40
0.1uF
LED1
LED
LED1
LED
12
C26
0.001uF
C26
0.001uF
1 2L1
47uH (>30mA)
L1
47uH (>30mA)
12
3
JP2JP2
12
C28
0.001uF
C28
0.001uF
12
C6
0.01uF
C6
0.01uF
R6391kR6391k
12
C20
0.001uF
C20
0.001uF
R11 0R11 0
12
C12
0.1uF
C12
0.1uF
12
C17
0.1uF
C17
0.1uF
12
C1
0.1uF
C1
0.1uF
R31 100R31 100
TP1TP1R8 1KR8 1K
C8
0.1uF
C8
0.1uF
12
JP1JP1
LED3
LED
LED3
LED
12
C22
0.1uF
C22
0.1uF
R12 0R12 0
VIN1 VOUT 5
GND2 BYPASS 4
ON/OFF3
U3
LP2992
U3
LP2992
12
C18
0.001uF
C18
0.001uF
12
C31
0.1uF
C31
0.1uF
C1550.01uFC1550.01uF
12
R26
10K
R26
10K
12
+ C2110uF
+ C2110uF
R13 0R13 0
12
3
JP5JP5
12
R410KR410K
VCC 5MR#3
RESET# 1
GND 2RST_IN4
U5
MAX6306UK30D1-T
U5
MAX6306UK30D1-T
R16
1K
R16
1K
R6 1KR6 1K
12
C38
0.1uF
C38
0.1uF
R22 0_NPR22 0_NP
C3310uF C3310uF
12
C19
0.1uF
C19
0.1uF
12345 6 7 8
RN1274RN1274
12
+C43
47uF
+C43
47uF
12
C27
0.1uF
C27
0.1uF
C410uF CeramicC410uF Ceramic
R20_NPR20_NP
12
C11
1uF
C11
1uF
R210
R210
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
LD18
LD18
LD4
LD4
LD31
LD31
LD26
LD26
LD17
LD17
LD19
LD19
LD8
LD8
LD24
LD24
LD7
LD7
LD10
LD10
LD13
LD13
LD27
LD27
LD12
LD12
LD9
LD9
LD28
LD28
LA28
LA11
LA2
LA14
LA30
LA24
LA15
LA18
LA13LA12
LA8
LA25
LA19
LA10
LA4
LA20
LA7
LA29
LA6
LA22LA23
LA21
LA17
LA5
LA16
LA3
LA9
LA31
LA27LA26
LBE#2LBE#3
LBE#1LBE#0
LA14LA15LA16LA17
LA21LA20LA19LA18
LA31
LA27LA30
LA26
DP0DP1DP2DP3
LRESET#
LSERR#
DREQ1#
BIGEND#
LW/R#
DMPAF/EOT#
DACK0#
ADS#
BREQo
WAIT#
LINTo#
BREQi
LINTi#
BTERM#
READY#
USERo/LLOCKo#USERi/LLOCKi#DREQ0#
DACK1#
BLAST#
LHOLDALHOLD
LCLK1
CCS#
MODE0MODE1
EESK
EECSBD_SEL#IDDQEN#
LA3LA4
LA2
LA5
LA6LA7LA8LA9
LA10LA11LA12LA13
LA25LA24LA23LA22
ADS#BLAST#READY#WAIT#
BREQoBREQi
LHOLDALHOLDALHOLDLHOLD
BIGEND#BIGEND#BIGEND#BIGEND#BIGEND#BIGEND#BIGEND#BIGEND#BIGEND#BIGEND#
BTERM#
LBE#1LBE#0
LBE#3LBE#2
DREQ1#
LW/R#
CCS#LINTo#
LINTi#LSERR#
BREQiBREQi
DMPAF/EOT#
USERi/LLOCKi#USERo/LLOCKo#
LRESET#
DREQ0#
DACK1#DACK0#
BD_SEL#
PEPRE
EECSEESK
MODE1
MODE0
LA28LA29
LCLK1
LHOLD LHOLDA
READY#
LD5
LD5
LD23
LD23
LD16
LD16
LD6
LD6
LD11
LD11
LD22
LD22
LD20
LD20
LD15
LD15
LD30
LD30
LD3
LD3
LD21
LD21
LD14
LD14
LD25
LD25
LD29
LD29
LD2
LD2
LD0
LD0
LD1
LD1
EEDI/EEDO
PMEIN#
CLKOUT
EEDI/EEDO
PMEOUT#
3.3VCC
3.3VCC 3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
PCIE3.3VCC 2.5VCC
3.3VCC
8311_3.3V
2.5VCC 8311_2.5V
8311_2.5V
8311_2.5V8311_3.3V
3.3VCC
LA[31:2] 4,5,6,9,10,11,12
DP[3:0] 5,11
LD[31:0] 4,5,6,9,10,11,12
LBE#[3:0] 4,5,6,12
LRESET# 5,6,12
LHOLDA 4,5
ADS# 4,5,6,11BLAST# 4,5,6,11READY# 4,5,6,12WAIT# 5,6,12LW/R# 4,5,6,12
DMPAF/EOT# 4,5,6,11
DREQ0# 4,5,6,11DREQ1# 4,5,6,12DACK0# 4,5,6,10DACK1# 4,5,6,11
SRAM_CLK 4
CLK_66MHZ 4LCLK_T 5,9,12POM_CLK 6
LINTi# 5,6,12LSERR# 5,10BREQi 5,6,9,11BREQo 5,6,9,11
BIGEND# 5,11USERo/LLOCKo# 5,6,9USERi/LLOCKi# 5,6,9,10
PMEIN# 5,11,12PMEOUT# 5
BTERM# 4,5,6,11
CCS# 11
LHOLD 4,5
LINTo# 5,6,9
CLKIN7
Title
Size Document Number Rev
Date: Sheet of
000
PEX-8311 Local bus
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
3 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PEX-8311 Local bus
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
3 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PEX-8311 Local bus
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
3 15Wednesday, December 14, 2005
www.plxtech.com
Clock Circuit
Serial EEPROM
MODE MODE0 MODE1C 0 0J 1 0 Reserved 0 1Reserved 1 1
R32 and R33 should notbe installed by default.
1A max.
Optional for debug
R51 should not be installed bydefault. For J Mode, R51 has to beinstalled and R50 remove.
91-0058-000-A
1234 5
678
RN3
742-08-3-103-J-XX
RN3
742-08-3-103-J-XX
R49 4.7K_NPR49 4.7K_NP
C66
0.01uF
C66
0.01uF
C74
0.01uF
C74
0.01uF
C50
0.1uF
C50
0.1uF
C57
0.1uF
C57
0.1uF
C64
0.01uF
C64
0.01uF
C71
0.1uF
C71
0.1uF
C47
0.1uF
C47
0.1uF
1234 5
678
RN4
742-08-3-103-J-XX
RN4
742-08-3-103-J-XX
TP2TP2
R55 33R55 33
R3210K_NP
R3210K_NP
NC 1GND4
OUT 5VCC8U8
osc_halfsize (Socket)
U8
osc_halfsize (Socket)
C77
0.1uF
C77
0.1uF
R57 33R57 33
R35 0R35 0
C53
0.1uF
C53
0.1uF
1234 5
678
RN13
742-08-3-103-J-XX
RN13
742-08-3-103-J-XX
C48
0.01uF
C48
0.01uF
R44 10KR44 10K
C62
0.01uF
C62
0.01uF
1234 5
678
RN2
742-08-3-103-J-XX
RN2
742-08-3-103-J-XX
C45
0.1uF
C45
0.1uF
R34 0R34 0
R41 1KR41 1K
C59
0.1uF
C59
0.1uF
R45 10KR45 10K
R3310K_NP
R3310K_NP
1234 5
678
RN6
742-08-3-103-J-XX
RN6
742-08-3-103-J-XX
1234 5
678
RN12
742-08-3-103-J-XX
RN12
742-08-3-103-J-XX
C54
0.01uF
C54
0.01uF
C68
0.01uF
C68
0.01uF
R54 33R54 33
C46
0.01uF
C46
0.01uF
R38 10KR38 10K
R530
R530
C55
0.1uF
C55
0.1uF
+C78
10uF
+C78
10uF
R46 0_NPR46 0_NP
1234 5
678
RN7
742-08-3-103-J-XX
RN7
742-08-3-103-J-XX
1234 5
678
RN14
742-08-3-103-J-XX
RN14
742-08-3-103-J-XX
R48 10KR48 10K
R39
4.7K_NP
R39
4.7K_NP
C61
0.1uF
C61
0.1uF
C72
0.01uF
C72
0.01uF
R56 33R56 33
C52
0.01uF
C52
0.01uF
1 2
J9J9
C56
0.01uF
C56
0.01uF
R37 10KR37 10K
C60
0.01uF
C60
0.01uF
C44
0.1uF
C44
0.1uF
R514.7K_NP
R514.7K_NP
1234 5
678
RN5
742-08-3-103-J-XX
RN5
742-08-3-103-J-XX
1234 5
678
RN10
742-08-3-103-J-XX
RN10
742-08-3-103-J-XX
C63
0.1uF
C63
0.1uF
1234 5
678
RN9
742-08-3-103-J-XX
RN9
742-08-3-103-J-XX
R58 33R58 33
C58
0.01uF
C58
0.01uF
REF1 CLK2 2CLK1 3
GN
D4
CLK3 5
VC
C6
CLK4 7
CLKOUT 8
U7
CY2305
U7
CY2305
C75
0.1uF
C75
0.1uF
R36
10K
R36
10K
R47 10KR47 10K
C65
0.1uF
C65
0.1uF+
C76
10uF
+C76
10uF
C79
0.01uF
C79
0.01uF
C49
0.1uF
C49
0.1uF
C70
0.01uF
C70
0.01uF
+C51
10uF
+C51
10uF
R42 10KR42 10K
LA2Y18
LA3W18
LA4V18
LA5Y17
LA6W17
LA7V17
LA8U17
LA9Y16
LA10W16
LA11V16
LA12U16
LA13Y15
LA14W15
LA15V15
LA16Y14
LA17W14
LA18Y13
LA19W13
LA20Y12
LA21W12
LA22Y11
LA23W11
LA24V11
LA25Y10
LA26W10
LA27Y9
LA28W9
LA29Y8
LA30W8
LA31Y7
DP0L16
DP1L15
DP2M16
DP3M15
LD0
K20
LD1
K19
LD2
K18
LD3
K17
LD4
L20
LD5
L19
LD6
L18
LD7
L17
LD8
M20
LD9
M19
LD10
M18
LD11
M17
LD12
N20
LD13
N19
LD14
N18
LD15
N17
LD16
P20
LD17
P19
LD18
P18
LD19
P17
LD20
R20
LD21
R19
LD22
R18
LD23
R17
LD24
T20
LD25
T19
LD26
T18
LD27
T17
LD28
U20
LD29
U19
LD30
V20
LD31
V19
BREQo G17BREQi G18
ADS# F19
LHOLD G20
LHOLDA G19
LW/R# U18
BLAST# F20
BTERM# J19
READY# F18
WAIT# H17
BIGEND# D18
LSERR# J18
DMPAF/EOT# C18
DREQ0# C19
DREQ1# B17
DACK0# C20
DACK1# B18
LRESET# E18
CCS# D17
LCLK J20
LINTo# E19
LINTi# E20
USERo/LLOCKo# D19
USERi/LLOCKi# D20
EECS A20EEDI/EEDO B20
EESK A19
MODE0 H19
MODE1 H20
BD_SEL# B19
IDDQEN# V10
VSS N6
VSS P6
VSS R6
VSS R7
VSS R8
VSS R9
VSS R10
VSS R11
VSS R12
VSS R13
VSS V1
VSS W1
VSS Y1
VSS W2
VSS Y2
VSS Y3
VSS Y4
VSS R5
VSS U5
VSS T5
VSS U6
VS
SA
17
VS
SA
16
VS
SB
16
VS
SD
15
VS
SD
14
VS
SD
13
VS
SD
12
VS
SE
14
VS
SE
13
VS
SE
12
VS
SE
11
VS
SE
10
VS
SE
8
VS
SE
7
VS
SF
14
VS
SH
15
VS
SJ1
5
VS
SK
15
VS
SN
15
VS
SP
15
VS
SR
15
VS
ST
14
VS
ST
13
VS
SU
13
VS
SV
13
VS
SU
12
VS
SV
12
VS
ST
11
VS
ST
10
VS
ST
9
VS
ST
8
VS
SU
8
VS
ST
7
VS
ST
6
VDD3.3N16
VDD3.3P16
VDD3.3R16
VDD3.3T15
VDD3.3U14
VDD3.3V14
VDD3.3T12
VDD3.3U11
VDD3.3U10
VDD3.3G16
VDD3.3H16
VDD3.3J16
VDD3.3K16
VDD2.5C17
VDD2.5H18
VDD2.5J17
VDD2.5T16
VDD2.5U15
VDD2.5V9
LBE0#W19
LBE1#W20
LBE2#Y20
LBE3#Y19
VSS F6
VSS G7
VSS G6
VSS H6
VSS J6
VSS K6
VSS L6
VSS M6
VSS F12VSS F13
VDD2.5Y5
CLKOUTA8
CLKINA15
PMEIN# C16
PMEOUT# B10
VSS R14
VS
SU
9
U1C
PEX8311
U1C
PEX8311
C69
0.1uF
C69
0.1uF
C67
0.1uF
C67
0.1uF
R1147 10KR1147 10K
CS1
SK2
DI3
DO4
VCC 8
PRE 7
PE 6
GND 5
U6
93CS56L or 66L(8DIP-Socket)
U6
93CS56L or 66L(8DIP-Socket)
R43 10KR43 10K
R50 10KR50 10K
1234 5
678
RN8
742-08-3-103-J-XX
RN8
742-08-3-103-J-XX
C73
0.1uF
C73
0.1uF
1234 5
678
RN11
742-08-3-103-J-XX
RN11
742-08-3-103-J-XX
VIN1
GN
D2
VOUT 3
U9LT1963AEXT-25U9LT1963AEXT-25
R52 0_NPR52 0_NP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
LD0LD1LD2LD3LD4LD5LD6LD7
LD8LD9LD10LD11LD12LD13LD14LD15
LD16LD17LD18LD19LD20LD21LD22LD23
LD24LD25LD26LD27LD28LD29LD30LD31
READY#
BTERM#
SRAM_CLKSRAMCS_SRAMOE_SRAM_BW_0SRAM_BW_1SRAM_BW_2SRAM_BW_3
MA2MA3MA4MA5MA6MA7MA8MA9
DREQ0#
DACK0#
DMPAF/EOT#
LD[31:0]
CPLD_TDO
LA[31:2]
CLK_66MHZADS#BLAST#LW/R#
READY#BTERM#LHOLDLHOLDALRESET#
LD2
LD5
LD4
LD3
LD8
LD7
LD6
LD9
AA3
AA4
AA8
AA9
CPLD_TMS
AA31
DREQ1#
DACK1#
AA29
LD31
LD30
LD29
SRAMCS_
SRAM_BW_0SRAMOE_
SRAM_BW_1SRAM_BW_2SRAM_BW_3LA6
AA28
AA30
CS_0#
LA29
AA7
AA31
SRAMCS_
CS_2#
LA3
LA10
MA4
LBG1
ADS#
LA12
LHOLDA
SRAM_BW_3
MA9
LBE#3
AA8
AA4
SRAM_BW_2
MA7
CS_1#
AA2
LA2
LBE#2
LA14
LA31
AA2
LBE#2
LA30
LA11
LBE#3
BLAST#
LHOLD
SRAM_BW_1
SRAM_BW_0
LBE#1MA2
AA6
AA29
LA13
LA7
LA28 AA28
CLK_66MHZ
READYN
BTERMN
LBR0LA16
MA8
CS_3#
LA8
LA9
CPLD_TCK
AA5
MA5
LA4
CPLD_TDI
LBE#0
LBE#1
LW/R#
LA5
LA15
AA7
AA9
LBE#0
LBG0
SRAMOE_
AA30MA3
AA6
AA5
AA3MA6LBR1
LBR0
SA15SA15
SA15SA16
LBR0LBG0LBR1LBG1
CS_3#
SA16
CS_0#
3.3VCC3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
SRAM_CLK3
DREQ0#3,5,6,11
DMPAF/EOT#3,5,6,11
DACK0#3,5,6,10
LA[31:2] 3,5,6,9,10,11,12
LD[31:0] 3,5,6,9,10,11,12
ADS#3,5,6,11BLAST#3,5,6,11LW/R#3,5,6,12
LRESET#3,5,6,12
LHOLD3,5
CLK_66MHZ3
DREQ1#3,5,6,12
DACK1#3,5,6,11
READY#3,5,6,12BTERM#3,5,6,11
LD[31:0] 3,5,6,9,10,11,12
LA[31:2]3,5,6,9,10,11,12
LHOLDA3,5
LBE#[3:0]3,5,6,12
LBR1 12
LBR0 6LBG0 6
LBG1 9
CS_3#10
CS_0# 6
Title
Size Document Number Rev
Date: Sheet of
000
SRAM & CPLD
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
4 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
SRAM & CPLD
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
4 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
SRAM & CPLD
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
4 15Wednesday, December 14, 2005
www.plxtech.com
100-pin TQFP
CPLD
R83 and R86 should notbe installed by default
or XC95144XL-5TQ100C
Synchronous SRAM and Controller Circuit
R59-R62, and R64 shouldnot be installed by default
For C mode (default), install R74,R76,R84,R88 ,R94,R96,R100,R106,R109,R111 and R113,remove R75, R77 and R85,R87,R93,R95,R97,R103,R108,R110,and R112 For J mode, it is vice versa.
128Kx36
91-0058-000-A
PA4PA4
PA60PA60
PA44PA44
R93 0R93 0
R66 0R66 0
PA54PA54
R86
0
R86
0
R91
10K
R91
10K
PA63PA63
R94 0R94 0
R68
1K
R68
1K
PA52PA52
PA62PA62
PA25PA25
PA22PA22
C83
0.01uF
C83
0.01uF
R113 0R113 0
R84 0R84 0
PA65PA65
R65
1K
R65
1K
PA47PA47
R111 0R111 0
R109 0R109 0
PA48PA48
PA19PA19PA18PA18
R791KR791K
PA34PA34
PA32PA32
R102 10KR102 10K
R731KR731K
PA14PA14
PA27PA27
R721KR721K
PA13PA13
C86
0.1uF
C86
0.1uF
PA56PA56
PA12PA12
PA31PA31
C87
0.1uF
C87
0.1uF
R108 0R108 0
C89
0.01uF
C89
0.01uF
PA50PA50
PA6PA6
PA17PA17
PA39PA39
R74 0R74 0
R92
10K
R92
10K
SA037
SA136
DQa0 52
DQa1 53
DQa2 56
DQa3 57
DQa4 58
DQa5 59
DQa6 62
DQa7 63
NC
1
NC
30
VS
S17
VS
S40
VS
S67
VS
S90
VS
S5
VS
S10
VS
S21
VS
S26
VS
S55
VS
S60
VS
S71
VS
S76
VD
D15
VD
D41
VD
D65
VD
D91
VD
DQ
4
VD
DQ
11
VD
DQ
20
VD
DQ
27
VD
DQ
54
VD
DQ
61
VD
DQ
70
VD
DQ
77
NC
14N
C16
NC
38
NC
39
NC
42
NC
43
NC
66
DQd0 18
DQd1 19
DQd2 22
DQd3 23
DQd4 24
DQd5 25
DQd6 28
DQd7 29
DQc0 2
DQc1 3
DQc2 6
DQc3 7
DQc4 8
DQc5 9
DQc6 12
DQc7 13
DQb0 68
DQb1 69
DQb2 72
DQb3 73
DQb4 74
DQb5 75
DQb6 78
DQb7 79
SA532SA433SA334SA235
SA1044
SA1145
SA1246
SA1347
SA1448
SA981SA882SA799SA6100
GW#88
CE297
MODE31
ADV#83
ADSP#84
BWE#87
CE2#92
ZZ64
CLK89
CE#98
OE#86
BWa#93
BWb#94
BWc#95
BWd#96
NC
51
NC
80
ADSC#85
SA1549
SA1650SYNC_SRAM
U11
K7B403625B
SYNC_SRAM
U11
K7B403625B
PA36PA36
R89
10K
R89
10K
PA68PA68
PA35PA35
PA7PA7
R76 0R76 0
PA26PA26
R112 0R112 0
PA57PA57
PA69PA69
R88 0R88 0
R70 0_NPR70 0_NP
PA46PA46
R781KR781K
PA9PA9
R62 0R62 0
R60 0R60 0
C91
0.01uF
C91
0.01uF
PA38PA38
R95 0R95 0
PA51PA51
R104 10KR104 10K
PA40PA40
IOA116
IOA213
IOA318
IOA420
IOA514
IOA615
IOA725
IOA817
IOA928
IOA1133
IOA1236
IOA1329
IOA1439
IOA1530
IOA1640
IOB187
IOB294
IOB391
IOB493
IOB595
IOB696
IOB897
IOB101
IOB116
IOB128
IO/GCK122
IOB1411
IOB1510
IOB1612
IOB1792
IO/GTS24
VC
C5
VC
C57
VC
C98
VC
C26
GN
D21
GN
D31
GN
D44
GN
D69
GN
D62
GN
D75
GN
D84
GN
D10
0
NC
2
NC
7
NC
19
NC
24IOD16 86
TCK 48
TDI 45
TDO 83
TMS 47
IOD13 85
IOD14 78
IOD15 89
IOD3 71
IOD4 72
IOD5 68
IOD6 76
IOD7 77
IOD8 70
IOD9 66
IOD10 81
IOD11 74
IOD12 82
IOC11 52
IOC12 61
IOC13 63
IOC14 55
IOC15 56
IOC16 64
IOC17 58
IOC18 59
IOD1 65
IOD2 67
IOC1 41
IOC2 32
IOC3 49
IOC4 50
IOC5 35
IOC6 53
IOC7 54
IOC8 37
IOC9 42
IOC10 60IOA10/GCK223
IO/GCK327
NC
34
NC
43
NC
46
NC
73
NC
80
VC
C38
VC
C51
VC
C88
IOD17 90
IOD18 79
IOB7/GTS13
IOB9/GSR99
IOB139
U10
XC9572XL-5TQ100C
U10
XC9572XL-5TQ100C
R105 10KR105 10K
PA37PA37
R75 0R75 0
R98 10KR98 10K
PA55PA55
C85
0.01uF
C85
0.01uF
R77 0R77 0
PA71PA71
C84
0.01uF
C84
0.01uF
PA29PA29
PA41PA41
C81
0.1uF
C81
0.1uF
R106 0R106 0
PA66PA66
C82
0.1uF
C82
0.1uF
R87 0R87 0
R801KR801K
PA11PA11
PA58PA58
R83 0R83 0
R59 0R59 0
PA5PA5
PA2PA2
PA30PA30
R100 0R100 0
PA61PA61
C80
0.1uF
C80
0.1uF
R90
10K
R90
10K
R110 0R110 0
PA3PA3
R71 0_NPR71 0_NP
PA23PA23
PA16PA16
R67
1K
R67
1K
PA67PA67
PA42PA42
R97 0R97 0
PA21PA21
R107 10KR107 10K
R63 0R63 0
PA45PA45
PA15PA15
C88
0.1uF
C88
0.1uF
PA64PA64
R69
1K
R69
1K
R85 0R85 0
PA59PA59
PA8PA8
R821KR821K
R99 330R99 330
R103 0R103 0
PA20PA20
PA49PA49
PA28PA28
R811KR811K
PA33PA33
PA24PA24
R61 0R61 0
123456789
J2
1x9 HDR, 0.1"oc
J2
1x9 HDR, 0.1"oc
PA70PA70
PA1PA1
R101 10KR101 10K
PA53PA53
R96 0R96 0
PA10PA10
R64 0R64 0
C90
0.01uF
C90
0.01uF
PA43PA43
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LBE#0LBE#1LBE#2LBE#3
LA3
LA29
LA10
LA13
LA8LA9
LA11
LA25LA26
LA2
LA24
LA30
LA6LA7
LA19
LA5
LA12
LA21
LA27LA28
LA31
LA4
LA23
LA15
LA17LA18
LA22
LA20
LA14
LA16
LBE#0LBE#2LA2LA4LA6LA8LA10LA12
LA13LA11
LA9LA7LA5LA3
LBE#3LBE#1
LA25
LA21
LA16
LA29
LA19
LA28
LA23LA26
LA15
LA20
LA24
LA18
LA27
LA22
LA14
LA17
LD5
LD1
DP0
LD9
DP3
LD8
LD3LD6
LA31
LD0
LD4
DP2
LD7
LD2
LA30
DP1
DP0DP1DP2DP3
LD24LD22LD20LD18LD16LD14LD12LD10
LD11LD13LD15LD17LD19LD21LD23LD25
LD31
LD27
BTERM#
LD28
BLAST#
LD29LD30
LHOLDALHOLDADS#
LW/R# WAIT#
LD26
READY#
DREQ0#DACK0#
LD23
LD20
LD3
LD29
LD24
LD26
LD30
LD13
LD27
LD0
LD17
LD14
LD31
LD21
LD18
LD28
LD15
LD1
LD25
LD22
LD12
LD2
LD19
LD16
LD9
LD4
LD6
LD10
LD7
LD11
LD8
LD5USERi/LLOCKi#USERo/LLOCKo#
DREQ1#DACK1# GPIO0
PMEIN#PMEOUT#WAKEIN#
GPIO2GPIO1
GPIO3
BAR0ENB#
BREQiBREQo
BIGENDE#
DMPAF/EOT#
LINTo#LINTi#
LSERR#LRESET#
3.3VCC2.5VCC
PCIE12VCC
PCIE3.3VCC
LA[31:2]3,4,6,9,10,11,12
LBE#[3:0]3,4,6,12
LD[31:0]3,4,6,9,10,11,12
DP[3:0]3,11
LCLK_T3,9,12
LW/R#3,4,6,12READY#3,4,6,12
ADS#3,4,6,11LHOLD3,4
BTERM# 3,4,6,11WAIT# 3,6,12BLAST# 3,4,6,11LHOLDA 3,4
GPIO0 2,9,10GPIO1 2,9,10
DACK0#3,4,6,10DREQ0#3,4,6,11
GPIO2 2,10,11GPIO3 2,9,11
DACK1#3,4,6,11DREQ1#3,4,6,12
WAKEIN# 2BAR0ENB# 2
USERi/LLOCKi#3,6,9,10USERo/LLOCKo#3,6,9
PMEIN# 3,11,12PMEOUT# 3BREQi3,6,9,11
BREQo3,6,9,11BIGEND# 3,11
DMPAF/EOT#3,4,6,11
LINTi#3,6,12LINTo#3,6,9 LSERR# 3,10
LRESET# 3,6,12
Title
Size Document Number Rev
Date: Sheet of
000
Test Headers
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
5 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
Test Headers
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
5 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
Test Headers
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
5 15Wednesday, December 14, 2005
www.plxtech.com
91-0058-000-A
1
C
TP3
C
TP3
R120
0_NP
R120
0_NP
1
C
TP11
C
TP11
R121
0_NP
R121
0_NP
1
C
TP9
C
TP9
R1140_NP
R1140_NP
R1150_NP
R1150_NP
R127100R127100
+5V1
D163
D145
D127
D109
D811
D613
D415
D217
D019
D17 2
D15 4
D13 6
D11 8
D9 10
D7 12
D5 14
D3 16
D1 18
GND 20
LAH1
Logic Analyzer Header
LAH1
Logic Analyzer Header
1
C
TP5
C
TP5
R1220 R1220
+5V1
D163
D145
D127
D109
D811
D613
D415
D217
D019
D17 2
D15 4
D13 6
D11 8
D9 10
D7 12
D5 14
D3 16
D1 18
GND 20
LAH5
Logic Analyzer Header
LAH5
Logic Analyzer Header
R1241.2KR1241.2K
1
C
TP4
C
TP4
1
C
TP10
C
TP10
+5V1
D163
D145
D127
D109
D811
D613
D415
D217
D019
D17 2
D15 4
D13 6
D11 8
D9 10
D7 12
D5 14
D3 16
D1 18
GND 20
LAH6
Logic Analyzer Header
LAH6
Logic Analyzer Header
R1160_NP
R1160_NP
+5V1
D163
D145
D127
D109
D811
D613
D415
D217
D019
D17 2
D15 4
D13 6
D11 8
D9 10
D7 12
D5 14
D3 16
D1 18
GND 20
LAH4
Logic Analyzer Header
LAH4
Logic Analyzer Header
R1170_NP
R1170_NP
1
C
TP7
C
TP7
+5V1
D163
D145
D127
D109
D811
D613
D415
D217
D019
D17 2
D15 4
D13 6
D11 8
D9 10
D7 12
D5 14
D3 16
D1 18
GND 20
LAH3
Logic Analyzer Header
LAH3
Logic Analyzer Header
LED8
LED
LED8
LED
LED6
LED
LED6
LED
+5V1
D163
D145
D127
D109
D811
D613
D415
D217
D019
D17 2
D15 4
D13 6
D11 8
D9 10
D7 12
D5 14
D3 16
D1 18
GND 20
LAH2
Logic Analyzer Header
LAH2
Logic Analyzer Header
LED5
LED
LED5
LED
R118
0_NP
R118
0_NP
1
C
TP6
C
TP6
R125330R125330
1
C
TP8
C
TP8
R119
0_NP
R119
0_NP
R1230 R1230
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
LD7LAD7LD6LAD6LD5LAD5
DMAEOT0#
LD4LAD4LD3LAD3LD2LAD2LD1LAD1LD0LAD0
LBE#0LBE#1LBE#2
WAIT#
LD31 LAD31LD30 LAD30LD29 LAD29LD28 LAD28LD27 LAD27LD26 LAD26LD25 LAD25LD24 LAD24
DACK0#DREQ0#
LRESET#
LA29ALE
LD23 LAD23LD22 LAD22LD21 LAD21LD20 LAD20LD19 LAD19
ADS#
POM_CLK
BLAST#
LW/R#
LD18 LAD18LD17 LAD17LD16 LAD16
DREQ1#DACK1#
DEN# LA30DT/R# LA31
DMAEOT1#USER0USER1
USERo/LLOCKo#
LD15 LAD15LD14 LAD14LD13 LAD13LD12 LAD12LD11 LAD11LD10 LAD10LD9 LAD9LD8 LAD8
BREQiBREQo
USERi/LLOCKi#
READY#
READY#
POM_CS#
POM_CS#
LBE#3
5VCC 5VCC3.3VCC
+12V
+12V
5VCCDMPAF/EOT# 3,4,5,11
WAIT#3,5,12
BTERM# 3,4,5,11
DACK0# 3,4,5,10DREQ0# 3,4,5,11
LA[31:2] 3,4,5,9,10,11,12
LD[31:0]3,4,5,9,10,11,12
LINTi#3,5,12
DREQ1# 3,4,5,12DACK1# 3,4,5,11
BREQi 3,5,9,11BREQo 3,5,9,11
CS_0# 4
USERo/LLOCKo#3,5,9
ADS#3,4,5,11
LW/R#3,4,5,12
BLAST#3,4,5,11
READY#3,4,5,12
LBG04
LINTo#3,5,9
LBR04
LRESET#3,5,12
USERi/LLOCKi#3,5,9,10
POM_CLK3
READY# 3,4,5,12
LBE#03,4,5,12LBE#13,4,5,12LBE#23,4,5,12LBE#33,4,5,12
Title
Size Document Number Rev
Date: Sheet of
000
PLX Option Module Connector
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
6 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PLX Option Module Connector
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
6 15Wednesday, December 14, 2005
www.plxtech.comTitle
Size Document Number Rev
Date: Sheet of
000
PLX Option Module Connector
PLX TECHNOLOGY, INC.870 Maude Ave, Sunnyvale, CA 94085
Custom
6 15Wednesday, December 14, 2005
www.plxtech.com
R128 should not be installed by default
PLX Option Module Connector
2X50 Connector
91-0058-000-A
PB1PB1
1234
J4
Molex 53109-0410
J4
Molex 53109-0410
PB6PB6
PB4PB4
PB8PB8
PB5PB5
R134 0R134 0
R132 0R132 0
PB3PB3
DMAREQ0# 51
DMAACK0# 52
DMAEOT0# 53
DMAREQ1# 54
DMAACK1# 55
DMAEOT1# 56
USER0 57
USER1 58
5 VCC 59
3.3 VCC 60
3.3 VCC 61
ASYNC_SEL# 62
PPC_ALE_H 63
LABS2 64
LABS3 65
3.3 VCC 66
POM_SERR# 67
5 VCC 68
DEN# 69
DT/R# 70
3.3 VCC 71
RD_STRB# 72
RESERVED 73
RESERVED 74
POM_RDY_OUT# 75
3.3 VCC 76
3.3 VCC 77
POM_PRESENT# 78
BREQ_IN 79
BREQ_OUT 80
BTERM_IN# 81
BTERM_OUT# 82
5 VCC 83
AD07 84
AD06 85
AD05 86
AD04 87
AD03 88
AD02 89
AD01 90
AD00 91
GND 92
5 VCC 93
3.3 VCC 94
3.3 VCC 95
GND 96
EESDA 97
EESCL 98
+12V 99
-12V 100
ADS#1
GND2
PCLK3
GND4
BLAST#5
LOCK#6
W/R#7
GND8
POM_RDY_IN#9
RESET#10
BE0#11
BE1#12
BE2#13
BE3#14
SYNC_SEL#15
GND16
IRQ_OUT#17
IRQ_IN#18
POM_REQ19
POM_GNT20
POM_WAIT#21
GND22
5 VCC23
AD3124
AD3025
AD2926
AD2827
AD2728
AD2629
AD2530
AD2431
GND32
AD2333
AD2234
AD2135
AD2036
AD1937
AD1838
AD1739
AD1640
GND41
AD1542
AD1443
AD1344
AD1245
AD1146
AD1047
AD0948
AD0849
GND50
J3
PLX Option Module 1 (POM1)
J3
PLX Option Module 1 (POM1)
R130 0R130 0
R133 0R133 0
PB7PB7
R135 0R135 0
PB2PB2
R129 0R129 0
PB10PB10
R128 0_NPR128 0_NP
R131 0R131 0
PB9PB9
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
CLK0pCLK0n
CLK1pCLK1n
REFCLK+REFCLK-
REFCLK2-REFCLK2+
XINXOUT
CLK66 CLKIN
PETp0PETn0 PERp0
PERn0
3.3VCC3.3VCC
PCIE3.3VCC
REFCLK+ 2REFCLK- 2
PERp0 2PERn0 2
PETp02PETn02
CLKIN 3
Title
Size Document Number Rev
Date: Sheet of
000
PCI Express Midbus & Clock
B
7 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
000
PCI Express Midbus & Clock
B
7 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
000
PCI Express Midbus & Clock
B
7 15Wednesday, December 14, 2005
PLACE R137,R138,R141,R142,R143,R145,R147,R148CLOSE TO U12Internal pull-up resistor
in OE, S0/1, SS0/1
R139,R140,R144,R146NOT INSTALL
Clock Circuit The components on this sheet are notinstalled by default.
91-0058-000-A
TX0+1
TX0-3 RX0+ 4
RX0- 6
GND 2
GND 8
RX1+ 10
RX1- 12
GND 14
RX2+ 16
RX2- 18
GND 20
RX3+ 22
RX3- 24
GND 26
RX4+ 28
RX4- 30
GND 32
RX5+ 34
RX5- 36
GND 38
RX6+ 40
RX6- 42
GND 44
RX7+ 46
RX7- 48
GND5
TX1+7
TX1-9
GND11
TX2+13
TX2-15
GND17
TX3+19
TX3-21
GND23
TX4+25
TX4-27
GND29
TX5+31
TX5-33
GND35
TX6+37
TX6-39
GND41
TX7+43
TX7-45
GND47
J5
Midbus LAI
J5
Midbus LAI
TP12TP12
12
C95
10pF_NP
C95
10pF_NP
12
Y1
25 MHz_NP
Y1
25 MHz_NP
12R145 33_NPR145 33_NP
12R140 10K_NPR140 10K_NP
S01
S12
SS03
SS18
X1/ICLK4
X25
OE6
IREF 9
GN
D7
GN
D13
CLK0p 15
CLK0n 14
CLK1p 11
CLK1n 10
VD
DO
DA
12
VD
DX
D16 U12
ICS557-03 (Socket)
U12
ICS557-03 (Socket)
12R146 10K_NPR146 10K_NP
12
R13849.9_NP
R13849.9_NP
12
C93
0.01uF_NP
C93
0.01uF_NP
12
R14249.9_NP
R14249.9_NP
12
C970.1uF_NPC970.1uF_NP
12R148 33_NPR148 33_NP
C9610uF_NPC9610uF_NP
R64110K_NP
R64110K_NP
12 R13610_NP
R13610_NP
12R141 33_NPR141 33_NP
12R137 33_NPR137 33_NP
12R139
10KR139
10K
12R144 10K_NPR144 10K_NP
12
C92
0.01uF_NP
C92
0.01uF_NP
12
R149475 +/-1%_NPR149475 +/-1%_NP
12
C94
10pF_NP
C94
10pF_NP
R150 0_NPR150 0_NP
12
R14349.9_NPR14349.9_NP
NC 1GND4
OUT 5VCC8U13
osc_halfsize (socket)
U13
osc_halfsize (socket)
12
R14749.9_NP
R14749.9_NP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1B
3B
2B
1
B5
B4
B8
B7
B6
USRVCC
B10
B9
B12
B11
B14
B13
B16
B15
B19
B18
B17
B22
B21
B20
B24
B23
B26
B25
B29
B28
B27
B32
B31
B30
B34
B33
B36
B35
F_TDO
D36
D1
B27
F_TDI
B35
D34
D35
D36
D32
D33
D29
D30
D31
D23
D25
D28
D20
D22
D17
D19
D13
D14
D16
D8
D10
D11
D5
D7
D1
D2
D4
D9
D6
D3
D15
D12
D24
D21
D18
D26
D27
A3A2A1
A5A4
A8A7A6
A11A10A9
A13A12
A16A15A14
A19A18A17
A21A20
A24A23A22
A27A26A25
A29A28
A32A31A30
A35A34A33
USRVCC
A36
A1
F_TMS
F_TCK
B4
C36
2.5VCC
C33C34C35
C31C32
C28C29C30
C22C23
C25
C19C20
C14
C16C17
C10C11
C13
C7C8
C2
C4C5C6
C3
C1
C12
C9
C21
C18
C15
C26C27
C24
B36
2.5VCC
C36
D2
D36
D1
PCIE3.3VCC
PCIE3.3VCC
PCIE3.3VCC
F_TDI
F_TDO
F_TDI
F_TMS
F_TCK
F_TMS
F_TCKF_TDO
PCIE3.3VCC5VCC
PCIE3.3VCC2.5VCC
PCIE3.3VCC
2.5VCC
USRVCC
A[36:1]9,13
B[36:1]10,13
C[36:1] 11,13
D[36:1] 12,13
F_TDO 11
F_TDI 11
F_TMS 11
F_TCK 11
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Footprint
B
8 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Footprint
B
8 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Footprint
B
8 15Wednesday, December 14, 2005
Side B bus
Note this is designed for the XilinxXCF01S or XCF02S device in theirV020 package.
Side C bus
Side D bus
Side A bus
USRVCC
The components on this sheet are notinstalled by default.
91-0058-000-A
PA72PA72
R63
70_
NP
R63
70_
NP
2468
101214
135791113
JP7JP7
R1750_NPR1750_NP
R63
40_
NP
R63
40_
NP
R170 100_NPR170 100_NP246810
13579
JP6JP6
PA77PA77
R165 0_NPR165 0_NP
R63
30_
NP
R63
30_
NP
11
22
33
44
55
66
77
88
99
1010 11 1112 1213 1314 1415 1516 1617 1718 1819 1920 20
FP1
20-pin SSOP, 0.025" pitch
FP1
20-pin SSOP, 0.025" pitch
PA74PA74
R167 0_NPR167 0_NP
PA78PA78
R163 0_NPR163 0_NP
R156 0_NPR156 0_NP
C101
0.01uF_NP
C101
0.01uF_NP
C99
0.1uF_NP
C99
0.1uF_NP
PA75PA75
R151 0_NPR151 0_NP
R154 0_NPR154 0_NP
+C100
10uF_NP
+C100
10uF_NP
PA76PA76
R63
10_
NP
R63
10_
NP
R157 0_NPR157 0_NP
R6300_NP
R6300_NP
R173 100_NPR173 100_NP
R155 0_NPR155 0_NP
R161 0_NPR161 0_NP11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
6161
6262
6363
6464
6565
6666
6767
6868
6969
7070
7171
7272
73 7374 7475 7576 7677 7778 7879 7980 8081 8182 8283 8384 8485 8586 8687 8788 8889 8990 9091 9192 9293 9394 9495 9596 9697 9798 9899 99
100 100101 101102 102103 103104 104105 105106 106107 107108 108
109
109
110
110
111
111
112
112
113
113
114
114
115
115
116
116
117
117
118
118
119
119
120
120
121
121
122
122
123
123
124
124
125
125
126
126
127
127
128
128
129
129
130
130
131
131
132
132
133
133
134
134
135
135
136
136
137
137
138
138
139
139
140
140
141
141
142
142
143
143
144
144 FP2
144 Pin QFP Footprint
FP2
144 Pin QFP Footprint
R164 0_NPR164 0_NP
R160 0_NPR160 0_NP
R63
60_
NP
R63
60_
NP
R166 0_NPR166 0_NP
R171 0_NPR171 0_NP
R162 0_NPR162 0_NP
R159 56_NPR159 56_NP
R152 0_NPR152 0_NP
R169 0_NPR169 0_NP
R63
20_
NP
R63
20_
NP
1
CTP20
CTP20
R1740_NPR1740_NP
R63
50_
NP
R63
50_
NP
R172 100_NPR172 100_NP
R158 0_NPR158 0_NP
+C98
10uF_NP
+C98
10uF_NP
PA73PA73
VIN3
GN
D1
VOUT 2
U14EZ117-2.5U14EZ117-2.5
R168 0_NPR168 0_NP
R153 0_NPR153 0_NP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
A12
A27
A17
PCIE3.3VCC
2.5VCC
1.5VCC
USRVCC
A8
A11
A12
A25
A26
A28
A29
A30
A31
A32
A33
A34
A35
A36
VA10
A21
A22
A23
A19
A20
A24
A9
A11
A13
A15
VA7
VA6
VA5
VA4
A8VA1
A9
A11
A13
A15
A18
USRVCC
A27
A28
A29
A30
A21
A22
A23
PCIE3.3VCC
2.5VCC
A27
A28
A29
VA12
A21
A22
A23
A19
VA11
A30
VA3
PCIE3.3VCC
2.5VCC
VA8
VA9
VA12
VA11
VA10
VA1
A9
A10
A13
A14
A16
A17
A18
A3
A4
A1
A5
A2
A6
A7
VA2
VA3
VA4
VA2
A15
VA4
VA5
PCIE3.3VCC
2.5VCC
VA6
PCIE3.3VCC
2.5VCC VA10
PCIE3.3VCC
USRVCC VA8
PCIE3.3VCC
2.5VCC VA7VA7
USRVCC
PCIE3.3VCC
2.5VCC
PCIE3.3VCC
2.5VCC
1.5VCC
VA12
PCIE3.3VCC
VA9
2.5VCC VA11
A12
1.5VCC
PCIE3.3VCC
2.5VCC
USRVCC
1.5VCC
PCIE3.3VCC
2.5VCC
USRVCC
LA23,4,5LA43,4,5
LA203,5
LA73,4,5,10
LA53,4,5
LA83,4,5,10
GPIO02,5,10
LD103,4,5,6
LD113,4,5,6LCLK_T3,5,12
LD03,4,5,6
GPIO32,5,11
LD23,4,5,6
LD33,4,5,6
BREQo3,5,6,11
LD43,4,5,6
LD73,4,5,6
LA213,5,12
LD53,4,5,6
LA43,4,5
LBG14
LD83,4,5,6
LA53,4,5
A[36:1]8,13
LD63,4,5,6
USERo/LLOCKo#3,5,6
LINTo#3,5,6
LA23,4,5
GPIO12,5,10
LD13,4,5,6
USERi/LLOCKi#3,5,6,10
LA63,4,5,10
LD93,4,5,6
A98,13
A198,13
A308,13
A188,13
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side A resistor options
B
9 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side A resistor options
B
9 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side A resistor options
B
9 15Wednesday, December 14, 2005
Side A bus
The components on this sheet are notinstalled by default.
91-0058-000-A
R243 0_NPR243 0_NP
R256 0_NPR256 0_NP
C105
10nF_NP
C105
10nF_NP
R202 0_NPR202 0_NP
R185 0_NPR185 0_NP
R239 0_NPR239 0_NP
R219 0_NPR219 0_NP
C109
10nF_NP
C109
10nF_NPR262 0_NPR262 0_NP
C107
10nF_NP
C107
10nF_NP
R259 0_NPR259 0_NP
R266 0_NPR266 0_NP
C112
10nF_NP
C112
10nF_NP
R180 56_NPR180 56_NP
R233 0_NPR233 0_NP
R187 0_NPR187 0_NP
R272 0_NPR272 0_NP
R246 0_NPR246 0_NP
R217 0_NPR217 0_NP
C106
10nF_NP
C106
10nF_NP
R201 0_NPR201 0_NP
C111
10nF_NP
C111
10nF_NP
R176 0_NPR176 0_NP
R181 0_NPR181 0_NP
R240 0_NPR240 0_NP
R234 0_NPR234 0_NP
C108
10nF_NP
C108
10nF_NP
R209 0_NPR209 0_NP
R191 0_NPR191 0_NP
R221 0_NPR221 0_NP
R208 0_NPR208 0_NP
R232 0_NPR232 0_NP
R196 0_NPR196 0_NP
R214 0_NPR214 0_NP
R269 0_NPR269 0_NP
R245 0_NPR245 0_NP
R258 0_NPR258 0_NP
R204 0_NPR204 0_NPR207 0_NPR207 0_NP
R195 0_NPR195 0_NP
C102
10nF_NP
C102
10nF_NP
R218 0_NPR218 0_NP
C103
10nF_NP
C103
10nF_NP
R244 0_NPR244 0_NP
R271 0_NPR271 0_NP
R227 0_NPR227 0_NP
R215 0_NPR215 0_NP
R188 0_NPR188 0_NP
R206 0_NPR206 0_NP
R247 0_NPR247 0_NP
R268 0_NPR268 0_NP
R261 0_NPR261 0_NP
R189 0_NPR189 0_NP
R252 0_NPR252 0_NP
R177 0_NPR177 0_NP
R255 0_NPR255 0_NP
R260 0_NPR260 0_NPC110
10nF_NP
C110
10nF_NP
R251 0_NPR251 0_NP
R225 0_NPR225 0_NP
R192 0_NPR192 0_NP
R226 0_NPR226 0_NP
C113
10nF_NP
C113
10nF_NP
R211 0_NPR211 0_NP
R254 0_NPR254 0_NP
R235 0_NPR235 0_NP
R228 0_NPR228 0_NP
R198 0_NPR198 0_NP
R249 0_NPR249 0_NP
R270 0_NPR270 0_NP
R253 0_NPR253 0_NP
R242 0_NPR242 0_NPR241 0_NPR241 0_NP
C104
10nF_NP
C104
10nF_NP
R264 0_NPR264 0_NP
R199 0_NPR199 0_NP
R178 0_NPR178 0_NP
R231 0_NPR231 0_NPR230 0_NPR230 0_NP
R182 0_NPR182 0_NP
R236 0_NPR236 0_NP
R186 0_NPR186 0_NP
R223 0_NPR223 0_NP
R205 0_NPR205 0_NP
R237 0_NPR237 0_NP
R179 0_NPR179 0_NP
R216 0_NPR216 0_NPR220 0_NPR220 0_NP
R190 0_NPR190 0_NP
R229 0_NPR229 0_NP
R267 0_NPR267 0_NP
R263 0_NPR263 0_NP
R210 0_NPR210 0_NP
R184 0_NPR184 0_NP
R213 0_NPR213 0_NP
R224 0_NPR224 0_NP
R197 0_NPR197 0_NP
R183 0_NPR183 0_NP
R238 0_NPR238 0_NP
R222 0_NPR222 0_NP
R193 0_NPR193 0_NP
R265 0_NPR265 0_NP
R212 0_NPR212 0_NP
R250 0_NPR250 0_NP
R200 0_NPR200 0_NP
R194 0_NPR194 0_NP
R257 0_NPR257 0_NP
R203 0_NPR203 0_NP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
B1
B4
PCIE3.3VCC
2.5VCC VB13
PCIE3.3VCC
2.5VCC VB15
PCIE3.3VCC
2.5VCC
1.5VCC
VB14
PCIE3.3VCC
2.5VCC VB1
VB11
VB11
VB12
VB15
VB14
VB13
VB12
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B3
B4
B1
B5
B2
B6
B7
VB2
VB3
VB13
PCIE3.3VCC
2.5VCC VB2
VB14
VB1
1.5VCC
VB15
USRVCC
VB3
VB2
VB10
PCIE3.3VCC
2.5VCC VB4VB4
PCIE3.3VCC
VB5VB5
PCIE3.3VCC
2.5VCC VB6VB6PCIE3.3VCC
2.5VCC VB8
PCIE3.3VCC
2.5VCC
1.5VCC
VB7
PCIE3.3VCC
2.5VCC VB9 VB10VB7
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B21
B22
B23
B19
B20
B24
B8
B9
B10
B6
B7
VB9
VB8
VB7
VB6
PCIE3.3VCC
2.5VCC VB11
B8
B9
VB8
B10
B13VB4
B1
B6
B7B25
B26
B27
B28
B29
B30
B21
B24
B25
B26
B27
B28
B29
B30
B36
B21
B19VB5
B24
VB9
2.5VCC
1.5VCC
USRVCC
VB12
B4
VB1
1.5VCC
USRVCC
PCIE3.3VCC
2.5VCC
USRVCC
PCIE3.3VCC
2.5VCC
USRVCC
1.5VCCLA63,4,5,9
LA93,4,5
LA73,4,5,9LD243,4,5,6
LD193,4,5,6
B[36:1]8,13
LA103,4,5
DACK0#3,4,5,6
LD253,4,5,6
GPIO12,5,9
LA183,5
LA163,4,5
LA173,5
LD153,4,5,6
LD163,4,5,6
LD173,4,5,6
LD123,4,5,6
LD283,4,5,6
LA193,5LSERR#3,5
GPIO02,5,9
LD263,4,5,6
LA103,4,5
LD273,4,5,6
GPIO22,5,11
CS_3#4
LD223,4,5,6
LD233,4,5,6
LD183,4,5,6
LA83,4,5,9
LA93,4,5
LA113,4,5,11
USERi/LLOCKi#3,5,6,9
B98,13
B108,13B288,13
B298,13
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side B resistor options
B
10 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side B resistor options
B
10 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side B resistor options
B
10 15Wednesday, December 14, 2005
Side B bus
The components on this sheet are notinstalled by default.
91-0058-000-A
C127
10nF_NP
C127
10nF_NP
R289 0_NPR289 0_NP
R341 0_NPR341 0_NP
R336 0_NPR336 0_NP
R380 0_NPR380 0_NP
R321 0_NPR321 0_NP
R338 0_NPR338 0_NP
R291 0_NPR291 0_NP
R278 0_NPR278 0_NP
R363 0_NPR363 0_NP
R305 0_NPR305 0_NP
R276 0_NPR276 0_NP
R295 0_NPR295 0_NP
C126
10nF_NP
C126
10nF_NP
R286 0_NPR286 0_NP
R330 0_NPR330 0_NP
R357 0_NPR357 0_NP
R343 0_NPR343 0_NP
R375 0_NPR375 0_NP
R273 0_NPR273 0_NP
R292 0_NPR292 0_NP
R376 0_NPR376 0_NP
R365 0_NPR365 0_NP
R296 0_NPR296 0_NP
R315 0_NPR315 0_NP
R350 0_NPR350 0_NP
C122
10nF_NP
C122
10nF_NP
R349 0_NPR349 0_NP
R294 0_NPR294 0_NP
R379 0_NPR379 0_NP
R306 0_NPR306 0_NP
R337 0_NPR337 0_NP
R361 0_NPR361 0_NP
R322 0_NPR322 0_NP
R277 0_NPR277 0_NP
R303 0_NPR303 0_NPR300 0_NPR300 0_NP
C117
10nF_NP
C117
10nF_NP
R319 0_NPR319 0_NPR318 0_NPR318 0_NP
R342 0_NPR342 0_NP
R327 0_NPR327 0_NP
R335 0_NPR335 0_NP
R362 0_NPR362 0_NP
R310 0_NPR310 0_NPR314 0_NPR314 0_NP
R369 0_NPR369 0_NP
R358 0_NPR358 0_NP
R274 0_NPR274 0_NP
R324 0_NPR324 0_NP
R299 0_NPR299 0_NP
R661 0_NPR661 0_NP
C118
10nF_NP
C118
10nF_NP
R283 0_NPR283 0_NP
C125
10nF_NP
C125
10nF_NPR374 0_NPR374 0_NP
R331 0_NPR331 0_NP
R316 0_NPR316 0_NP
R333 0_NPR333 0_NP
R367 0_NPR367 0_NP
R281 0_NPR281 0_NP
R347 0_NPR347 0_NP
R352 0_NPR352 0_NP
R288 0_NPR288 0_NP
R370 0_NPR370 0_NP
R293 0_NPR293 0_NP
R344 0_NPR344 0_NP
R325 0_NPR325 0_NP
R340 0_NPR340 0_NP
R371 0_NPR371 0_NP
R287 0_NPR287 0_NPR285 0_NPR285 0_NP
R348 0_NPR348 0_NP
R284 0_NPR284 0_NP
R308 0_NPR308 0_NP
C115
10nF_NP
C115
10nF_NP
C124
10nF_NP
C124
10nF_NP
R346 0_NPR346 0_NP
R312 0_NPR312 0_NP
C123
10nF_NP
C123
10nF_NP
R297 0_NPR297 0_NP
R377 0_NPR377 0_NP
R290 0_NPR290 0_NP
R360 0_NPR360 0_NP
R302 0_NPR302 0_NP
R334 0_NPR334 0_NP
R359 0_NPR359 0_NP
R355 0_NPR355 0_NP
R373 0_NPR373 0_NP
R351 0_NPR351 0_NP
C116
10nF_NP
C116
10nF_NP
R368 0_NPR368 0_NP
R313 0_NPR313 0_NP
R304 0_NPR304 0_NP
R339 0_NPR339 0_NP
R364 0_NPR364 0_NP
R332 0_NPR332 0_NP
R275 0_NPR275 0_NP
R372 0_NPR372 0_NP
R307 0_NPR307 0_NP
R323 0_NPR323 0_NP
R301 0_NPR301 0_NP
R353 0_NPR353 0_NP
R311 0_NPR311 0_NP
R282 0_NPR282 0_NP
R345 56_NPR345 56_NP
R366 0_NPR366 0_NP
R320 0_NPR320 0_NPR317 0_NPR317 0_NP
R329 0_NPR329 0_NP
R356 0_NPR356 0_NP
R280 0_NPR280 0_NP
C120
10nF_NP
C120
10nF_NP
R298 0_NPR298 0_NP
R279 0_NPR279 0_NP
R354 0_NPR354 0_NP
R378 0_NPR378 0_NP
C119
10nF_NP
C119
10nF_NP
C114
10nF_NP
C114
10nF_NP
R326 0_NPR326 0_NP
R309 0_NPR309 0_NP
R328 0_NPR328 0_NP
C121
10nF_NP
C121
10nF_NP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
VC7
PCIE3.3VCC
2.5VCC
USRVCC
VC4
VC8
PCIE3.3VCC
2.5VCC
USRVCC
VC5
VC9 VC10
PCIE3.3VCC
2.5VCC
USRVCC
VC6VC11
PCIE3.3VCC
2.5VCC
USRVCC
VC10
PCIE3.3VCC
2.5VCC
USRVCC
VC11
PCIE3.3VCC
2.5VCC
USRVCC
VC12
PCIE3.3VCC
2.5VCC
USRVCC
VC7
PCIE3.3VCC
2.5VCC
USRVCC
VC8
PCIE3.3VCC
2.5VCC
USRVCC
VC9
VC12
VC1
VC3
VC13
VC10
VC13
VC12
VC11
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C3
C4
C1
C5
C2
C6
C7
VC2
VC4
VC5
VC1
VC11
PCIE3.3VCC
C25
C26
C27
C28
2.5VCC
USRVCC
VC13
C29
C30
C31
C32
C33
C34
C35
C36
C21
C22
C23
C19
C20
C24
C8
C17
C18
C7
VC8
VC7
VC5
C8
C9
C16
C17
C18
C1
C7
C27
C28
C29
C30
C20
C27
C28
C29
C30
C36VC9
C23VC6
C20
VC2
PCIE3.3VCC
2.5VCC
USRVCC
VC1
VC3
VC4
VC5
PCIE3.3VCC
2.5VCC
USRVCC
VC2
VC6
PCIE3.3VCC
2.5VCC
USRVCC
VC3
1.5VCC
USRVCC
PCIE3.3VCC
2.5VCC
PCIE3.3VCC
2.5VCC
USRVCC
1.5VCC
DP03,5
DP13,5
F_TCK8
F_TMS8
DP23,5
F_TDO8
DP33,5
LA303,4,5,6
DACK1#3,4,5,6
BREQi3,5,6,9
PMEIN#3,5,12
ADS#3,4,5,6
BTERM#3,4,5,6
F_TDI8
CCS#3
C[36:1]8,13
BIGEND#3,5
BLAST#3,4,5,6
LA313,4,5,6
LA293,4,5,6
DMPAF/EOT#3,4,5,6
DREQ0#3,4,5,6
GPIO22,5,10
LD293,4,5,6
LD303,4,5,6
GPIO32,5,9
LD313,4,5,6
LA113,4,5,10
LA123,4,5
LA153,4,5,12
LA123,4,5
LA133,4,5,12
LA143,4,5,12
LA223,5,12
LA33,4,5,12
C88,13
C308,13
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side C resistor options
B
11 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side C resistor options
B
11 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side C resistor options
B
11 15Wednesday, December 14, 2005
Side C bus
Note LA29=ALE (J Mode),LA31= DT/R#(J Mode)
Note: LA30=DEN# (J Mode)
The components on this sheet are notinstalled by default.
91-0058-000-A
R467 0_NPR467 0_NP
R484 0_NPR484 0_NP
R410 0_NPR410 0_NP
R443 0_NPR443 0_NP
C128
10nF_NP
C128
10nF_NP
R414 0_NPR414 0_NP
R476 0_NPR476 0_NP
C133
10nF_NP
C133
10nF_NP
R408 0_NPR408 0_NP
R447 0_NPR447 0_NP
R430 0_NPR430 0_NP
R466 0_NPR466 0_NP
R448 0_NPR448 0_NP
R461 0_NPR461 0_NP
R392 0_NPR392 0_NP
R418 0_NPR418 0_NP
R422 0_NPR422 0_NP
R381 0_NPR381 0_NP
R389 0_NPR389 0_NP
R438 0_NPR438 0_NPR439 0_NPR439 0_NP
R478 0_NPR478 0_NP
R454 0_NPR454 0_NP
R441 0_NPR441 0_NPR442 0_NPR442 0_NP
R398 0_NPR398 0_NPC129
10nF_NP
C129
10nF_NP
R396 0_NPR396 0_NP
R460 0_NPR460 0_NP
C134
10nF_NP
C134
10nF_NPR468 0_NPR468 0_NP
C138
10nF_NP
C138
10nF_NP
R383 0_NPR383 0_NP
R421 0_NPR421 0_NP
R405 0_NPR405 0_NP
R429 0_NPR429 0_NP
R420 0_NPR420 0_NP
R459 0_NPR459 0_NP
R385 0_NPR385 0_NP
R394 0_NPR394 0_NP
R450 0_NPR450 0_NP
R475 0_NPR475 0_NP
R471 0_NPR471 0_NP
R487 0_NPR487 0_NP
R402 0_NPR402 0_NP
R416 0_NPR416 0_NP
R395 0_NPR395 0_NP
R440 0_NPR440 0_NP
R411 0_NPR411 0_NP
R428 0_NPR428 0_NP
R424 0_NPR424 0_NP
R400 0_NPR400 0_NP
R465 0_NPR465 0_NP
R409 0_NPR409 0_NP
R431 0_NPR431 0_NP
R473 0_NPR473 0_NP
C130
10nF_NP
C130
10nF_NP
R458 0_NPR458 0_NP
R479 0_NPR479 0_NP
R486 0_NPR486 0_NP
R446 0_NPR446 0_NP
C132
10nF_NP
C132
10nF_NP
R457 0_NPR457 0_NP
R463 0_NPR463 0_NP R464 0_NPR464 0_NP
R449 0_NPR449 0_NP
R387 0_NPR387 0_NP
R470 0_NPR470 0_NP
R483 0_NPR483 0_NP
C135
10nF_NP
C135
10nF_NP
R412 0_NPR412 0_NP
R417 0_NPR417 0_NP
R390 0_NPR390 0_NP
R452 0_NPR452 0_NP
R413 0_NPR413 0_NP
R433 0_NPR433 0_NP
R472 0_NPR472 0_NP
R453 0_NPR453 0_NP
R434 0_NPR434 0_NP
R455 0_NPR455 0_NP
R401 0_NPR401 0_NP
R393 0_NPR393 0_NP
R423 0_NPR423 0_NP
R427 0_NPR427 0_NP
C140
10nF_NP
C140
10nF_NP
R462 0_NPR462 0_NP
R382 0_NPR382 0_NP
R415 0_NPR415 0_NP
R435 0_NPR435 0_NPR436 0_NPR436 0_NP
R481 0_NPR481 0_NP
R391 0_NPR391 0_NP
R444 0_NPR444 0_NPR445 0_NPR445 0_NP
R469 0_NPR469 0_NP
R485 0_NPR485 0_NP
R399 0_NPR399 0_NP
R451 0_NPR451 0_NP
R388 0_NPR388 0_NP
R474 0_NPR474 0_NP
C137
10nF_NP
C137
10nF_NP
C131
10nF_NP
C131
10nF_NP
R384 0_NPR384 0_NP
R386 0_NPR386 0_NP
R426 0_NPR426 0_NP
R437 0_NPR437 0_NP
R407 0_NPR407 0_NP
R425 0_NPR425 0_NP
R406 0_NPR406 0_NP
R397 0_NPR397 0_NP
R419 0_NPR419 0_NP
R456 0_NPR456 0_NP
R404 0_NPR404 0_NP
R480 0_NPR480 0_NP
C139
10nF_NP
C139
10nF_NP
R403 0_NPR403 0_NP
R477 0_NPR477 0_NP
C136
10nF_NP
C136
10nF_NP
R432 0_NPR432 0_NP
R482 0_NPR482 0_NP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
VD14
PCIE3.3VCC
2.5VCC
USRVCC
VD2
VD9
PCIE3.3VCC
2.5VCC
1.5VCC
USRVCC
VD3
VD13
PCIE3.3VCC
2.5VCC
USRVCC
VD4
VD8
VD9
VD10
VD11
VD14
VD13
VD12
VD12
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D3
D4
D1
D5
D2
D6
D7
VD1
VD2
VD3
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D21
D22
D23
D19
D20
D24
D8
D9
D10
D11
D12
D3
D1
PCIE3.3VCC
2.5VCC
USRVCC
D2
D6
D7
VD5
VD8
VD7
VD6
VD5 D19
D8
D9
D10
D11
D12
D13VD4
D3
D1
D2
D6
D7D25
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
VD7
D25
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
PCIE3.3VCC
2.5VCC
1.5VCC
USRVCC
VD6
VD1
VD11
PCIE3.3VCC
2.5VCC
USRVCC
VD9
VD2
PCIE3.3VCC
2.5VCC
USRVCC
VD10
PCIE3.3VCC
2.5VCC
USRVCC
VD7
PCIE3.3VCC
2.5VCC
USRVCC
VD8
VD3
PCIE3.3VCC
2.5VCC
1.5VCC
USRVCC
VD11
VD4
PCIE3.3VCC
2.5VCC
1.5VCC
USRVCC
VD12
PCIE3.3VCC
2.5VCC
USRVCC
VD13
PCIE3.3VCC
2.5VCC
USRVCC
VD14
VD5
VD6
PCIE3.3VCC
2.5VCC
USRVCC
VD1
VD10
1.5VCC
USRVCC
PCIE3.3VCC
2.5VCC
PCIE3.3VCC
2.5VCC
USRVCC
1.5VCC
D[36:1]8,13
WAIT#3,5,6
LBE#03,4,5,6
LBE#13,4,5,6
LCLK_T3,5,9
LW/R#3,4,5,6
LD143,4,5,6
READY#3,4,5,6LBR14
LD133,4,5,6
LINTi#3,5,6
LRESET#3,5,6
DREQ1#3,4,5,6
LA153,4,5,11
LA213,5,9
LA233,5
LA243,5
LA133,4,5,11
LA143,4,5,11
LA253,5
LA263,5
LA223,5,11
LA283,4,5
LA33,4,5,11
LA283,4,5
LD203,4,5,6
LD213,4,5,6
LA273,5
LBE#23,4,5,6
LBE#33,4,5,6
PMEIN#3,5,11
D78,13
D298,13
D308,13
D198,13
D218,13
D108,13
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side D resistor options
B
12 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side D resistor options
B
12 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
FPGA Side D resistor options
B
12 15Wednesday, December 14, 2005
Side D bus
The components on this sheet are notinstalled by default.
91-0058-000-A
R584 0_NPR584 0_NP
R520 0_NPR520 0_NP
C147
10nF_NP
C147
10nF_NP
C149
10nF_NP
C149
10nF_NP
R522 0_NPR522 0_NP
C142
10nF_NP
C142
10nF_NP
R602 0_NPR602 0_NP
R579 0_NPR579 0_NP
R532 0_NPR532 0_NP
R585 0_NPR585 0_NP
R536 0_NPR536 0_NP
C152
10nF_NP
C152
10nF_NP
R563 0_NPR563 0_NP
R612 0_NPR612 0_NP
R596 0_NPR596 0_NP R598 0_NPR598 0_NP
R499 0_NPR499 0_NP
R488 0_NPR488 0_NP
R544 0_NPR544 0_NPR547 0_NPR547 0_NP
R578 0_NPR578 0_NP
R616 0_NPR616 0_NP
R611 0_NPR611 0_NP
C148
10nF_NP
C148
10nF_NP
C141
10nF_NP
C141
10nF_NP
R535 0_NPR535 0_NPR534 0_NPR534 0_NP
R489 0_NPR489 0_NP
R609 0_NPR609 0_NP
R550 0_NPR550 0_NP
R569 0_NPR569 0_NP
R617 0_NPR617 0_NP
R501 0_NPR501 0_NP
R589 0_NPR589 0_NP
R523 0_NPR523 0_NP
R517 0_NPR517 0_NP
R546 0_NPR546 0_NP
R551 0_NPR551 0_NP
R600 0_NPR600 0_NP
R545 0_NPR545 0_NP
R587 0_NPR587 0_NP
R513 0_NPR513 0_NP
R583 0_NPR583 0_NP
R559 0_NPR559 0_NP
R582 0_NPR582 0_NP
R577 0_NPR577 0_NP
R557 0_NPR557 0_NP
R524 0_NPR524 0_NP
R610 0_NPR610 0_NP
R556 0_NPR556 0_NP
R586 0_NPR586 0_NP
R508 0_NPR508 0_NP
R533 0_NPR533 0_NP
R565 0_NPR565 0_NP
R512 0_NPR512 0_NP
R572 0_NPR572 0_NP
R566 0_NPR566 0_NP
R604 0_NPR604 0_NP
R615 0_NPR615 0_NP
R574 0_NPR574 0_NP R576 0_NPR576 0_NP
R619 0_NPR619 0_NP
C153
10nF_NP
C153
10nF_NP
R521 0_NPR521 0_NP
R498 0_NPR498 0_NP
R575 0_NPR575 0_NP
R495 0_NPR495 0_NP
R613 0_NPR613 0_NP
R509 0_NPR509 0_NP
R502 0_NPR502 0_NP
C154
10nF_NP
C154
10nF_NP
R543 0_NPR543 0_NP
C150
10nF_NP
C150
10nF_NP
R515 0_NPR515 0_NP
R510 0_NPR510 0_NP
R514 0_NPR514 0_NP
R597 0_NPR597 0_NP
C151
10nF_NP
C151
10nF_NP
R592 0_NPR592 0_NP
R564 0_NPR564 0_NP
R525 0_NPR525 0_NPR529 0_NPR529 0_NP
R497 0_NPR497 0_NP
R542 0_NPR542 0_NP
C146
10nF_NP
C146
10nF_NP
R555 0_NPR555 0_NP
R607 0_NPR607 0_NP
R591 0_NPR591 0_NP
R620 0_NPR620 0_NP
R493 0_NPR493 0_NP
R562 0_NPR562 0_NP
R538 0_NPR538 0_NP
R590 0_NPR590 0_NP
R541 0_NPR541 0_NP
R568 0_NPR568 0_NP
R601 0_NPR601 0_NP
R606 0_NPR606 0_NP
R528 0_NPR528 0_NP
R593 0_NPR593 0_NP
R549 0_NPR549 0_NP
R516 0_NPR516 0_NP
C145
10nF_NP
C145
10nF_NP
R527 0_NPR527 0_NP
R491 0_NPR491 0_NP
C143
10nF_NP
C143
10nF_NP
R531 0_NPR531 0_NP
R573 0_NPR573 0_NP
R518 0_NPR518 0_NP
R603 0_NPR603 0_NP
R540 0_NPR540 0_NPR539 0_NPR539 0_NP
R490 0_NPR490 0_NP
R588 0_NPR588 0_NP
R594 0_NPR594 0_NP
R548 0_NPR548 0_NP
R558 0_NPR558 0_NP
R553 0_NPR553 0_NP
R526 0_NPR526 0_NP
R519 0_NPR519 0_NP
R599 0_NPR599 0_NP
R496 0_NPR496 0_NP
R552 0_NPR552 0_NP
R581 0_NPR581 0_NP
R530 0_NPR530 0_NP
R621 0_NPR621 0_NP
R608 0_NPR608 0_NP
R567 0_NPR567 0_NP
R561 0_NPR561 0_NP
R605 0_NPR605 0_NP
R505 0_NPR505 0_NP
R560 0_NPR560 0_NP
R511 0_NPR511 0_NP
R570 0_NPR570 0_NP
R580 0_NPR580 0_NP
R618 0_NPR618 0_NP
R506 0_NPR506 0_NP
R554 0_NPR554 0_NP
R571 0_NPR571 0_NP
R614 0_NPR614 0_NP
R504 0_NPR504 0_NP
R507 0_NPR507 0_NP
R494 0_NPR494 0_NP
R503 0_NPR503 0_NP
C144
10nF_NP
C144
10nF_NP
R595 0_NPR595 0_NP
R537 0_NPR537 0_NP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B21
B22
B23
B19
B20
B24
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B3
B4
B1
B5
B2
B6
B7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C3
C4
C1
C5
C2
C6
C7 C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C21
C22
C23
C19
C20
C24
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D3
D4
D1
D5
D2
D6
D7 D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D21
D22
D23
D19
D20
D24
A8
A11
A12
A9
A10
A13
A14
A16
A17
A18
A3
A4
A1
A5
A2
A6
A7
A15
A27
A25
A26
A28
A29
A30
A31
A32
A33
A34
A35
A36
A21
A22
A23
A19
A20
A24
C[36:1]8,11 D[36:1]8,12A[36:1]8,9 B[36:1]8,10
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
PADS
B
13 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
PADS
B
13 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
PADS
B
13 15Wednesday, December 14, 2005
The components on this sheet are notinstalled by default.
91-0058-000-A
PF27PF27
PF62PF62
PF97PF97
PF139PF139
PF2PF2
PF54PF54
PF88PF88
PF89PF89
PF109PF109
PF30PF30
PF65PF65
PF100PF100
PF141PF141
PF1PF1
PF40PF40
PF75PF75
PF117PF117
PF132PF132
PF7PF7
PF42PF42
PF76PF76
PF120PF120
PF33PF33
PF68PF68
PF102PF102
PF10PF10
PF45PF45
PF80PF80
PF124PF124
PF20PF20
PF72PF72
PF106PF106
PF107PF107
PF127PF127
PF48PF48
PF83PF83
PF126PF126
PF19PF19
PF58PF58
PF93PF93
PF133PF133
PF13PF13
PF25PF25
PF60PF60
PF95PF95
PF137PF137
PF16PF16
PF17PF17
PF51PF51
PF86PF86
PF112PF112
PF28PF28
PF63PF63
PF98PF98
PF140PF140
PF3PF3
PF38PF38
PF90PF90
PF110PF110
PF115PF115
PF66PF66
PF103PF103
PF142PF142
PF5PF5
PF37PF37 PF73PF73
PF118PF118
PF31PF31
PF129PF129
PF8PF8
PF43PF43
PF78PF78
PF121PF121
PF34PF34
PF35PF35
PF69PF69
PF104PF104
PF11PF11
PF46PF46
PF81PF81
PF125PF125
PF21PF21
PF56PF56
PF108PF108
PF128PF128
PF131PF131
PF84PF84
PF114PF114PF24PF24
PF55PF55
PF94PF94
PF134PF134
PF14PF14
PF49PF49
PF26PF26
PF61PF61
PF96PF96
PF138PF138
PF18PF18
PF52PF52
PF53PF53
PF87PF87
PF113PF113
PF29PF29
PF64PF64
PF99PF99
PF143PF143
PF4PF4
PF39PF39
PF74PF74
PF116PF116
PF101PF101
PF144PF144
PF6PF6
PF41PF41 PF77PF77
PF119PF119
PF32PF32
PF67PF67
PF9PF9
PF44PF44
PF79PF79
PF122PF122
PF36PF36
PF70PF70
PF71PF71
PF105PF105
PF130PF130
PF47PF47
PF82PF82
PF123PF123
PF22PF22
PF57PF57
PF92PF92
PF135PF135
PF12PF12
PF111PF111
PF23PF23 PF59PF59
PF91PF91
PF136PF136
PF15PF15
PF50PF50
PF85PF85
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
PF60PF59PF58PF57PF56PF55PF54PF53PF52PF51PF50PF49PF48PF47
PF33PF34PF35PF36PF37PF38PF39PF40PF41PF42PF43PF44PF45PF46
PF89PF90PF91PF92PF93PF94PF95PF96PF97PF98PF99PF100PF101PF102PF103PF104PF105PF106PF107PF108PF109PF110PF111PF112
PF136PF135PF134PF133PF132PF131PF130PF129PF128PF127PF126PF125PF124PF123PF122PF121PF120PF119PF118PF117PF116PF115PF114PF113
PF137PF138PF139PF140PF141PF142PF143PF144PF145PF146PF147PF148PF149PF150PF151PF152PF153PF154PF155PF156PF157PF158PF159PF160
PF184PF183PF182PF181PF180PF179PF178PF177PF176PF175PF174PF173PF172PF171PF170PF169PF168PF167PF166PF165PF164PF163PF162PF161
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
Prototype Footprint
B
14 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
Prototype Footprint
B
14 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
Prototype Footprint
B
14 15Wednesday, December 14, 2005
20X10 0.1" c-c Through hole Prototype Area
91-0058-000-A
PF154PF154
PF212PF212
PF266PF266
PF203PF203
PF217PF217
PF265PF265
PF202PF202
PF153PF153
PF159PF159
PF236PF236
PF200PF200PF206PF206
PF235PF235
PF253PF253
PF194PF194
PF148PF148
PF260PF260
PF198PF198
PF220PF220
PF267PF267
PF189PF189
PF173PF173
PF171PF171
PF147PF147
PF188PF188
PF238PF238
PF255PF255
PF195PF195
PF199PF199
PF172PF172
PF222PF222
PF250PF250
PF174PF174 PF175PF175
PF215PF215
PF168PF168
PF158PF158
PF240PF240PF234PF234
PF184PF184
PF225PF225
PF181PF181PF180PF180
PF155PF155
PF152PF152
PF218PF218
PF176PF176
PF205PF205
PF230PF230
PF245PF245
PF177PF177
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414 15 1516 1617 1718 1819 1920 2021 2122 2223 2324 2425 2526 2627 2728 28
FP3
28-pin SOIC, 0.05" pitch
FP3
28-pin SOIC, 0.05" pitch
PF162PF162
PF150PF150
PF264PF264
PF196PF196
PF216PF216
PF263PF263
PF241PF241
PF209PF209
PF145PF145
PF252PF252
PF186PF186
PF224PF224
PF247PF247
PF179PF179
PF233PF233
PF167PF167
PF190PF190
PF242PF242 PF243PF243
PF211PF211
PF223PF223
PF166PF166
PF161PF161
PF226PF226
PF246PF246
PF187PF187
PF197PF197
PF228PF228
PF164PF164
PF221PF221
PF249PF249
PF183PF183
PF160PF160
PF244PF244
PF262PF262
PF204PF204
PF156PF156PF157PF157
PF256PF256PF258PF258
PF178PF178
PF239PF239
PF227PF227
PF201PF201
PF146PF146
PF268PF268
PF193PF193
PF213PF213
PF251PF251
PF257PF257
PF191PF191
PF165PF165
PF149PF149
PF248PF248
PF208PF208
PF229PF229 PF231PF231
PF207PF207
PF261PF261
PF169PF169
11
22
33
44
55
66
77
88
99
1010
2020191918181717161615151414131312121111
2121
2222
2323
2424 25 2526 2627 2728 2829 2930 3031 3132 3233 3334 3435 3536 3637 3738 3839 3940 4041 4142 4243 4344 4445 4546 4647 4748 48
FP4
48-pin SSOP, 0.025" pitch
FP4
48-pin SSOP, 0.025" pitch
PF214PF214PF210PF210
PF259PF259
PF192PF192
PF219PF219
PF170PF170
PF163PF163
PF232PF232
PF254PF254
PF182PF182
PF185PF185
PF237PF237
PF151PF151
11
22
33
44
55
66
77
88
99
1010
2020191918181717161615151414131312121111
2121
2222
2323
2424 25 2526 2627 2728 2829 2930 3031 3132 3233 3334 3435 3536 3637 3738 3839 3940 4041 4142 4243 4344 4445 4546 4647 4748 48
FP5
48-pin SSOP, 0.025" pitch
FP5
48-pin SSOP, 0.025" pitch
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
NC BALLS
B
15 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
NC BALLS
B
15 15Wednesday, December 14, 2005
Title
Size Document Number Rev
Date: Sheet of
<Doc> 000
NC BALLS
B
15 15Wednesday, December 14, 2005
91-0058-000-A
N/CT1
N/CP1
N/CW6
N/CB12
N/CB11
N/CC11
N/CB13
N/CC8
N/CB7
N/CB9
N/CR2
N/CN3
N/CM2
N/CP3
N/CV8
N/CN2
N/CT2
N/CP2
N/CN4
N/CV7
N/CR1
N/CU2
N/CY6
N/CE6
N/CD4
N/CC5
N/CU4
N/CR3
N/CC10
N/CD11
N/CD5
N/CE4
N/CW7
N/CU7
N/CC4
N/CC12
N/C D16
N/C B8
N/C B5
N/C B3
N/C P4
N/C U1
N/C V5
N/C V2
N/C T3
N/C T4
N/C U3
N/C V6
N/C A5
N/C A6
N/C B4
N/C A4
N/C C7
N/C A9
N/C A7
N/C B6
N/C C6
N/C A12
N/C R4
U1B
PEX8311
U1B
PEX8311
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