power and control in networked sensors e. jason riedy and robert szewczyk presenter: fayun luo

Power and Control in Networked Sensors

E. Jason Riedy and Robert Szewczyk

Presenter: Fayun Luo

Outline

Introduction Real System Experiment One Processor Analysis Multiple Processor Analysis Summary Related Work

Introduction

Resource Constraints in WSN CPU speed Memory Communication Bandwidth Power

Energy Constraints

Not feasible to replenish the energy in deployed sensors

Current Battery has very limited capacity Battery technology has been improving at

only a modest pace

Architecture Design Dilemma

A typical PC: many processors Current networked sensor: one single

processor Dilemma: one processor or multiple

processors?

Intuition

Multiple processors lower frequency Lower frequency lower current and voltage Multiple processors meet real time constraints

better

Tradeoffs: Communication between processors is not free Allocating tasks to processors may be really hard

Roadmap

IntroductionIntroduction Real System Experiment One Processor AnalysisOne Processor Analysis Multiple Processor AnalysisMultiple Processor Analysis SummarySummary Related WorkRelated Work

Recap - Berkeley Motes

Processor Atmel AVR, 4MHz, 8-bit, 8KB inst mem and 512 bytes data mem

Radio FR Monolithics 916.5MHz, Speed up to 19.2 Kbps

Temperature Sensor

Analog Devices AD7418, I2C protocol

Light Sensor Photoresistor, 10~50

Recap - TinyOS Event-driven architecture Simple FIFO scheduler + graph of components Two level scheduling: events and tasks Events preempt tasks single shared stack

Microbenchmarks

Turn_off_all_devicesSetupWhile(1) {

Flash_Trigger_PinBody

}For I = 0 to N {

InstXInstX…InstX

}

Turn_on_lightSensor()

Instructions and Modules Experiment Result

Questions about Mote ExperimentHow about experiment on other Motes?

How do we measure the communication cost?

Mote Type Processor

Berkeley Motes One Atmel AVR chip

MIT µAMPS Two dedicated chips

UCLA Medusa Two chips

Rockwell WINS 32-bit RISC processor + one dedicated microcontroller

The paper claims the communication cost is free. Do you buy it?

TinyOS Experiment Result

Questions about TinyOS Experiment

How about other OS?

Different Scheduler?

Different event-task model?

Roadmap

IntroductionIntroduction Real System ExperimentReal System Experiment One Processor Analysis Multiple Processor AnalysisMultiple Processor Analysis SummarySummary Related WorkRelated Work

Architecture Model – Hardware Model

One central processor controls many ‘dumb’ devices, while each ‘intelligent’ device has a dedicated processor

Architecture Model – Task Model

f

f

T

Kf

fT

KnUtilizatio m

m :

Example:

T = 1 sec f = 4,000,000 Hz K = 2,000,000 cycles

= 2,000,000 / (1 * 4,000,000) = 0.5

fm = 2,000,000 / 1 = 2,000,000 Hz

Questions About the Assumptions of Task Model

Is the time span periodic in real world?

What might be different between different schedulers?

Architecture Model – Energy Model

)()(000

fVTIdtfIVIVdtPdtETTT

T

I(t)

I(f)

We will focus on I(f)

Current Model

AAAIII bfaIbfaI

foffunctionlinearaisfI

:)(

f

I Iactive

IIdle

f

I

IA

AAidleactiveA bfaIII

The bottom line is: all our current models are linear.

Define

One Processor Mathematical Model

)()(

)()1()(

fIfI

fIfII

AI

idleactives

Question: Does it model power off and power save mode?

),( fFI s Note: f, are dependent, = fm/f

Iactive(f)

(1- )Iidle(f)

One Processor Analysis

AmImAIs bfafabfFI 1),(

)(0 LineDashedaI

In a single processor, frequency is the main parameter we can adjust:

]1,0(

:)(0

2

mA

Iopt

I

fb

a

CurveSolida

Case 1: opt <= 1 Case 2: opt >= 1 run as low as possible

Run as fast as possible ( = fm/f)

1

1

One Processor with Overhead

Time and instruction overhead can be modeled by:

K = Kw + Ko

And processor utilization splits into:

= w + 0

Current consumption with overhead can be modeled by:

Is = F(f, ) = F(f, w + 0)

Reduce Overhead by Frequency Scaling

faa

fIcfIcfI

cfFcfI

fFfI

wAI

Ass

ws

ws

)(

)(1?)()(

),()(

),()(

0'

'

0

Example:

w = 0.5, o = 0.1, f = 4MHz, IA = 20mA,aI=2.0×10-8, aA = 4.0×10-8

c < 2.25 f’ = cf < 9MHz

f

I Iactive

IIdle

Questions about Frequency Scaling

Exactly how much should we scale the frequency?

What might change if we scale the frequency?

Roadmap

IntroductionIntroduction Real System ExperimentReal System Experiment One Processor AnalysisOne Processor Analysis Multiple Processor Analysis SummarySummary Related WorkRelated Work

Multiple Processors

Two fundamental questions:

1.How to partition the application tasks?

2.What are the inter-processor communication costs?

Application Partition

Bit-level 57%

Byte-level 28%

Other network processing

Other non-network CPU time

10%5%Split off the bit-level processing

Split off the whole network stack

Is it beneficial? What is the gain?

Cut off 45 cyclesBut add additional 130 cycles

Solution:Rewrite the structure of Component

Inter-Processor Communication Cost

How do we measure it? What factors may affect it?

Multiple ProcessorMathematical Model

),,(

)(

NfG

INIII Aprocsp

pIprocsp

pm

),( fFI s

Now, we have two variables: N,

We have only one variable

Frequency Scaling

),( fFI s

),,( NN

N

fGIm

))(1( AIms bbNII

),,( NfGIm

Scale frequency by 1/N:

We got:

Frequency Scaling

p II

p II

p II

Which means frequency scaling alone consumes more energy!!! Why?

))(1( AIms bbNII

bI > 0, bA > 0, > 0, N > 1 Is – Im < 0

Example: bI=2.0×10-8, bA = 4.0×10-8, = 0.5, N = 3

Is – Im = -8×10-8 < 0

p =

Reduction of Frequency and Overhead

wAI

Ams

wm

bb

fINII

NN

N

fGI

0

''

)(10

),,(

Example:

w = 0.5, o = 0.1, IA(f) = 20mA,bI=2.0×10-8, bA = 4.0×10-8

N < 5,001

If we can both reduce frequency and eliminate overhead

Question: what is the optimal N?

p II

p II

p II

p = w

Share Idle Current

II

Question: How difficult is it?

II II IIII

Conclusions

Single Processor:There is an optimal frequency for a given task load

Multiple Processor:Simple task partition and frequency scaling wouldn’t save any energy.We can save power in a multiple processor design if we can eliminate various types of overhead.

Big direction:The optimal architecture should build upon a single processor with hardware support for multiple contexts.

About the resultWhat do you think about the results? Results are very convincing and useful? Not quite convincing, limited usefulness?

One Processor: Task load may vary, not a constant.

Multiple Processor:

1. Limited experiment data.

2. Some assumptions that are difficult to achieve.

Big design direction: not quite convincing

Roadmap

IntroductionIntroduction Real System ExperimentReal System Experiment One Processor AnalysisOne Processor Analysis Multiple Processor AnalysisMultiple Processor Analysis Summary Related WorkRelated Work

Summary - Contributions Developed useful mathematical models of energy

consumption for single and multiple processors. Explored the tradeoffs between simple and multiple

processor Observed that Mere partition or simple frequency scaling

does not save energy in multiple processors system. Proved that it is possible to save energy in a multiple

processor system via elimination of various types of overhead.

Pointed out the direction of future architecture design for WSN

Summary - Limitations

Limited experiments Mathematical model can be refined Some assumptions difficult to achieve Results have limited usefulness Did not consider group behavior

Roadmap

IntroductionIntroduction Real System ExperimentReal System Experiment One Processor AnalysisOne Processor Analysis Multiple Processor AnalysisMultiple Processor Analysis SummarySummary Related Work

Related Work

Shin and Choi: real-time scheduler Lorch and Smith: Survey of techniques for

lowering power on portable computers Henkel: hardware-software partition Kirovski and Potkonjak: task partition

References

[1] Jason Hill, et al. “System Architecture Directions for Networked Sensors”

[2] John A. Stankovic, et al. “Real-Time Communication and Coordination in Embedded Sensor Networks”

[3] Shin and Choi “Power conscious fixed priority scheduling for hard real-time systems”

[4] J. Lorch and A. Smith “Software Strategies for Portable Computer Energy Management”

[5] J. Henkel. “A low power hardware/software partitioning approach for core-based embedded systems”

[6] D. Kirovski and M. Potkonjak. “System-level synthesis of low-power hard real-time systems”

[7] Radu Stoleru: Presentation - HW1