power- and performance-aware ip mapping for noc-based mpsoc platforms

Khalid Latif1, Amir-Mohammad Rahmani1, Tiberiu Seceleanu2, Hannu Tenhunen1

1University of Turku, Finland. 2ABB Corporate Research, Västerås, Sweden

Power- and Performance-Aware IP Mapping for NoC-

Based MPSoC Platforms

2

Outline

• Networks-on-Chip (NoCs)

• Problem

• Allocation/Placement

• Prioritization

• Placement Algorithm

• Comparison with existing techniques

3

Networks-on-Chip

• An on-chip interconnection.• Approach extracted from computer networks.• Communication resources increase with the number of cores.• Abstraction between computation and communication.• Sophiticated routing algorithms.• Plug and play platform.• Solution for 100s of cores on a single chip.

router router router

router router router

router router router

router router router

DSP Mem

PE0

Mem

PE1 PE2

UP

ACC CoP Arb

Ctrl Mng

router

router

router

router

FPU

ALU

MPEG

MP3

router router router router

PE5Profil PE3 PE4

4

Networks-on-Chip

• All the benefits are provided at the cost of router area, power consumption, data packetization and de-packetization.

•Cache coherence is the big issue.

router router router

router router router

router router router

router router router

DSP Mem

PE0

Mem

PE1 PE2

UP

ACC CoP Arb

Ctrl Mng

router

router

router

router

FPU

ALU

MPEG

MP3

router router router router

PE5Profil PE3 PE4

5

Networks-on-Chip

• Typical NoC

router router router

router router router

router router router

router router router

DSP Mem

PE0

Mem

PE1 PE2

UP

ACC CoP Arb

Ctrl Mng

• Comprises:

• Interconnects• Routers• Processing Elements

6

Networks-on-Chip

• Typical NoC• Key challenge:

• Flow control• Store and forword• Cut through

• Less buffer requirements

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Cycle

Chann

el H B B B T

H B B B TH B B B T

0123

Time-Space diagramsH B B B T

H B B B TH B B B T

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Cycle

Chann

el 0

123

Chann

el H B B B T

H B B B TH B B B T

0123

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Networks-on-Chip

• Typical NoC• Key challenge:

• Flow control• Store and forword• Cut through

DEADLOCK!!!All channels are free.

IP3Interface

IP2

InterfaceIP1

(HM)

Interface

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Networks-on-Chip

• Typical NoC• Key challenge:

• Flow control• Store and forword• Cut through

• Overall higher throughput but problem for time critical applications.• Good mapping/placement technique needed.

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Networks-on-Chip

• Typical NoC• Target:

• Minimization of communication cost.•In terms of hop-count.

• Average hop-count should be one (Best case).• Inturn, power optimization.

• Mapping Criteria:• Cores communicating more often should be neighbors.

• Neighboring cores might not serve, when needed.• High piriority core/process should be mapped to highly suitable position. Piriority? Suitable position?

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Core Prioritization

• Core Piriority:•Total number of packets to be communicated to-and-by the core. (Npi)•Number of neighboring cores required. (Ni)•Traffic distribution σxi

2 (statistical varience):•Number of neighbors of neighboring cores. (Nf)

2xiiPi

iNN

P

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Placement Algorithm

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Sample Application

• Priority:

MC > YUV Generator > ME > SRAM > DCT > Predictor > Q . . .

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Sample Application

• Placement

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Experimental Results

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Future Work

•Extension to 3D NoCs•Cosideration of TSV features

THANKS!

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