power plane and decoupling optimization · package decoupling modeled usi it / esr esling a...
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Power Plane and D liDecoupling
OptimizationpIsaac Waldron
OverviewOverview
Frequency- and time-domain powerFrequency and time domain power distribution system specificationsDecoupling design exampleDecoupling design example
Bare boardAdd d itAdded capacitorsBuried Capacitance
Conclusion
Frequency Domain PDS TargetsFrequency Domain PDS TargetsExcessive impedance seen by a device drawing power f PDS ill l flfrom a PDS will cause power voltage to fluctuateOn a board, impedance must be below target from DC to several hundred MHzWorking in the frequency domain allows quick estimation of power quality
Mag. of Z
|Z|targetZ
f
PDS Components
Z
Mag. of Z
|Z|targetZ
1 GHz
f
1MHz1KHz
Switching Electrolytic High Power/GroundPlanes
1 GHz100MHz
Switching Power Supply
Electrolytic Bulk Capacitors
gFrequency Ceramic Capacitors
PlanesBuried Capacitance
Time Domain PDS TargetsTime Domain PDS Targets
S-parameters and impedance areS parameters and impedance are calculated in the frequency domainDevice specifications are typically given inDevice specifications are typically given in the time domainE l i VCC i 10%Example: maximum VCC excursion 10% of nominal value
1.8 V VCC has an allowable range of 1.62 V to 1.98 V
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
for critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Board Imported from LayoutBoard Imported from Layout
Measuring impedance at the six VCC pins on U41
Defining the Target ImpedanceDefining the Target Impedance
To define the target
VR
To define the target impedance we need to consider two VRM
VR
M
RM
VR
M
C58
AN
ame=
vrm
factors:Peak current
Package Model
00
0
50
R5
V33
DC=VCC
V35
io
pullup
pulldown
logic_in
enableout_of_in
Cpkg
C58
Lpkg
L59
Rpkg
R60
Determines maximum impedance
Spectral powerDetermines cutoff frequency
Driver
Peak CurrentPeak current 37.87
Peak CurrentPeak current 37.87 mASix drivers and 0.18 V 40.00
Ansoft Corporation DriverDriver CurrentCurve Info max
mag(Ipositive(vrm))Transient 37.8706
maximum voltage swing:
20.00
25.00
30.00
35.00
sitiv
e(vr
m))
[mA
]
a s e t
5.00
10.00
15.00mag
(Ipos
( ) Ω= m 800mA 87.376V 18.0
0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00Time [ns]
0.00
Driver Spectrum1.00E-003
Ansoft Corporation DriverXY Plot 4Curve Info
Driver Spectrum
46 11 dB @ 400 MH
95% of driver power is below 667 MHz
1.00E-005
1.00E-004
mag(vrm_pow er)Transient-46.11 dB @ 400 MHz
-51.59 dB @ 83 MHz
1.00E-007
1.00E-006
rm_p
ower
)
1.00E-009
1.00E-008
mag
(v
1.00E-012
1.00E-011
1.00E-010
0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00Spectrum [GHz]
1.00E 012
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
for critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Bare BoardBare Board
Target impedance 800
Bare Board
impedance 800 mOhm to 667 MHz
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain
Choose capacitor or geometric
for critical devices
specification violations
to check for compliance
change to address violations
Alter design according to g
findings
Time Domain SchematicTime Domain Schematic
J5_VC
VC
C
VC
C D i
CC
J5_VC
C
C_U
41-2
io
pullup
logic_in
C_U
41-2
Cpkg
C58
L59
Driver
Board
VCC_U41-21VCC_U41-42
VCC_U41-44VCC_U41-63VCC_U41-84
VCC_U41-2
C
VCC_U41-2VCC_U41-21VCC_U41-42
VCC_U41-44VCC_U41-63VCC_U41-84
0
50
R5
V35pulldown
enable out_of_in
0
Lpkg
Rpkg
R60
x6
J5_VC
C 800 Mbps data rate
DDR2 IBIS driver into idealVRM
V33
DC=VCC0
DDR2 IBIS driver into ideal termination used as load for PDS
Package decoupling modeled i it / ESR ESLusing a capacitor w/ ESR, ESL
Switching Power NoiseSwitching Power Noise2.40
Ansoft Corporation BareU41 PowerCurve Info pk2pk
2.20
V(VCC_U41-2)Transient 0.5427
V(VCC_U41-21)Transient 0.4800
V(VCC_U41-42)Transient 0.5614
1.80
2.00
Y1
[V]
V(VCC_U41-44)Transient 0.5065
V(VCC_U41-63)Transient 0.5659
V(VCC_U41-84)Transient 0.5106
1.60
Y
1.20
1.40
Shaded area represents time domain specification 1.8 V ± 10% 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00
Time [ns]
1.20
Spectral AnalysisSpectral Analysis2.40
Ansoft Corporation BareU41 PowerCurve Info pk2pk
V(VCC_U41-2)Transient 0.5427~11-12 ns period
11-12 ns period corresponds to frequency of 80-90 MHz
1.80
2.00
2.20
Y1
[V]
V(VCC_U41-21)Transient 0.4800
V(VCC_U41-42)Transient 0.5614
V(VCC_U41-44)Transient 0.5065
V(VCC_U41-63)Transient 0.5659
V(VCC_U41-84)Transient 0.5106
~11-12 ns periodThis is confirmed by the spectral plot and correlates with the ideal driver simulation shown earlier
1.40
1.60
Y
2.50
12.50Ansoft Corporation BareSpectral
Curve Info
dB(V(VCC_U41-2))Transient
dB(V(VCC_U41-21))T i t
Name X Y
m1 90.0000 -20.5597
m2 400.0000 -28.4996-13.96 dB @ 90 MHz
d e s u a o s o ea e(peak @ 83 MHz)
0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]
1.20
-37.50
-27.50
-17.50
-7.50
Y1
m1
m2
Transient
dB(V(VCC_U41-42))Transient
dB(V(VCC_U41-44))Transient
dB(V(VCC_U41-63))Transient
dB(V(VCC_U41-84))Transient
-77.50
-67.50
-57.50
-47.50
0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00 900.00 1000.00Spectrum [MHz]
-87.50
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
h ddfor critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Adding Bulk CapacitorsAdding Bulk CapacitorsAdded two 47 uF capacitors ascapacitors as specified by VRM manufacturer
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
for critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Bare Board vs. Bulk CapacitorsBare Board vs. Bulk Capacitors
Resonance @ 50 MHz Bare BoardBoard w/
C
Target impedance 800 Bulk Capsimpedance 800 mOhm to 667 MHz
Bulk CapacitorsBulk Capacitors
Board w/ Bulk CapsTarget
impedance 800Resonance @ 50 MHz
impedance 800 mOhm to 667 MHz
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain
Choose capacitor or geometric
for critical devices
specification violations
to check for compliance
change to address violations
Alter design according to g
findings
Switching Power NoiseSwitching Power Noise2.40
Ansoft Corporation BulkU41 PowerCurve Info pk2pk
11 12 i d
2.20
V(VCC_U41-2)Transient 0.6787
V(VCC_U41-21)Transient 0.6995
V(VCC_U41-42)Transient 0.8191
~11-12 ns period
1.80
2.00
Y1
[V]
V(VCC_U41-44)Transient 0.7597
V(VCC_U41-63)Transient 0.7882
V(VCC_U41-84)Transient 0.6858
1.60
Y
1.20
1.40
Shaded area represents time domain specification 1.8 V ± 10% 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00
Time [ns]
1.20
Spectral AnalysisSpectral Analysis2.40
Ansoft Corporation BulkU41 PowerCurve Info pk2pk
V(VCC_U41-2)Transient 0.6787
~11-12 ns periodS 11 12 i d
2.00
2.20
Transient
V(VCC_U41-21)Transient 0.6995
V(VCC_U41-42)Transient 0.8191
V(VCC_U41-44)Transient 0.7597
V(VCC_U41-63)Transient 0.7882
Same 11-12 ns period as exhibited by bare board
1 40
1.60
1.80
Y1
[V] V(VCC_U41-84)
Transient 0.6858
2.50
12.50Ansoft Corporation BulkSpectral
Curve Info
dB(V(VCC_U41-2))Transient
dB(V(VCC_U41-21))Transient
dB(V(VCC U41 42))Name X Y
1 90 0000 13 9600
-13.96 dB @ 90 MHz
0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]
1.20
1.40
-37.50
-27.50
-17.50
-7.50
Y1
m1
m2
dB(V(VCC_U41-42))Transient
dB(V(VCC_U41-44))Transient
dB(V(VCC_U41-63))Transient
dB(V(VCC_U41-84))Transient
m1 90.0000 -13.9600
m2 50.0000 -37.1805-37.18 dB @ 50 MHz
Note that resonance @ 50 MHz
-77.50
-67.50
-57.50
-47.50
Note that resonance @ 50 MHz is not excited due as indicated by low spectral content at that frequency
0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00 900.00 1000.00Spectrum [MHz]
-87.50
Resonance at 50 MHzResonance at 50 MHz
U41
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
h ddfor critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Choosing a CapacitorChoosing a CapacitorTo reduce the effect 22 nFTo reduce the effect of a resonance, choose a capacitor
22 nF Capacitor
with a low impedance at the resonant ffrequency
Board w/ Bulk Caps
Added HF CapacitorsAdded HF Capacitors
52 20 nF capacitors were added across52 20 nF capacitors were added across the board to reduce high-frequency impedance and to cancel resonance at 50impedance and to cancel resonance at 50 MHz
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
for critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Bulk vs. HF Capacitors 1Bulk vs. HF Capacitors 1
Board w/ Bulk Caps
/
Target impedance 800 Board w/
HF Caps 1
impedance 800 mOhm to 667 MHz
No Resonance @ 50 MHzNo Resonance @ 50 MHz
HF Capacitors 1HF Capacitors 1
Board w/HF Caps 1Exceeds 800 mOhm @ 200 MHzTarget
impedance 800impedance 800 mOhm to 667 MHz
No resonance @ 50 MHzNo resonance @ 50 MHz
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain
Choose capacitor or geometric
for critical devices
specification violations
to check for compliance
change to address violations
Alter design according to g
findings
Switching Power NoiseSwitching Power Noise2.40
Ansoft Corporation HF1U41 PowerCurve Info pk2pk
2.20
V(VCC_U41-2)Transient 0.6481
V(VCC_U41-21)Transient 0.6979
V(VCC_U41-42)Transient 0.8802
1.80
2.00
Y1
[V]
V(VCC_U41-44)Transient 0.9182
V(VCC_U41-63)Transient 0.6925
V(VCC_U41-84)Transient 0.7319
1.60
Y
1.20
1.40
Shaded area represents time domain specification 1.8 V ± 10% 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00
Time [ns]
1.20
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
h ddfor critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Extending Low ImpedanceExtending Low Impedance10 1.2 nF capacitors pwere added across the board to extend minimum highminimum high-frequency impedance1 2 nF capacitor was Added capacitors1.2 nF capacitor was chosen due to low impedance at 200 MHMHz4 of these were located near U41located near U41
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
for critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
HF 1 vs. HF 2HF 1 vs. HF 2
New resonance @ 80 MHz
Board w/HF Caps 1
/
Target impedance 800 e eso a ce @ 80
Board w/HF Caps 2
impedance 800 mOhm to 667 MHz
Impedance exceeds 800 Oh @ 350 MH800 mOhm @ 350 MHz
HF 2HF 2
New resonance @ 80 MHz
Board w/HF Caps 2Target
impedance 800 e eso a ce @ 80impedance 800 mOhm to 667 MHz
Impedance exceeds 800 Oh @ 350 MH800 mOhm @ 350 MHz
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain
Choose capacitor or geometric
for critical devices
specification violations
to check for compliance
change to address violations
Alter design according to g
findings
Switching Power NoiseSwitching Power Noise2.40
Ansoft Corporation HF2U41 PowerCurve Info pk2pk
2.20
V(VCC_U41-2)Transient 0.2552
V(VCC_U41-21)Transient 0.2857
V(VCC_U41-42)Transient 0.2930
1.80
2.00
Y1
[V]
V(VCC_U41-44)Transient 0.4047
V(VCC_U41-63)Transient 0.3083
V(VCC_U41-84)Transient 0.3359
1.60
Y
1.20
1.40
Shaded area represents time domain specification 1.8 V ± 10% 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00
Time [ns]
1.20
Resonance at 80 MHzResonance at 80 MHz
U41
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
h ddfor critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Removing a ResonanceRemoving a ResonanceSix 8 nF capacitorsSix 8 nF capacitors were added near U41 to cancel resonance at 80 MHz
Added capacitors
Choosing a CapacitorChoosing a CapacitorTo reduce the effect 8 2 nFTo reduce the effect of a resonance, choose a capacitor
8.2 nF Capacitor
with a low impedance at the resonant ffrequency
Board w/HF Caps 2
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
for critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
HF 2 vs. HF 3HF 2 vs. HF 3
Board w/HF Caps 2
/
Target impedance 800 Board w/
HF Caps 3
impedance 800 mOhm to 667 MHz
Impedance crosses 800 Oh @ 500
No resonance @ 80 MHz800 mOhm @ 500 MHz
HF 3HF 3
Board w/HF Caps 3Target
impedance 800impedance 800 mOhm to 667 MHz
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain
Choose capacitor or geometric
for critical devices
specification violations
to check for compliance
change to address violations
Alter design according to g
findings
Switching Power Noise2.40
Ansoft Corporation FinalU41 PowerCurve Info pk2pk
Switching Power Noise
2.20
V(VCC_U41-2)Transient 0.2416
V(VCC_U41-21)Transient 0.2685
V(VCC_U41-42)Transient 0.2660
Maximum peak to peak noise of 371 mV
1.80
2.00
Y1
[V]
V(VCC_U41-44)Transient 0.3264
V(VCC_U41-63)Transient 0.3709
V(VCC_U41-84)Transient 0.3142
1.60
Y
1.20
1.40
Shaded area represents time domain specification 1.8 V ± 10% 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00
Time [ns]
1.20
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
h ddfor critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
Buried CapacitanceBuried CapacitanceDue to parasitic i d t it ill binductance it will be impossible to further decouple the board with capacitorscapacitorsUsing a thinner dielectric layer between power and ground planes introducesground planes introduces additional capacitance and reduces high frequency impedanceq y p
dAC ε=Capacitance of
parallel plates: dparallel plates:
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain to
Choose capacitor or geometric
for critical devices
specification violations
check for compliance
change to address violations
Alter design according to g
findings
HF 3 vs. Buried CapacitanceHF 3 vs. Buried Capacitance
Board w/HF Caps 3B d /
Target impedance 800 Board w/
Buried Capacitance
impedance 800 mOhm to 667 MHz
Impedance crosses 800 Oh @ 667800 mOhm @ >667 MHz
Buried CapacitanceBuried Capacitance
Board w/Buried Capacitance
Target impedance 800
Target impedance specification metCapacitanceimpedance 800
mOhm to 667 MHz
PDS Design FlowPDS Design Flow
EM extraction of impedance
Determine frequencies of
Simulate in time domain
Choose capacitor or geometric
for critical devices
specification violations
to check for compliance
change to address violations
Alter design according to g
findings
Switching Power Noise2.40
Ansoft Corporation BuriedU41 PowerCurve Info pk2pk
Switching Power Noise
2.20
V(VCC_U41-2)Transient 0.2177
V(VCC_U41-21)Transient 0.2295
V(VCC_U41-42)Transient 0.2418
Maximum peak to peak noise 273 mV24% smaller than limit
1.80
2.00
Y1
[V]
V(VCC_U41-44)Transient 0.2549
V(VCC_U41-63)Transient 0.2729
V(VCC_U41-84)Transient 0.2169
24% smaller than limit
1.60
Y
Time-domain noise specification met
1.20
1.40
Shaded area represents time domain specification 1.8 V ± 10%
Time domain noise specification met
0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]
1.20
ConclusionConclusionAnsoft software allows PCB engineers to gdesign effective decoupling solutions for their PCBsImpedance and resonant mode simulationsImpedance and resonant mode simulations connect the frequency domain to the spatial domain and allow selection of capacitor value pand placementFrequency domain extractions are useful for quickly optimizing PDS designs but timequickly optimizing PDS designs, but time domain simulations are necessary to ensure compliance with device specs
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