production readiness review of the mdt rod
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Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 1
Production Readiness Reviewof the MDT ROD
Electronic Design Details
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 2
MROD-X Design, Changes with respect to the MROD-1 design
MROD-1 MROD-X
3x
+
SHARC links usedfor data transport
RocketIO links usedfor data transport
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 3
MROD-Out FPGA
RocketIO
RocketIObetween MROD-In and MOD-Out FPGAs
MROD-In FPGA
RocketIO
FIFO8191 1.6 Gb/s
(160 MB/s)FIFO511
FIFO511
FIFO511
Regis-ters
FIFO511
HF
HF
Extended ReturnData
EventData
EventLength(+ID)
EventData
EventLength
(+ID)
ReturnData
FIFO511
RdRq
RdRq
Regis-ters
Extended ReturnData
ReturnData
High Priority Path
Low Priority PathConnections from other7 MROD-In FPGAs
•Backpressure•8B/10B•Extended Data•Length Look-ahead•TDC Limit
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 4
D5
D4
TDC Limit Register
D1
D2
D3
Dn
BOT
EOT}
12 bit, programmable 1 to 4096 data words
TDC Word Count bits [11:0]
Example when limit is set to 4:
D1
D2
D3
BOT
n
EOT6
D4
D1
D2
D3
BOT
EOT7
Register default = 0x60Maximum Event Fragmentfor 18 TDCs:18 x (BOT + 96 + 1 EOT) =1782 words
D4
D1
D2
D3
BOT
EOT6
D4
D1
D2
D3
BOT
EOT7
MROD-Out, Event Builder:Maximum Event Fragment8 x (1782 + 4 envelope words) =14288 words
No shutdown as with “Maximum Event Length”(Default 1K words)
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 5
Backpressure and ROD-BusyMROD-In
Buffer MemoryPartition
CSM link
RocketIOFIFOs
S-LinkFIFO
Link FIFOFull
HalfFull
AlmostFull
X
ROD-Busy•Backplane P3 -> TIM•Front panel NIM•Front panel Led
18x8k
8x8K
1x511
Whenone of 18 partitions Half Full
OrI2O-FIFO Half Full
thenCSM Link Busy
Front panel Led “B”
I2OFIFO512
HalfFull
MROD-In Buffer Memory Partition = 8K wordsConsider the situation where a lot of small events are received. Buffer Memory Partition does not get Half Full while I2O-FIFO rapidly fills.
I2O FIFO Half Full signals ROD-Busy.
Up Busy Error
I2O-FIFO:event fragment complete -> start MROD-In Output Controller
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 6
MROD-Out FPGA
TTC FIFOs
Event/Bunch-IDFIFO511
Trigger-TypeFIFO511
MROD-OutSHARCD
MA
Event/Bunch-IDFIFO511
Trigger-TypeFIFO511
EventBuilder
ROD-Busy•Backplane P3 -> TIM•Front panel NIM•Front panel Led
HF
HF
TTC1ECR
TTC4Event/Bunch-ID
TTC5TriggerType
DeSerialize
DeSerialize
ExtendedEvent-ID
Inc
Load
P3
back
plan
e dr
iven
by
TIM
•Debug•Test•Monitor
Other busy sources
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 7
Event Builder (1)
EventData
EventLength
EventData
EventLength
8 x
TTC FIFOsnot empty
RocketIO1A
RocketIO4B
1A Busy
4B Busy
Cha
nnel
Ena
ble
Reg
iste
r
ROD-Busy
EventBuilder
TestMode
Test Count Event-ID
12
3
5
Event Fragment
Trailer
Event FragmentHeader
4
1. Wait for TTC info2. Send Header3. Repeat
If a channel is enabled (wait for / read) event length entry
then read event data and insert Link Word Count
4. Until all channels read5. Send Trailer
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 8
Event Builder (2)Event Fragment Header•BOF (S-Link Control Word) 0xB0F00000•Header Marker 0xEE1234EE•Header Size 0x00000009•Format Version Number (VME register) 0x03000000•Module ID (VME Register) 0x00610080•Run number (VME Register) 0x00000000•Event –ID 0xEEeeeeee•Bunch-ID 0x00000bbb•Trigger-Type 0x000000tt•Detector Event Type (VME Register) 0x00000000•MROD BOB 0x80eeeeee
Test ModeNormal Running
eeeeee = from TTCTest Mode (run without TTC)
eeeeee = from Test Counter
Event Fragment Trailer •MROD EOB 0xF000wwww•MROD Status word (MSE1)•Number of Status Elements (NSE) 0x00000001•Number of Data Elements (NDE) 0x0000wwww•Status Block Position 0x00000001•EOF (S-Link Control Word) 0xE0F00000
2031-21 19181716 15-4 3 2 1 0
GOL Parity Error
TDC Parity Error
TDC Bunch-IDMiss Match
TDC Event-IDMiss Match
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 9
Spy (MROD-In)
SHARC
•Debug•Test•Monitor
Event DataFIFO512
Event LengthFIFO
16
MROD-In FPGA
RocketIO
Event DataFIFO8191
Event LengthFIFO511
MROD-InOutput
Controller
1. MROD-X Mode2. MROD-1 Mode3. MROD-X Debug
Spy Pre-scale registera. Nob. Allc. One in ‘n’ [1..65536]
AF
AF
AF
AF
By Default: Main data stream is not halted by Spy Channel
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 10
Spy (MROD-Out)
SHARC
•Debug•Test•Monitor
Event DataFIFO16K
Event LengthFIFO
4
MROD-Out FPGA
EventBuilder
1. MROD-X Mode2. MROD-1 Mode3. MROD-X Debug
Spy Pre-scale registera. Nob. Allc. One in ‘n’ [1..65536]
S-LinkFIFO511
AF
AF
AF
By Default: Main data stream is not halted by Spy Channel
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 11
Test GeneratorMROD-In
SFP
SHARCFPGA
TestFIFO
(Pre-scaled)Data and Event-Length
MROD_InFunctionality
ExternalLoop back
RocketIO
SHARCLinks
TTC L1A•CSM links unidirectional•Test generator•Transparent / Circular mode•Free running / Triggered •Internal test mode
SFP
FPGA
TestFIFO
(Pre-scaled)Data and Event-Length
MROD_InFunctionality RocketIO
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 12
XCF08P
XCF08P
XilinxXC2VP20
ASP
FPGA_TDOMROD-Out
MROD-In FPGAs
J26
SelSharcF for 3 or 4
MROD-Ins
TDI TDO
FPGA_TDI
MRO_XCF08P_TDI
FP
GA
_TD
O3
FP
GA
_TD
O4
XilinxXC2VP7/20
XilinxXC2VP7/20
XilinxXC2VP7/20
XilinxXC2VP7/20
XilinxXC2VP7/20
XilinxXC2VP7/20
XilinxXC2VP7/20
XilinxXC2VP7/20
ConfigurationBus
Configuration Bus
Remote Configuration (1)FPGA JTAG Chain
MTMbus
GeographicalAddress
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 13
Remote Configuration (2)
buffers
P2
P1
P3
buffers
rear frontVME bus
to all MRODmodules
MTMbus
USB-JTAG(= Xilinx
DownloadCable)
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 14
Other Extras
31-24Year
23-16Month
15-8Date
7-0Revision
FPGA firmware Date and Revision RegisterAutomatically determined during synthesis of VHDL code (TCL script)
OS Date Rev. File
31-24ID[31-0]
23-16 15-8 7-0
Unique Identifier Registers (DS2401)
Family-ID CRC ID[47-32]ID1ID2
S-Link Flush Mode
Temperature Readout for each FPGA (MAX 1618)
Zero Suppress Overridechoose to override zero suppression:
–Never–Once every ‘n’ [1..65536] events (first event of a run always non zero suppressed)
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 15
Production Readiness Reviewof the MDT ROD
Prototype issues
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 16
Design issues found in prototypes• Parallel termination for MROD-In FPGA configuration bus• Pull-up resistor on FPGA TDO• Wrong polarity for two capacitors• Small errors in silkscreen (Dip switch SW9, Ref. IC511, Pin 1 marking)
• Footprint for inductors too small• Short pin 1-2 for SMD LEDs (2 = Anode, 3 = Cathode)
• Power On Reset circuit: TPS3838SOT231 2
3SOT232 1
3
Rst_n pin 4
MR pin 3
VDD pin 1,5
Critical Ramp-Rate ~ 125 mV/msHappens to be exactly VME crate power supply Ramp-Rate!
Okay Fail
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 17
Minor Assembly issues found in prototypes
• One capacitor misplaced (module 1)
• Software Test Procedure found 2 open address pins on a Temperature Sensor (module 1)
• One wrong component placed. IC511 = NC7SZ125 instead of NC7SZ126 (module 3)
• One IC557 missing (NC7SZ08) (module 5)
• One wrong component placed. IC564 = NC7SZ08 instead of NC7SZ126 (module 5)
• Open output pin on buffer, SHARC JTAG chain (module 6)
Keep in mind that we asked for assembly of 6 modules (4 different production runs):2 eight-channel, 1 eight-channel, 1 eight-channel without SHARC-B, 2 six-channel
Assembly house did a great job. Some issues:
Automatic Optical Inspection would track many, if not all of these failures.
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 18
Changes to be made in PCBNeeded:• Parallel termination for MROD-In FPGA configuration bus (add 18 resistors)• Add Pull-up resistor to FPGA TDO• Change the polarity for two capacitors• Connect pin 1 and 2 for SOT23 SMD LEDs• Increase Footprint for inductors• Power On Reset (still under investigation… Use MAX 6863?)
Needed for MROD-Out @ 50 MHz:• Review Clock circuit on MROD-Out:
– Remove automatic Clock switch for selection of LHC-Clock or crystal– Re-route one LHC-Clock signal– MROD-Out FPGA prepared, system operation still to be demonstrated
Desirable:• Inverter for GA[4..0] connected to ASP• Review silkscreen (SW9 and IC511, Pin 1 marking)
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 19
Thank you
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 20
MROD_In
SFPSHARC
LHC_Clk1
MROD_In LHC_CLk2
MROD_In LHC_Clk3
MROD_In LHC_Clk4
MROD_Out
SHARCB
SHARCA
MROD-X Clocks
SFPXilinx
XC2VP7/20
XilinxXC2VP7/20
50/80 80
GO
L_X
Clk
AG
OL_
XC
lkB
Roc
ket
XC
lkB
Roc
ket
XC
lkA
40
RoboClock
ChA
_Clk
ChA
_Clk
x2
Sha
rcC
lk
ChB
_Clk
ChB
_Clk
x2Xilinx
XC2VP20
40
80RocketXClk
Clk
Sha
rcC
lk
Clk
x2
LHC
_Clk
S-Link
ZBT
ZBT
RoboClock
RoboClock
LHC_Clk(From TIM)
Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 21
MROD_In
SFPSHARC
MROD_In
MROD_In
MROD_In
MROD_Out
MROD-X Clocks (MROD-Out @ 50 MHz)
SFPXilinx
XC2VP7/20
XilinxXC2VP7/20
50/80 100
40
RoboClock
XilinxXC2VP20
LHC_Clk(From TIM)
50
100ZBT
ZBT
RoboClock
RoboClock
X
LHC_Clk1
LHC_CLk2
LHC_Clk3
LHC_Clk4
GO
L_X
Clk
AG
OL_
XC
lkB
Roc
ket
XC
lkB
Roc
ket
XC
lkA
ChA
_Clk
ChA
_Clk
x2
Sha
rcC
lk
ChB
_Clk
ChB
_Clk
x2RocketXClk
Clk
Clk
x2
LHC
_Clk
SHARCB
SHARCA
Sha
rcC
lkS-Link
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