programmable asic i/o cells

PROGRAMMABLE ASIC I/O CELLS

-Yalagoud Patil

CONTENTS Introduction DC Output

-Totem-Pole O/P-Clamp Diodes

AC Output-Supply Bounce-Transmission Lines

Introduction All programmable ASICs Contain some type of

input/output cells(I/O cells). These cells handle driving logic signals off-chips,

receiving and conditioning external inputs, as well as handling such things as electrostatic protection.

The following are different types of I/O Requirements.1.DC Output: Driving a resistive load at DC or low frequency.2.AC Output: Driving a capacitive load with a high speed logic signal off chip.

3.DC Input: Example sources are a switch, sensor, or another logic chip.4.Ac Input: Example sources are high speed logic signals from another chip.5.Clock Input: Examples are system clocks or signals on a synchronous bus.6.Power Input: We need to supply power to the I/O cells and the logic in the core, without introducing voltage drops or noise.

These issues are common to all FPGA so that the design of FPGA cells is driven by the I/O requirements as well as the programming technology.

DC Output The following figure shows a robot arm driven

by three small motors together with a switch to control the motors.

Armature current varies between 50mA and 0.5 mA when the motor is stalled.

This figure shows a CMOS complementary output buffer used in many FPGA I/O cells and its DC characteristics.

Output current is +ve, if it flows into the output, similarly input current is +ve if it flows into the inputs.

CMOS logic connected to the output draw minute amount of current, but bipolar TTL inputs can require several milliamperes.

If we force Output voltage of an output buffer using voltage supply and measure current, we find that buffer is capable of sourcing and sinking far more than specified current values.

Most of the vendors do not specify output characteristics because they are difficult to measure in production.

Some FPGA vendors do specifically allows connection for adjacent output cells in parallel to increase the output drive. If cells are not in the same chip there is a risk of Contention.

The remedy mentioned above to increase the DC drive capability is not a good idea to do so because we may damage or destroy the chip.

Following figure shows a simple circuit to boost the drive capability of the output buffers using OP-AMPS.

Totem- Pole Output Following figure shows totem-pole output

buffer and its DC characteristics. The high-level voltage, VOHmin, for a totem

pole is lower than VDD. Which makes rising and falling delays more symmetrical and closely matches TTL voltage levels.

Disadvantage: It will only drive the output as high as 3-4V. So its not a good choice.

Clamp Diodes Following figure shows the of clamp

diodes that prevent the I/O pad from voltage excursions greater than VDD and less than VSS.

AC Output Following figure shows an example of an

off-chip three-state bus. Chips that have inputs outputs connected to a bus are called bus transceivers.

One bit B1 on bus BUSA BUSA.B1. CHIP1.OE Signal OE inside CHIP1.

(CHIP1.OE is not connected to CHIP2.OE).

Initially CHIP2 drives BUSA.B1 high. The buffer output enable on CHIP2 goes low,

floating the bus. The buffer output enable on CHIP3 goes high and

the buffer drives a low onto the bus.

In figure (a),When the output enable E is ‘0’ the output is three stated. To measure the buffer delay. The resistor pulls the buffer output high or low depending on whether we are measuring.1.tENZL, when the output switches from hi-Z to 0.2.tENLZ, when the output switches from 0 to hi-Z.3.tENZH, when the output switches from hi-Z to 1.4.tENHZ, when the output switches from 1 to hi-Z.

A new driver may not start driving the bus until a clock edge after the previous driver floats it.

Supply Bounce Following figure shows an n-channel

transistor, M1,that is part of an output buffer driving an output pad, OUT1; M2 and M3 from an inverter connected to an input pad,IN1;and M4 and M5 are part of another output buffer connected to an output pad OUT2.

The voltage drop across Rs and Ls causes a spike on the GND net, changing value of Vss, leading to a problem known as supply bounce(With Vss bouncing to a maximum of VoLp).

Ground Bounce may also cause problems at chip.

This problem is overcome by FPGA’s by using quite I/O circuits that sense when the input to an out buffer changes.

Transmission Lines Most of the problems with driving large

capacitive loads at high speed occur on a bus and in this case we may have to consider the bus as a transmission line.

Following figure shows how a transmission line appears to a driver. Where Z0 is characteristic impedance.

There are several ways to terminate a transmission line.

1. Open circuit or Capacitive termination.(Ex PCI).

2. Parallel resistive termination.(Ex ECL).3. The’venin termination.4. Series termination at the source.5. Parallel termination with a voltage bias.6. Parallel termination with a series

capacitance.

An alternative to using a transmission line that operates across the full swing of the supply voltage is to use current mode signaling or differential signals with low voltage swings.

These and other techniques are used in specialized bus structures and in high speed DRAM.

Examples: Rambus and Gunning Transistor Logic (GTL) (These are analog rather than digital circuits).