programmable logic device devices and applications

Programmable Logic Device

Devices and Applications

• Architecture and Characteristic of PLD• FPGA Devices• Development Boards• FPGA Design Flow• Application in Signal Processing

T o p i c s

Architecture of MAX 7000 MacroCell

Architecture of MAX 7000

Architecture of CycloneIII LE

Architecture of CycloneIII LAB

Connection between LABs

Difference between CPLD & FPGA

CPLD FPGA

architecture Product term Look up Table

configuration inner EEPROM outer EEPROM

resource Rich in combination

Rich in Flip-Flops

density Low High

Used Filed Logical control Complex algorithms

Other resource

－ EAB ， PLL

security good So so

Global PLD Providers• www.altera.com– Inventor of CPLD ， Best FPGA

• www.xilinx.com– Inventor of FPGA ， Best FPGA

• www.latticesemi.com– Inventor of ISP

• www.actel.com– For G.I. and Astrionics

40nm 、 65nm 、 90nm 、 130nm High Performance FPGAs

65nm 、 90nm 、 130nm Low Cost FPGAs

CPLDs based on LUT

General CPLDs

Low Cost FPGAs with High Speed transceiver

structured ASICsBetter PerformanceLower Cost

Virtex Series High Performance FPGAsVitrex-5 for latestVitrex-5 TXT ， 120Gbps in a single chip ！

Spartan SeriesLow Cost FPGAsSpartan-3E for latest

CoolRunner Series CPLDsCoolRunner-II for latest

• Anti-fuse FPGAs （ Radiation protection ， perfect in security ）

• Flash Based FPGAs （ Inner configuration ，perfect in security ）

• CPLDs (EEPROM)

• FPGAs with ViaLink （ Low power cost ， perfect in security

• Earliest access to 40-nm technology AND a low-risk path to production

• Highest density, highest performance, AND lowest power

Stratix IV E FPGAs

• Up to 680K high-performance logic elements(LEs)

• DSP blocks—with a parallel architecture and up to 1,360 embedded 18x18 multipliers running at 550 MHz, Stratix IV FPGAs deliver up to 748 GMACS of DSP performance, a level unmatched by competing devices

• TriMatrix memory—three memory block sizes with up to 22.4 Mbits of embedded memory running at 600 MHz

• An FPGA fabric that is two speed grades , or 35 percent, faster than that of the nearest competitor

Transceiver-based Stratix IV GX FPGAs • Up to 48 high-speed transceivers supporting

data rates of up to 8.5 Gbps, including hard intellectual property (IP) protocols and signal integrity optimization blocks

• Up to four hard IP blocks for PCI Express (PCIe) compliant with PCIe Base Specification 2.0, 1.1, or 1.0, supporting x1, x2, x4, and x8 configurations. You’ll also have support for end-port and root-port applications.

• LVDS support up to 1.6 Gbps• Up to four 72-bit high-speed DDR3 interfaces

at 1,067 Mbps (533 MHz)

256-bit key AES encryption with FIPS-197 certification

• to 120,000 logic elements (LEs) and 4 Mbits embedded memory .

• 260-MHz multiplier performance with the highest multiplier-to-logic ratio in the industry.

• Robust clock management and synthesis with dynamically reconfigurable and flexible phase-locked loops (PLLs).

• Improved signal integrity with adjustable I/O slew rates.

• Support for high-speed external memory interfaces including DDR,DDR2, SDR SDRAM, and QDRII SRAM.

• Support for I/O standards including LVTTL, LVCMOS, SSTL, HSTL, PCI Express, LVPECL, LVDS, mini-LVDS, RSDS, PPDS.

Example—Software Defined Radio

Example—Software Defined Radio

New LUT & LE Based CPLD

DE2 Development and Education Board

DE1 Development and Education Board

DE2-70 Development and Education Board

Cyclone III FPGA Starter Kit

Cyclone® III Development Kit

Spartan-3E Starter Kit

• Xilinx XC3S500E FPGA• Xilinx XCF04 Platform Flash for storing FPGA

configurations• St Microelectronics M25P16 16Mbit Serial Flash• Intel TE28F128 (or JS28F128) 128Mbit StrataFlash• Linear Technologies Power Supplies• Texas Instruments TPS75003 Triple-Supply Power

Management IC• SMSC LAN83C185 Ethernet PHY• Micron 256Mbit DDR SDRAM

Quartus II 设计流程

• FPGA 提供了极强的灵活性，可让设计者开发出满足多种标准的产品。• FPGA 所固有的灵活性和性能也

可让设计者紧跟新标准的变化，并能提供可行的方法来满足不断变化的标准要求。

• 由于成本、系统功耗和面市时间等原因，许多通讯、视频和图像系统已无法简单地用现有DSP 处理器来实现， FPGA 尤其适合于乘法和累加 (MAC) 等重复性的 DSP 任务，最典型的就是 FFT 。

复数乘法器 RTL 示意图

蝶形运算单元示意图

蝶形运算单元 RTL 示意图

1024 点 16 位字长 FFT 耗时• TI 公司 TMS320C62x: 66 μs ( 定点 )• TI 公司 TMS320C64x: 36 μs ( 定点 )• ADI 公司 TigerSharc TS101: 39 μs ( 浮点 )• Xilinx 公司的 FFT IP 核在 100M 外频时钟下达到

40.96 us,246MHz 外频时钟下，速度达到 25.49 μs ( 定点 )

• Altera 公司的 FFT IP 核在 100M 外频时钟下达到20.7us, 在 333MHz 外频时钟下仅需要 6.3 μs ( 定点 )

• r-4 DIF FFT 算法在 100 MHz Virtex Ⅱ 上以多级串行同步流水方式 完成 1 024 点、 16 位复数点的块浮点 FFT 处理时间为 10. 2 μs

• SR DIF FFT 算法在 100MHz Virtex II Pro 上以6 级级联流水方式完成 1024 点、 16 位复数点的块浮点 FFT 处理仅需要 2.56 μs

• 采用 16 块工作在 550MHz 的 Virtex-5 XC5VSX240T （片内 1056 个 DSP48E Slices ）的全并行结构同时处理两路信号可在 1 个时钟周期内完成 1024 点 16 位 SR-FFT ，单路处理时间小于 2ns ，处理延时仅为十几μs 。

谢谢！2009.1.3