programming models and hardware dependent software abstraction for multi-processor soc
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CASTNESS'07Rome, Italy15-17 January 2007
Programming Models and Hardware Dependent Software
Abstraction for Multi-Processor SoC
Programming Models and Hardware Dependent Software
Abstraction for Multi-Processor SoC
Ahmed A. JerrayaTIMA Laboratory
46 Avenue Felix Viallet, 38031 Grenoble Cedex FranceTel: +33 476 57 47 59, Fax: +33 476 47 38 14
Email: Ahmed.Jerraya@imag.fr
CASTNESS'07 - 2Ahmed Jerraya
TIMA LaboratoryTechniques of Informatics and Microelectronics for computer Architecture
CNRS – INPG – UJF ~ 140 persons (incl. CMP) Research
Concurrent Integrated Systems, M. RENAUDIN System Level Synthesis, A. JERRAYA, F. PETROT MiCro & Nano Systems, S. BASROUR & B. COURTOIS Reliable Mixed-signal Systems, S. MIR QuaLiFication of Circuits, R. VELAZCO Verification and Modeling of Digital Systems, D. BORRIONE
Service: CMP 500 institutions, 60 countries, ICs, MEMS, CAD, Kits CMOS .12µ ST
CASTNESS'07 - 3Ahmed Jerraya
System-Level Synthesis Group (SLS)
Research area :
System on chip design
Objectives :
Decrease the design time through new design methodologies and tools
Methods :
Theoretical work : Hardware/software interfaces Heterogeneous components based design
Applications to understand the needs: Divx, MJPEG, H264
Validation of research in collaboration with industry
CPU
IP
DSP
MPEG4 Encoder
NoC
CASTNESS'07 - 4Ahmed Jerraya
System-Level Synthesis (SLS)
Staff (25): Group Leaders: A. Jerraya, F. Pétrot Permanent Staff : P. Amblard, A. Bouchhima, L. Kriaa
F. Rousseau, W. Youssef, N. Zergainoh
Ph.D. students: Y. Atat, Y. Cho, A. Chureau, P. de Massas, P. Gerin, X.
Guérin, S. Han, A. Kouadri Mostéfaoui, M. Oyamada, K. Popovici, B. Senouci, H. Shen
Industrial Ph.D.: M. Fiandino, R. Lemaire, Ch. Sahnine
Contracts: Industrial cooperation National & EC Funding: MEDEA , IST, RNRT, ITEA
CASTNESS'07 - 5Ahmed Jerraya
Acknowledgement
Prof F. Pétrot, Dr. F. Rousseau Dr. A. Bouchhima, Dr W Youssef PhD Students
A. Chureau K. Popovici H. Shen X. Guérin P. Gerin
CASTNESS'07 - 6Ahmed Jerraya
Summary Context
MPSoC design: Abstract software (e.g.: CORBA,
Simulink µCCM) and heterogeneous hardware (DSP, RISC)
Performance/cost constraints Time-to-market:
Reuse HW Platforms and SW components
Problems Architecture exploration for mapping of
SW components on Hardware platform Difficult Hardware dependent Software
debug The Challenge: Fast and efficient mapping
of software components to hardware platform
SW IPs
Target Hardware platform
SW IP Component
(F3)
SW IP Component
(F4, F6)
SW IP Component
(F2, F5)
SW IP Component
(F1)
DSP #1C5510
200 Mhz
DSP #2C5510
200 Mhz
GPPMPC86080 Mhz
FPGA
BusEthernet
Contrôle
CAN
CNA
Contrôle du signal radio
ApplicationSW
HDS
Binary SW
CASTNESS'07 - 7Ahmed Jerraya
Outline
1.- Programming Models: the Bridge between Hardware and Software
2.- Application-Specific Programming Models to Handle MPSoC
3.- Programming Models at Different Abstraction Levels
4.- Next Generation Design Flow Based on Programming Models
5.- Summary
CASTNESS'07 - 8Ahmed Jerraya
Context: Heterogeneous MPSoC
HardwareNode
SoftwareNode
Communication Network
Multi-Thread application
OperatingSystem
SpecificI/O
HAL
CPU DMAMEM
bridge Networkinterface
HardwareCo-processor
HW/SWInterface
Model
HW PROTOCOL
SW interface
Heterogeneous MPSoC Hardware nodes for performance Software nodes for flexibility Communication network
A programming model abstracts HW-SW interfaces for SW design.
Software node:
Specific CPU subsystem GPP, DSP, ASIP, ... I/O and memory architecture
Layered SW architecture Application code (threads) Hardware dependent software
CASTNESS'07 - 9Ahmed Jerraya
Programming Model: The Classical Solution to Abstract HW-SW Interfaces
Abstract HW model for SW design Programming language with
implicit primitives (e.g. module hierarchy & threads in SystemC)
API: Application Programming Interface (MPI, Posix Threads)
Simulation model (MPICH, Linux)
Used by SW community to free the SW designer from knowing HW details.
Facilitate porting of application SW over different architectures that support the same API.
SW modules
API
SW modules
API
SW modules
API
HW dependent SW (HDS)
HW architecture
ExecutionEnvironment
SW 1 SW 2 SW n...
Implementation Simulation
CASTNESS'07 - 10Ahmed Jerraya
SW Reuse Based on Programming Model (API):
MPEG4
HAL API
HDSx
CPUx
Comm. network
SW
API
HDSy
CPUy
Communication network
IP1
IP3IP2
API
MPEG4
API
IP
Executing same SW on different architectures using different CPUs
HDS = Hardware dependent Software (OS, HAL, Specific I/O)
CASTNESS'07 - 11Ahmed Jerraya
Defining HW-SW Interfaces
Application SW Designer: A set of system calls used to hide the underlying execution platform. Also Called Programming Model
HW designer: A set of registers, control signals and more sophisticated adaptors to link CPU to HW subsystems.
System SW designer: Low level SW implementation of the programming Model for a given HW architecture.
CPU is the ultimate HW-SW Interface Sequential scheme assuming HW is ready to
start low level SW design
SoC Designer Abstracts both HW and SW in addition
to CPU HW-SW interfaces tradeoff
Sequential SW program…Call HW (x, y, z)
x y zHW function wait start …
API
CPU (local Architecture)
HW Dependant SW
CPU Bus
HW-AdaptationStart done x y z
data@CTRLHW-SW
Interfaces
CASTNESS'07 - 12Ahmed Jerraya
Outline
1.- Programming Models: the Bridge between Hardware and Software
2.- Application-Specific Programming Models to Handle MPSoC
3.- Programming Models at Different Abstraction Levels
4.- Next Generation Design Flow Based on Programming Models
5.- Summary
CASTNESS'07 - 13Ahmed Jerraya
Classical HW/SW Interfaces Abstraction Models : The GAPS
Functionalspecification
Partitionning
Software design
Hardware design
Integration ISA/RTLHardware/Software
discontinuity
Correction cycle
Virtual PrototypeSystem Level
Early HW/SW integration
Software Sub-System
SoftwareThread 1
SoftwareThread 2
Hardware
BinarySW Appli
OSHAL
ISS
FIFO
IT Ctrl
MEM
HW
Software Sub-System
SoftwareThread 1
SoftwareThread 1
Hardware
GAPFully implicitHW/SW Interface
Fully explicitHW/SW Interface
AbstractHW/SW Interface
CASTNESS'07 - 14Ahmed Jerraya
Parallel Programming Models: The mixed HW-SW interfaces GAP
SoC Design Distributed SW Design
RTL(Verilog, BinSW)
VirtualPrototype
(RTL HW, BinSW, e.g.
SystemC)
MPI RT-CORBACORBA
SDL
Programming Model
SW: ALL
CPU imple-mentation
SW: ALL
RTL HWCPU orga-
nization
High Level Synchro-nisation
HW:NONE
Communi-cation
HW:NONE
- Concurrency- Threading
HW:NONE
HW-SW InterfacesExplicit concepts
Mixed Abstract HW-SW
Interfaces models
CASTNESS'07 - 15Ahmed Jerraya
Parallel Programming Models for MPSoC
RTL(Verilog, BinSW)
VirtualPrototype
(RTL HW, BinSW, e.g.
SystemC)
MPI RT-CORBACORBA
SDL
SoC Design Distributed SW Design
SW: ALL
CPU imple-mentation
SW: ALL
RTL HWCPU orga-
nization
TransactionAccurate
(TLM HW, TLM SW: Abstract CPU+HAL)
VirtualArchitecture(Abstract HW,
HL SW: Threads & Abstract OS +
CPU SS)
- OS- Specific I/O
- CPU SS- Abstract Bus- Explicit HW modules
Communication/Computation
Modules
AbstractInterconnect
Synchro-nisation
HW:NONE
Communi-cation
HW:NONE
- Concurrency- Threading
HW:NONE
Programming Model
HW-SW InterfacesExplicit concepts
HDSdevelopment
platform
SW applicationdevelopment
platform
CASTNESS'07 - 16Ahmed Jerraya
Outline
1.- Programming Models: the Bridge between Hardware and Software
2.- Application-Specific Programming Models to Handle MPSoC
3.- Programming Models at Different Abstraction Levels
4.- Next Generation Design Flow Based on Programming Models
5.- Summary
CASTNESS'07 - 17Ahmed Jerraya
Wires
API
HW modules
Applicationsoftware
HW modulesHardware
AbstractSW
Executionengine
Abstract comm. channels
or abs.channels
SoC Model with Abstract HW-SW Interfaces
Separate HW and SW design
Better HW & SW reuse.
Key Innovation to Higher Level HW/SW Interface Abstraction: from CPU to SW
Execution Subsystem
HW platform
Hardware
HW modules
Hardware interconnects
CPU
Hardware
Application Software +
Traditional view of SoC CPU is HW-SW
interface. SW validation
assumes HW ready.
HW & inf.to CPU
Hardware Dependent SWHW-SW interfacesto be abstracted
HW-SW Interfaces to be abstracted
Require to model HW, SW and CPU
Allow new architecture trade-off.
Boot MemBank
(Mem) CtrlCPU
TaskMgr
CASTNESS'07 - 18Ahmed Jerraya
Interface Modeling at Transaction Accurate Level
To be abstracted HAL software layer Details of CPU subsystem
SW interface : HAL API Context switch Synchronization (e.g. spin lock) IO Read/Write
HW interface : HW protocol Bus Protocol,… Specific HW interface (FIFO)
CPU DMAMEM
bridge Networkinterface
HardwareCo-processor
Multi-Thread application
OperatingSystem
SpecificI/O
HAL
Hardware
HW/SW InterfaceAt TransactionAccurate Level
HW PROTOCOL
HAL API
CASTNESS'07 - 19Ahmed Jerraya
Services for HW/SWInterfaces Adaptation
Both HW and SW interfaces are modeled as set of services (provided/required)
HW
Hyb
SW
Software Sub-System
SoftwareThread 1
SoftwareThread 2
Hardware
Component based interface adaptation Software elements Hardware elements Hybrid elements
CASTNESS'07 - 20Ahmed Jerraya
HARDWARE
SOFTWARE
Motion JPEG application :System Level Model
High Simulation speed
Easiest functional validation
No Operating System details
No details on communications
6 software and 2 hardware tasks Execution model synchronized
with communications
TRAFFICGENERATOR
VIDEOOUT
DEMUX
VLD IQ ZZ
IDCTLIBU
Communicationchannel thread
CASTNESS'07 - 21Ahmed Jerraya
Motion JPEG application :Virtual Prototype Model
Detailed communications Performances precision Fastidious Operating System
validation Very slow simulation
BinarySW AppliMutek OS
HAL
ISS
FIFO
IT Ctrl
MEM
TG
VCI Cross bar
VIDEO
Software tasks executed on a POSIX compliant OS: MUTEK
Software interpreted by the target processor ISS
Rest of the system at RTL level
HW/SW InterfaceAt Transaction Accurate Level
HW PROTOCOL
HAL API
CASTNESS'07 - 22Ahmed Jerraya
HWPROTOCOL
HALAPI
Motion JPEG application:Transaction Accurate Model
Pure software elements
CONTEXT INTERRUPT
Pure Hardware VCI FIFO
Hybrid elements CROSSBAR VCI WRAPPER EXEC_UNIT …
OS
INITSMPTHIS
COUNT
IO_ACCESSREAD
WRITE
DIAGNOSTIC
CONSUME
MEM VCI_WRAPPER
FIFO
XBAR
CXTINIT
SWITCH
SPINLOCK
UNLOCK
CONTEXT
EXEC_UNIT
HS_WRITEREQ ACK DATA
ITMASK
UNMASK
IT_CTRL
INTERRUPT
SPIN
HS_READ REQ ACK DATA
CASTNESS'07 - 23Ahmed Jerraya
Interfaces Modeling at Virtual Architecture Model
Apply the proposed approach to other abstraction level :
CPU DMAMEM
bridge Networkinterface
HardwareCo-processor
Multi-Thread application
OperatingSystem
SpecificI/O
HAL
Hardware
HW/SW InterfaceAt TransactionAccurate Level
HW interface
SW interfaceHW/SW InterfaceAt Virtual
ArchitectureLevel
HW interface
SW interface
Virtual Architecture, abstract the operating system and the specific communication
HW/SW interface design automation to enable :
Architecture exploration. Refinement
CASTNESS'07 - 24Ahmed Jerraya
Experiment Simulations
3 simulations
MJpeg Appli
Host OS(LINUX)
POSIX API
SW view of HW
POSIX API
System Level
MJpeg AppliPOSIX API
MUTEK OS
T.A. Model
HW PROTOCOL
POSIX API
Hardware
Transaction Accurate
MJpeg AppliPOSIX API
MUTEK OSHAL API
HAL (sparc)
ISS + Sub-System
HardwareHW PROTOCOL
Virtual Prototype
235s/frame(Fully explicit
HW-SW interfaces)
Same OS code in T.A. and V.P.
Same SW application code in the 3 models
Same SW Same SW
Same SW
0.017s/frame
(Fully implicitHW-SW interfaces)
X 70 1.2s/frame
(Abstract HW-SW interfaces)
X 200
CASTNESS'07 - 25Ahmed Jerraya
Outline
1.- Programming Models: the Bridge between Hardware and Software
2.- Application-Specific Programming Models to Handle MPSoC
3.- Programming Models at Different Abstraction Levels
4.- Next Generation Design Flow Based on Programming Models
5.- Summary
CASTNESS'07 - 26Ahmed Jerraya
HW and SW Design Approaches
Using high level HW-SW Interfaces models
SW Debug Application SW
Design API
Time
Classical HW & SW design approaches for computers
HDS DesignHW Design
Debug and integrationHW Design Application SW and HDS Design
HW & SW Design Approaches for SoC
HW-SW Interfaces design
Application SW Design
Application SWdevelopmentPlatform (VA)
HW Design
HDS developmentPlatform(TA)
Time savingDebug/
Performancesvalidation
CASTNESS'07 - 27Ahmed Jerraya
Conclusions: Programming Models for MPSoC
Abstract HW-SW Interfaces to enable Higher than RTL design
A platform for early application SW & HDS validation
Better match between HW & SW
Is an opportunity for new HW-SW codesign approaches and architecture Exploration
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