q=a*b+c system
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1
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
1
AbstractionAbstraction levelslevels of a of a digitaldigital systemsystem
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
RTL (Register Transfer Level)
SYSTEMq=a*b+c
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
2
FCMOS: Static Complementary CMOSFCMOS: Static Complementary CMOSVDD
F(In1,In2,…InN)
In1In2
InN
In1In2InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
……
2
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
3
CMOS InverterCMOS Inverter
Polysilicon
In Out
VDD
GND
PMOSgate
Metal 1
NMOSgate
Contacts
N Well
V in Vout
VDD
Contacts bulk pMOS
Contacts bulk nMOS
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
4CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC Analysis
VOL = 0VOH = VDD
VDD VDD
V = VDDIn
VoutVout
V = 0In
V = 0In
Vin = VDD
3
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
5
Simulated voltage transfer Simulated voltage transfer charatcteritisccharatcteritisc
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin
(V)
Vou
t(V)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
6
Regenerative PropertyRegenerative Property
A chain of inverters
v0 v1 v2 v3 v4 v5 v6
2
V (
Vol
t)
4
v0
v1v2
t (nsec)0
2 1
1
3
5
6 8 10Simulated response
Vdd = 5 VVlt = Vdd/2 = 2.5 V
4
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
7
Regenerative PropertyRegenerative Property
v0
v1
v3
finv(v)
f (v)
v3
out
v2 in
Regenerative Non-Regenerativev2
v1
f (v)
finv(v)
v3
out
v0 in
Es: Vin = Vo < Vlt (“0”)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
8
Complementary CMOS Logic StyleComplementary CMOS Logic StylePUNPUN
5
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
9Example Gate: NANDExample Gate: NAND
OUT = GOUT = F
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
10
Example Gate: NORExample Gate: NOR
6
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
11
CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response
V outVout
V DDV DD
inV = V DDV in = 0
(a) Low-to-high (b) High-to-low
CLCL
V in = 0
Vin = VDD
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
12
Delay DefinitionsDelay Definitions
Vout
tf
tpHL tpLH
tr
t
V in
t
90%
10%
50%
50% t
In
t
Out
Simulazione circuitale
Tp,HL Tp,LH
Simulazione logica
7
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
13CMOS Inverter Propagation DelayCMOS Inverter Propagation DelaySimplified approach 1Simplified approach 1
• modello di ordine 0 del MOSFET• capacità concentrata in uscita• fronti istantanei
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
14CMOS Inverter Propagation DelayCMOS Inverter Propagation DelaySimplified approach 2Simplified approach 2
Imax
VDD
Vout
Vin = VDD
CLImax
tpHL = CL VDD /2
I = vsat W Cox(Vdd –Vtn) max
capacità concentrata in uscitafronti istantaneitransitorio al 50% a corrente costante
8
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
15CMOS Inverter Propagation DelayCMOS Inverter Propagation DelaySimplified approach 3Simplified approach 3
tpHL = f(Ron.CL)
= 0.69 RonCL
V outVout
R n
R p
V DDV DD
V inV in
(a) Low-to-high (b) High-to-low
CLCL
ln (2)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
16
Inverter loadInverter load
Load
Delay Tp (50%)
Cint CL,extTp,int
Ron
CL = CL,ext + CintTp = Tp,int + 0,69 Ron CL,ext
Tp,int in prima approssimazione indipendente dal dimensionamento
9
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
17TwoTwo differentdifferent questionsquestions::
1. Find a model compute the propagation delay of a chain of logic cells i.e. a model for synthesis and logic simulation tools
2. Find a model that allow us to size a chain of logic gates designed at transistor level i.e. a simplified model for circuit analysis BEFORE the necessary simulation at transistor level
TwoTwo differentdifferent modelsmodels !!
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
18Propagation delay model (1) based on Propagation delay model (1) based on linear relationshiplinear relationship
• TP,int: intrinsic delay (i.e. delay with no output loading)• RC : fraction of the delay caused by the output load• STr: fraction of the delay due to input slope
C = ΣCin,eq + Clinea
For each input 7 parameters: TP,int,HL TP,int ,LH Rup RDown SS,UP SS,Down Ceq,in
10
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
19
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
20Propagation delay model (2) based on Propagation delay model (2) based on lookup tableslookup tables
........
........
........
......ValueTd
TP = TP,int + TP(Ts,in, Cext)
table 1) Tp(Ts,in, Cext)
CextTs,in
table 2) TS,OUT(Ts,in, Cext)
........
........
........
......ValueTs,out
CextTs,in
sono inoltre da calcolare TP,int Ceq,in
Cext = ΣCin,eq + Clinea
11
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
21EsempioEsempio: : definizionedefinizione delledelle tabelletabelle
Cext
val(ps)
Ts,in
4 12 28 80
5.6
101
261
533
160 (fF)
1069
(Ts,in in ns)(Cext in pF)
1500
(ps)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
22
Example: INVERTER 0.13um
pF
ns
pFns
Ts,
in
Ts,
in
Cext
CextTp,HL
Ts,out,fall
12
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
23
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
24
EsempioEsempio::
CL
CL
CLCin
13
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
252) Delay model to size a chain of logic 2) Delay model to size a chain of logic gatesgatesq dimensionare porte logiche connesse in
cascata al fine di minimizzare il tempo totaledi propagazione
q confrontare differenti schemi tuttidimensionati per minimizzare Tp,tot
q stimare Tp,tot
PRIMA di progettare le celle e di effettuare la simulazione circuitale che è semprenecessaria se si progetta una macrocella full-custom
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
26Delay model to size a chain of logic Delay model to size a chain of logic gates: logical effortgates: logical effort
isolare i contributi che dipendono da:• processo tecnologico• schema circuitale della porta logica• rete logica in cui la porta è inserita• dimensionamento
CL
CL
CLCin
14
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
27
q Ipotesi: § i transistori a canale n hanno uguale fattore
di forma (W/L) nMOS = Sn
§ i transistori a canale p hanno uguale fattoredi forma (W/L) pMOS = Sp
qα := (W/L)pMOS/ (W/L)nMOS
qE’ necessaria una specifica per definireil valore di α
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
28
B
VDD
A
Tpint ≈2 Tpint,not
Rup ≈ Rup,notRdown ≈ 2 Rdown,not
Cin = Cin,not = Cg(Sn,not + Sp,not)
B
VDD
A
A
Tpint ≈2 Tpint,not
Rup ≈ 2 Rup,notRdown ≈ Rdown,not
Cin = Cin,not
In prima In prima approssimazioneapprossimazioneSp = Sp,not
Sp = Sp,not
Sn = Sn,not
Sn = Sn,not
15
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
29
B
VDD
A
Tpint ≈ 2 Tpint,not
Rup ≈ Rup,notRdown ≈ Rdown,not
Cin = Cg(2Sn,not + Sp,not)
B
VDD
A
A
Tpint ≈ 2 Tpint,not
Rup ≈ Rup,notRdown ≈ Rdown,not
Cin = Cg(Sn,not + 2 Sp,not)
Sp = Sp,not
Sp = 2 Sp,not
Sn = 2 Sn,not
Sn = Sn,not
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
30αα:= (W/:= (W/L)L)pMOSpMOS/ (W// (W/L)L)nMOSnMOSsceltoscelto in in modomodo dada avereavere RupRup = = RdownRdown
αNOT = (Imax,n)/(Imax,p)
B
A
A B
F
VDDVDD
A B
A
B
F
VDD
A
A
F
1
2 2 2
2
21 1
4
4
Inverter 2-input NAND 2-input NOR
αNand2 = αNOT /2 αNor2 = 2 αNOT
Ipotesi: αnot = 2
16
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
31tempo di tempo di propagazionepropagazione dell’inverterdell’inverter di di area area minimiaminimia cheche nene pilotapilota unouno ugualeuguale
qTp,not = Tp,int + Rnot Cineq,not
qDefinizioni: § tpo : = Tp,int indipendente dal
dimensjonamento, funzione solo del processo e della scelta di α§ γ : = Cd/Cg funzione solo del processo (≈ 1)
q Tp,not = tpo + tpo/γ
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
32
GeneralizzazioneGeneralizzazione
CL
CL
CLCin
ii -1 i +1
17
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
33Delay model to size a chain of logic Delay model to size a chain of logic gates: logical effortgates: logical effort
tpo = Tp,int dell’invertitore di area minima pi parasitic delay (numero degli ingressi della porta logica)fi= Ceq,in,i+1/Ceq,in,ibi=numero di porte logiche connesse in uscitagi logical effort
iiiii gfbtpo
ptpoTpγ
+⋅=
NOTineq
iineq
NOT
ii C
CRR
g,,
,,=
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
34Logical EffortLogical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current
g = 1 g = 4/3 g = 5/3
B
A
A B
F
VDDVDD
A B
A
B
F
VDD
A
A
F
1
2 2 2
2
21 1
4
4
Inverter 2-input NAND 2-input NOR
assuming αNOT =2
18
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
35Delay model to size a chain of logic Delay model to size a chain of logic gates: logical effortgates: logical effort
tpo , tpo / γ dipendono solo dal processo e possono esserericavati tramite simulazione circuitale
pi , gi dipendono solo dallo schema circuitale e non daldimensionamento
bi dipende dalla rete in cui la parta logica è inseritafi dipende dal dimensionamentohi = bi fi gi stage effort
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
36Problem 1:Problem 1:Chain of N Inverters for Chain of N Inverters for minumumminumum TpTp
q Es: N =2
q Tp,tot = tpo + (tpo/γ) f1 + tpo + (tpo/γ) f2q F = f1 f2
-> Tp,tot = 2 tpo + tpo/γ (F/f2 + f2)
= 0 -> f2 = F1/2
q f1 = F/f2 -> f1 = f2 = F1/2
2
,df
totdTp
19
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
37Problem 1:Problem 1:Chain of N Inverters for Chain of N Inverters for minumumminumum TpTp
1,,/ ineqL
N CCFf ==When each stage is sized by f and has same eff. fanout f:
N Ff =
( )γ/10N
pp FNtT +=Minimum path delay
Effective fanout of each stage:
• each stage has the same effective fanout f• each stage has the same delay
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
38ExampleExample
CL= 8 C1
In Out
C1
283 ==fCL/C1 has to be evenly distributed across N = 3 stages:
( )
92*33
/1
0
0
=+=
+=
p
p
pp
tT
fNtT γ
assuming γ =1
I1 I2 I3
20
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
39ExampleExample
CL= 8 C1
In Out
C1
CL/C1 has to be evenly distributed across N = 3 stages:
C2= f C1 C3= f C2
I1 I2 I3
Sn2 =f SN1 Sn3 =f SN2= f2Sn1
•f =2•starting from the output:
• f3 = CL/C3 = 2 C3 = CL/2 = 4 C1• f2 = C3/C2 = 2 C2 = C3/2 = 2 C1• f1= C2/C1 = 2 C1 = C2/2 = C1
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
40
DimostrazioneDimostrazione per per induzioneinduzione
qN=1 è vero: f=F q Ipotizzo vero per N:qPer N+1 si ha:
e
si può quindi scrivere:
( ) N
N Ffff /1
21 ==== L
( ) ( )11 ++++= NfNftpo
tpoNTpγ
( )1121 ++ == N
N
NN ffffffF L
+
++= +
+
1
/1
1
)1( N
N
N
ffF
Ntpo
tpoNTpγ
21
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
41
q Il valore diche rende minimo Tp , è
da cui si ricava anche
1+Nf
( ) )1/(1
1
+
+ = N
N Ff
( ) 1
)1/(1
/1
1
1 +
+ ===+ N
N
Nf
N
fFF
fN
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
42Problem 2: Optimize PathProblem 2: Optimize Path
Cin
CL= 12 Cin
p1 = 2b1 =1g1 = 4/3
αNOT = 2
p2 = 2b2 =1g2 = 5/3
p3 = 2b3 =1g3 = 4/3
p4 = 1b4 =1g4 = 1
1
2
34
22
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
43
Optimum Effort per StageOptimum Effort per StageWhen each stage bears the same effort:
N Hh =
( ) ( ) ( ) N
iiitotP NHtpo
ptpohtpo
ptpoT /1
, γγ+=+= ∑∑∑
Minimum path delay
Effective fanout of each stage:
ii
i gbh
f =
Stage efforts: b1g1f1 = b2g2f2 = … = bNgNfN
∏∏==N
i
N
iineqL
N bgCCFGBh11
1,,/
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
44Problem 2: Optimize PathProblem 2: Optimize Path
Cin
CL= 12 Cin
αNOT = 2γ = 1
• h =2.44•Sizing from the output:
• f4 = h/(g4 b4 )= 2.44 f4 = CL/C4 C4 = CL/2.44 = 4.9 Cin• f3 = h/(g3 b3 )= 1.83 f3 = C4/C3 C3 = C4/1.83 = 2.7 Cin• f2 = h/(g2 b2 )= 1.45 f2 = C3/C2 C2 = C3/1.45 = 1.8 Cin• f1 = h/(g1 b1 )= 1.83 f1 = C2/C1 C1 = C2/1.83 = Cin
•Tp,tot/tpo = (S pi) + N h/ γ = 7 + 4 2.44 = 16.76•CL/ C1 = (CL/ C4 )*(C4/ C3)*( C3/ C2)*( C2/ C1) = 12
1
2
3 4
23
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
45
Example:Example:qCompare alternative logic structures
varying CLF = ABCDEFGH
p1 = 4b1 =1g1 = 6/3
p2 = 2b2 =1g2 = 5/3
p2 = 1b2 =1g2 = 1p1 = 8
b1 =1g1 = 10/3
scheme A
scheme B
scheme C
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
46Problem 3:Problem 3:Optimum Number of inverter (Buffer)Optimum Number of inverter (Buffer)
For a given load, CL and given input capacitance CinFind optimal sizing f and number of stages N
( )
+=+=
ff
fFt
fNtT p
pp lnlnln
/1 0
0
γγ
γ
0ln
1lnln2
0 =−−
⋅=∂∂
fffFt
fT pp γ
γ
fF
NCfCFC in
N
inL lnln
=→=⋅=
( )ff γ+= 1exp
24
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
47
Optimum Effective Optimum Effective FanoutFanout ffOptimum f for given process defined by γ
( )ff γ+= 1exp
fopt = 3.6for γ=1
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
48Sensibilità al numero di stadiSensibilità al numero di stadi
25
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
49
ProgettoProgetto bufferbuffer
q noto il processo tecnologico, è noto ilvalore di γ
q dal valore di γ si ricava il fattore ottimodi dimensionamento fott
q il numero ottimo di stadi èq si sceglie il valore di N interoq si calcola f = (F)1/N
ott
ott fF
Nlnln
=
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
50ExampleExample
CL= 8 C1
In Out
C1
when N = 3 stages: f = 2 < fott Tp/tpo = 9If we optimize the buffer
( )
6.78.2*22
8.2,2
6.1lnln
0
2/1
=+=
===
→==
p
p
ott
ott
tT
FfN
fF
Nγ =1
26
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
51
DimensionamentoDimensionamento
CL/C1 has to be evenly distributed across N = 2 stages:
•f =2.8•starting from the output:
• f2 = CL /C2 = 2.8 C2 = CL/2.8 = 2.8 C1• f1= C2/C1 = 2.8 C1 = C2/2.8 = CIN
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
52
Problem 4: Problem 4:
q Isolating fan-in from fan-out using buffer insertion
CLCL
N ? f ?
27
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
53
Optimum Effort per StageOptimum Effort per Stage
hH
NBFGHhN
lnln
11 =⇒==
When each stage bears the same effort:
( ) ( )
21
/1
1
1
1
,
)(
NNN
NHtpo
tpoNNptpo
htpo
ptpoT
NN
i
iitotP
+=
++−=
=+=
∑
∑∑
γ
γ
Minimum path delay
( )hh γ+= 1exp
N1, G1, B1, pi noti N2 inverterG2=1, B2=1, pi=1
CLCIn
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
54ExampleExample
CL = 500 CinF = ABCDEFGH
Cin
28
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
55
SoluzioniSoluzioni possibilipossibili αNOT = 2 γ = 1
q dimensiono per rendere minimo Tp,tot (problema 2, schema A)§ h = 6.2 (> hott)§ Tp,tot/tpo = 31.8
q Dimensionamento minimo della rete che realizza la funzione nand e a valle un buffer con F =500 (problema 2 con F =1, schema C, e problema 3 con F=500)§ Nbuffer = 4.8 -> N =5, f = 3.46 § Tp,tot/tpo = 9.65 + (5 +17) = 31.65
q Ottimizzo la rete che realizza la logica e la catena di invertitori contemporaneamente (problema 4)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
56
SoluzioneSoluzione problemaproblema 44q Schema A per realizzare AND8§ H = 500 * ? gi= 1480§ Nott= ln H/ ln hott = 5.69 -> N = 6§ N2 = N –N1 = 2§ h = (H)1/6 = 3.37§ Tp,tot/tpo = Spi + 6 h = 9+ 6* 3.37 = 29.22
q Schema C per realizzare AND8§ H = 500 * ? gi= 1666§ Nott= ln H/ ln hott = 5.8 -> N = 6§ N2 = N –N1 = 4§ h = (H)1/6 = 3.44§ Tp,tot/tpo = Spi + 6 h = 10 + 6* 3.44 = 30.64
29
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
57
ProgettoProgettoq noto il processo tecnologico, è noto il valore
di γq dal valore di γ si ricava il fattore ottimo di
dimensionamento hottq si calcola H = BGFq il numero ottimo di stadi èq si sceglie il valore di N intero e
si ricava N2 = N-N1q si calcola h = (H)1/N
q si ricava il valore di fi =h/bigi e quindi ildimensionamemnto di ogni stadioprocedendo dall’ultimo verso il primo
ott
ott hH
Nlnln
=
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
58
Branching EffortBranching Effort
pathon
pathoffpathon
C
CCb
−
−− +=
Critica path
Non critical path
Caso particolare:in uscita sono connesseN porte logiche uguali
Con-path = Ceq,inCoff-path = (N-1) Ceq,inb = N -> coincide con il fanout logico
30
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
59
Where Does Power Go in CMOS?Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
60
Short Circuit CurrentsShort Circuit Currents
Vin Vout
CL
Vd d
I VD
D (m
A)
0.15
0.10
0.05
Vin (V)5.04.03.02.01.00.0
31
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
61
LeakageLeakage
Vout
Vdd
Sub-ThresholdCurrent
Drain JunctionLeakage
Sub-threshold current one of most compelling issuesin low-energy circuit design!
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
62
SubthresholdSubthreshold Leakage ComponentLeakage Component
32
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
63
ModelloModello per per stimarestimare la la potenzapotenza in in programmiprogrammi di di simulazionesimulazionee e sintesisintesi logicalogica
ModelloModello basatobasatosusu looklook--up tableup table
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
64Inverter
pW
pW (valore medio)
pW
pF
ns
pFns
Po
ten
zast
atic
a
33
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
65
Energia assorbita a seguitodella transizione degli ingressiespressa in pJ
in questo valore sono consideratii contributi associati alla corrente di cortocircuito e agli effetti reattivi intrinseci
Ts,
inCext
Cext
Ts,
in
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
66
Caratterizzazione Tp
34
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
67
Principles for Power ReductionPrinciples for Power Reduction
qPrime choice: Reduce voltage!§ Recent years have seen an acceleration in
supply voltage reduction§ Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
qReduce switching activity qReduce physical capacitance
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
68
Maximum Clock FrequencyMaximum Clock Frequency
tCK,Q + max{tp,rc} + tsetup ≤ TCK
CK
DinRC
tCK,Q + min{tp,rc} > thold
D Q D QDoutclockedDinclocked Dout
35
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
69
Latch versus RegisterLatch versus Registerq Latch
stores data when clock is low or high
D
Clk
Q D
Clk
Q
q Registerstores data when clock rises (or falls)
Clk Clk
D D
Q Q
Ex: positive latch
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
70Latch Latch trasparentetrasparente durantedurante la la fasefasebassabassa del clockdel clock
36
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
71
ModelloModello a a interruttoriinterruttori
qCK =0
qCK =1
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
72
Register ParametersRegister Parameters
D
Clk
Q
D
Q
Clk
TpClkQ
Thold
T
Tsu
Delays can be different for rising and falling data transitions
TsetupTholdTp dal fronte del clock all’uscita
37
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
73
Register designRegister design
•input data NOT on an high impedance node•two clock phases: avoiding clock overlap
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
74
ModelloModello a a interruttoriinterruttori
qCK =0
qCK =1
38
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
75Typical standard cell static registerTypical standard cell static register
buffered Q and Q
generatedlocally and φφ
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
76RegistroRegistro staticostatico mastermaster--slaveslavememorizzazionememorizzazione: : bistabilebistabile
Tsu
39
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
77
RegistroRegistro staticostatico mastermaster--slaveslave
Thold
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
78
RegistroRegistro staticostatico mastermaster--slaveslave
TCK,Q
40
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
79
……
area
potenza statica (pW)
CMOS 0.13um
segnale di clock: Cin (pF)
Energia associata alle transizioni del clockper differenti valori di Q e D (pJ)
durata minima delle fasi alta e bassadel clock (ns)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
80
……
segnale di dato: Cin (pF)
Energia associata alle transizioni del datoper differenti valori di Q e del clock (pJ)
hold time in funzione delladurata della transizione del segnale diclock (ns)
setup time in funzione delladurata della transizione del segnale diclock (ns)
41
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
81
TP,CKQ e Tslope,outin funzione dellacapacità di carico e delladurata della transizionedel segnale di clock
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
82RegistroRegistro con con ingressoingresso asincronoasincrono di di resetreset
Reset = 0 Q = 1
42
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
83
ModelloModello a a interruttoriinterruttori
q Ingresso di reset applicato quando CK =0
qIngresso di reset applicato quando CK =1
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