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Research & Technology
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Heterogeneous Manycore with Self Adaptive Capabilities and the Corresponding Industrial
Needs
RAW 2012Fabrice Lemonnier, 22nd May, 2012
2 /2 /
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Manycore: main issue for industry
Programmability: Time to market
Development cost
Reuse of legacy software
Why take so many risks with manycore ?
Most of industrials want to continue like the past few years: compile without thinking (as much as possible) !
No more Free lunch ! In the near futurethe processors will all be made of multi-cores and many-cores.
Nevertheless, can we provide solutions to ease the programmation ?
3 /3 /
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Programmability: Homogeneous manycores
Tile-Gx100 from Tilera: 100 cores
Programmability:
• Standard C/C++ languages
• Multicore Development environmentTM (MDE)
• SMP Linux
• Bare Metal Environment
• Standard Debugging Tools (gdb 7)
4 /4 /
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Programmability: Homogeneous manycores
Fermi from Nvidia 512 cores organised in 16 Streaming Multiprocessor
Programmability:
CUDA parallel programming model: multi-threading
Programming languages: C/C++, openCL, …
5 /5 /
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Programmability: Homogeneous manycores
MPPA from Kalray: 256 cores organised in 16 clusters
Programmability:
•specific data flow language: sigmaC
•Tools to automatically map the application
6 /6 /
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Homogeneous manycores
Parallelisation is the only way to raise computing power for a low power consumption.
Homogeneity eases the programming aspects
Maximum of performance is reached only for static application.
Moreover, tools can be used to make automatic optimisation through data parallelism and generate static allocation and scheduling.
7 /7 /
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But parallelisation is not enough
Customization is necessary to raise the efficiency for a targeted application domain
• Customisation
Australian Desert Animal: the Thorny Devil
8 /8 /
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MPSoC
OMAP: Communication market
Heterogeneity for the best efficiency (computing power – power consumption ratio) but for a dedicated domain
9 /9 /
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Heterogeneous manycores
Heterogeneous manycore P2012 from ST
Cluster Cluster Cluster
Cluster Cluster Cluster
Cluster Cluster Cluster
Fabric Controller
core
Fabric
10 /10 /
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Heterogeneous manycores
Dedicated to a specific domain of application
Only affordable for large series of products.
Industry with small and medium series of products have no way to develop their own heterogeneous manycore
An alternative is to use a combination between multicore and …
11 /11 /
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FPGA + multicore
ZYNQ: Xilinx FPGA with a dual core ARM A9 MPCore
12 /12 /
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…or the inverse: GPP + FPGA
Intel® Atom™ Processor E6x5C Series
GPP + dedicated accelerators on FPGA on a Multi-Chip Package (MCP)
13 /13 /
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Our proposition
A combination between the heterogeneous manycore solution like P2012 and the FPGA+multicore approach like ZYNQ
Cluster Cluster Cluster
Cluster Cluster Cluster
Cluster Cluster Cluster
Fabric Controller
core
Fabric
14 /14 /
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Our proposition
A 3D stacked chip based on:
• A manycore layer
• A FPGA layer
15 /15 /
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Most important Advantages
Increase accessibility to heterogeneous manycores technology by allowing a customisation by the user
Reduction of the impact of the NRC
Allow implementation of self adaptive capabilities necessary for the future interactive applications and the constraints of the current and future technologies
16 /16 /
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Future applications issues
Embedded Real-Time Applications
low power consumption
low volume
Adapt to environment dynamicity, flexibility & dependability
Smart cameraCognitive radio UAV
17 /17 /
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Self adaptive capabilities, why?
• To be able to dynamically adapt the architecture to the current request of the application for the same power consumption
• Evolution of the technology: reduction of the reliability and the yield of current and future sub-micron technologies -> adaptation depending on the faulty cores.
• Increase energy efficiency
• Increase the programming efficiency by taking a part of the mapping complexity at runtime
• Temperature management -> adaptation of the application mapping
18 /18 /
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State of the art
Projects:
• Morpheus (FP6 project): heterogeneous chip with 3 FPGA technologies managed by an ARM processor.
• FOSFOR (ANR project): distributed OS for heterogeneous multicore on FPGA
• Main drawbacks:
• the scalability of the solution
• the limitation of the size of the FPGA area
19 /19 /
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20 /20 /
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Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
21 /21 /
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Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
22 /22 /
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Programming efficiency: common execution model
Master Nodes
Slave Nodes
GPP
eFPGA nodesDSP nodes
GPP Node
acceleratornode
NI
NoC
NI
Accelerator Interface (AI)
accrequests
control / status
DMA
DMArequests
data
Master-slave execution model
23 /23 /
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DMA Accelerator (slave)
receive_datasend_sync2acc
wait_syncsend_data
wait_syncwork
send_sync2dmu
GPP (master)
data_transfersynchro
requests FIFOssend_sync2gpp
Ensure hardware and software independency with the accelerator specificities
Master-slave execution model
24 /24 /
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, di
ssem
inat
ion,
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trib
utio
n, c
opyi
ng o
r ot
herw
ise
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of t
his
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men
t is
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ictly
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hibi
ted
with
out T
hale
s pr
ior
writ
ten
appr
oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
25 /25 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
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iew
, di
ssem
inat
ion,
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utio
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opyi
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ise
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his
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t is
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ictly
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hibi
ted
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hale
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ior
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Tool flow and MoC
Act
: Actor
: static cluster
Act
Act Act
Act
Act ActAct
Act
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
• Optimisation and parallelisation tools can only be used on static applications.
• Necessity to identify static clusters inside the applications based on SDF/CSDF MoC
SDF, CSDF MoC
actor: consume and produce token of data with predefined and static rules
26 /26 /
The
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rmat
ion
cont
aine
d in
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s do
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ent
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pert
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ALE
S.
You
are
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eby
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ied
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iew
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t is
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ictly
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hibi
ted
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oval
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Application (C code)
C to SpearDE representation
Conversion (Cosy)
Data parallelisation Mapping (SpearDE)
Graphic input
(manual)
Streaming optimisation (Cosy)
Compilation (Cosy)
executable code
architecture representation
Master coresSlave cores
Library of IPs
Tool flow and MoC
The Tool flow is based on 2 main tools:• Thales tool: SpearDE• ACE tool: Cosy
27 /27 /
The
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rmat
ion
cont
aine
d in
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s do
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ent
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ents
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pert
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TH
ALE
S.
You
are
her
eby
notif
ied
that
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iew
, di
ssem
inat
ion,
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utio
n, c
opyi
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ise
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his
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men
t is
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ictly
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hibi
ted
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hale
s pr
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Tools : partitionning, parallelisation and mapping
: Actor number x
: static cluster
Ax
A1 A2
A3
cluster1
A5
A4
: partition
: cluster input/output
: partition input/output
A1 A2
A3
cluster1p1
A5
A4
partition1
partition2
partition3
partition
mapping
A1.1 A2.1
A3
A5
A4
A1.2 A2.2
A1.3 A2.3
A1.4 A2.4
• FPGA
• DSP
• GPP
• DSP
• FPGA
• DSP
cluster1p1
28 /28 /
The
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rmat
ion
cont
aine
d in
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s do
cum
ent
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ents
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pert
y of
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ALE
S.
You
are
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eby
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ied
that
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iew
, di
ssem
inat
ion,
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opyi
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ise
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his
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men
t is
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ictly
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hibi
ted
with
out T
hale
s pr
ior
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
29 /29 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
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trib
utio
n, c
opyi
ng o
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ise
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his
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men
t is
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ictly
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hibi
ted
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hale
s pr
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Modularity and scalability: common interfaces
Homogeneous GPP nodes
Heterogeneous accelerators
nodes
GPP Node
AI
DSPNode
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Generic Interfaces
eFPGA Domain (Reconfigurable HW acc.)
Dedicated Accelerator
Node
Dedicated Accelerator
Node
30 /30 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
use
of t
his
docu
men
t is
str
ictly
pro
hibi
ted
with
out T
hale
s pr
ior
writ
ten
appr
oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
31 /31 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
herw
ise
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his
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men
t is
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ictly
pro
hibi
ted
with
out T
hale
s pr
ior
writ
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Act
: Actor
: static cluster
Act
Act Act
Act
Act ActAct
state 1
state 2
state 3
states management
Act
: Clusters group managed by one state management
: Cluster group input/output
: Cluster input/output
cluster groupevent
Dynamicity: the cluster group
32 /32 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
dis
trib
utio
n, c
opyi
ng o
r ot
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ise
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his
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men
t is
str
ictly
pro
hibi
ted
with
out T
hale
s pr
ior
writ
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Dynamicity at cluster group level
Act
sensordata : Actor
: static cluster
states managementevent
Act
state 1
nop
state 1
states management
states management
Act Act
Act
state 2
Act
Act
states managementevent
Act Act
Act
state 1
Act
Act
Act
: Clusters group managed by one state management
states management
Act Act
Act
state 1
Act
Actscatter
Act Act
Act
state 1.1
Act
Act
Act Act
Act
state 1.2
Act
Act
gather
: Cluster group input/output
: Cluster input/output
sensordata
cluster group 3
cluster group 4
cluster group 5
cluster group 2
cluster group 1 event
event
event
33 /33 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
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trib
utio
n, c
opyi
ng o
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ise
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his
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men
t is
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ictly
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hibi
ted
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hale
s pr
ior
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Start a new part of the application
Act
sensordata : Actor
: static cluster
states managementevent
Act
state 1
states management
states management
Act Act
Act
state 2
Act
Act
states managementevent
Act Act
Act
state 1
Act
Act
Act
: Clusters group managed by one state management
states management
Act Act
Act
state 1
Act
Actscatter
Act Act
Act
state 1.1
Act
Act
Act Act
Act
state 1.2
Act
Act
gather
: Cluster group input/output
: Cluster input/output
sensordata
cluster group 3
cluster group 4
cluster group 5
cluster group 2
cluster group 1 event
event
event
Act Act
Act
state 2
Act
34 /34 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
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trib
utio
n, c
opyi
ng o
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ise
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his
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men
t is
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ictly
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hibi
ted
with
out T
hale
s pr
ior
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Modification of the behaviour
sensordata : Actor
: static cluster
states managementevent
states management
states management
Act Act
Act
state 2
Act
Act
states managementevent
Act Act
Act
state 1
Act
Act
Act
: Clusters group managed by one state management
states management
Act Act
Act
state 1
Act
Actscatter
Act Act
Act
state 1.1
Act
Act
Act Act
Act
state 1.2
Act
Act
gather
: Cluster group input/output
: Cluster input/output
sensordata
cluster group 3
cluster group 4
cluster group 5
cluster group 2
cluster group 1 event
event
event
Act Act
Act
state 2
ActAct Act
Act
state 2
35 /35 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
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trib
utio
n, c
opyi
ng o
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ise
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his
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men
t is
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ictly
pro
hibi
ted
with
out T
hale
s pr
ior
writ
ten
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Modification of the parallelisation level
sensordata : Actor
: static cluster
states managementevent
states management
states management
Act Act
Act
state 2
Act
Act
states managementevent
Act Act
Act
state 1
Act
Act
Act
: Clusters group managed by one state management
states management
Act Act
Act
state 1
Act
Actscatter
gather
: Cluster group input/output
: Cluster input/output
sensordata
cluster group 3
cluster group 4
cluster group 5
cluster group 2
cluster group 1 event
event
event
Act Act
Act
state 2
ActAct Act
Act
state 2
36 /36 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
her
eby
notif
ied
that
any
rev
iew
, di
ssem
inat
ion,
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utio
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opyi
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men
t is
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ictly
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hibi
ted
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hale
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ior
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Dynamicity at cluster level
A1.1 A2.1
A3
A5
A4
A1.2 A2.2
A1.3 A2.3
A1.4 A2.4
• FPGA
• GPP
• FPGA
cluster1p1
A1.1 A2.1
A3
A5
A4
A1.2 A2.2
A1.3 A2.3
A1.4 A2.4
• DSP • G
PP
• DSP
cluster1p1
A1.1 A2.1
A3
A5
A4
A1.2 A2.2
A1.3 A2.3
A1.4 A2.4
• DSP • D
SP
• DSP
cluster1p1
timerelocation relocation relocation
37 /37 /
The
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ion
cont
aine
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s do
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ent
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ents
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ALE
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You
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eby
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iew
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ion,
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Dynamic relocation
I/O
NoC
GPP
Acc1
GPP
Acc1
GPP
Acc3
GPP
Acc4I/O
GPP
DDR ctrl
GPP
thread1 thread2 thread3 thread4
API
thread1 thread2
thread1 thread2thread3 thread4
API
thread1
thread2
Application
Tools for parallelisation and mapping
Acc1
Acc1
Acc3
Acc4
Dynamic relocation
Tools for parallelisation and mapping
runtime
compile time
38 /38 /
The
info
rmat
ion
cont
aine
d in
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s do
cum
ent
and
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ents
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pert
y of
TH
ALE
S.
You
are
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eby
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ied
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rev
iew
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ssem
inat
ion,
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utio
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opyi
ng o
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ise
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his
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men
t is
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ictly
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hibi
ted
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out T
hale
s pr
ior
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oval
. ©
TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
39 /39 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
that
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rev
iew
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ssem
inat
ion,
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utio
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opyi
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t is
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ictly
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
ApplicationAllocation file
Network services
SchedulerCluster
mngtTask mngt
Memory mngt
Communication management
Monitoring ActuatorsSemaphoreevent mngt
Virtualisation services
Self adaptive services
DIAGNOSISO = F(L)
ACTION
SYSTEM
MONITORING
A Virtualisation Layer for self adaptive capabilities
Virtualisation services provide a high level of abstraction of the heterogeneous resources: communication and accelerators managementSelf adaptive services define actions to be taken depending on events (monitoring): relocation, DVFS,…
VirtualisationLayer
kernel
40 /40 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
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atta
chm
ents
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pert
y of
TH
ALE
S.
You
are
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eby
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ied
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iew
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inat
ion,
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utio
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men
t is
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ictly
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hibi
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Self-adaptation
Heterogeneous Hardware
Controlled byKernel and
Virtualization layerEthernet
IMDCT MatrixMult
Accelerator/Virtual Code
Dynamicallocation / binding
DIAGNOSISO = F(L)
ACTION
SYSTEM
MONITORING
Mapping
GPP Node
AI
DSPNode
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Dedicated Accelerator
Node
Dedicated Accelerator
Node
eFPGA Domain (Reconfigurable HW acc.)
41 /41 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
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ied
that
any
rev
iew
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ssem
inat
ion,
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utio
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opyi
ng o
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ise
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his
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men
t is
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ictly
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hibi
ted
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hale
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oval
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
e
Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
42 /42 /
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
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pro
pert
y of
TH
ALE
S.
You
are
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eby
notif
ied
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iew
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inat
ion,
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men
t is
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ictly
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
Da
te /R
éfé
renc
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Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
3D stacked reconfigurable layer
43 /43 /
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éfé
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Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Map Accelerated functions
44 /44 /
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ALE
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éfé
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e
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Duplicate
45 /45 /
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ALE
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éfé
renc
e
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Migrate
46 /46 /
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ALE
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éfé
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e
Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
3D NETWORK
47 /47 /
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éfé
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NoC QoS
chip
GPP
icache
dcache
dLMEM GPP
NI
iLMEM eFPGA
eFPGA
dLMEM eFPGA
iLMEM DSP
DSP
dLMEM DSP
DDR
NI+
DDR ctrl
on chipshMEM
NI NI
controlNOC
bitstreamNOC
dataNOC
instructionNOC
test/debugNOC
48 /48 /
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ALE
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éfé
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ANoC (CEA)
GALS: asynchronous logic in nodes, local synchronous coreshighly scalable
between nodes: no global clock, no even local clockpower efficient and dependable
packet switchingwormhole protocol
low latency
49 /49 /
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éfé
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AEtheral NoC (TUe)
Guaranteed levels of services and performancesContention free routing by construction
wormhole routing specified at design time Globally Synchronous with time slots
50 /50 /
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éfé
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Conclusion (1)
Parallelisation is the only way to reach HPC for low power consumption.
But Industry doesn’t want to take the plunge
Moreover, parallelisation is not enough, customisation is also necessary
• Only affordable for high volumes and very difficult to programme
Reconfigurable customisation is the solution:
• Increase accessibility to heterogeneous manycore technology
• Allow implementation of self adaptive capabilities
51 /51 /
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Conclusion (2)
Self adaptive capabilities provide:
• Dynamic customisation of the manycore architecture to the current request of the application
• Reduction of the programming complexity by taking a part of the mapping complexity at runtime
• Fault tolerance: adaptation depending on the faulty cores.
• Energy efficiency
• Temperature management -> adaptation of the application mapping
52 /52 /
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ALE
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éfé
renc
e
Holistic Approach
Model of programmation
Model of Computation
Model of Execution
Flexible Hardware
Common Interfaces
strategies of relocation
Optimisation tools
Programming efficiency
self adaptive capabilities
3D NETWORK
53 /53 /
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Our proposition: a 3D stacked chip and …
A 3D stacked chip based on:
• A manycore layer
• A FPGA layer
54 /54 /
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…a complete platform
Virtualisation layer
relocatable binary code
Parallelisation, partioning
Application
Hardware Nodes
Compilation Synthesis, P&Rrelocatable bitstream
Hardware Abstraction Layer
Hardware Abstraction Layer API
Operating Library API
Kernel Resource Monitoring &
Allocation
DIAGNOSISO = F(L)
ACTION
SYSTEM
toolchain
operating library
heterogenousmanycore
MONITORING
55 /55 /
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éfé
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FlexTiles: FP7 project
FlexTileswww.flextiles.eu
Project coordinator: THALES
Funding budget: 3,670,000€
Starting date: 15/10/2011
Duration: 36 months
56 /56 /
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Consortium and questions
Partners & Third Party
Country Main scientific and technical contributions
THALES France Infrastructure and applications
KIT Germany Virtualisation layer
TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United Kingdom
FPGA Demonstrator
ACE Netherlands Parallelisation and compilation Tools
8 partners in 5 countries
57 /57 /
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With FlexTiles, Industry will be able to…
Take the plunge to the manycore utilisation
58 /58 /
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éfé
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Thank you for your attention
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