realizations of cmos fully differential current followers/amplifiers
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Realizations of CMOS Fully Differential Current
Followers/Amplifiers by
Hussain Alzaher and Noman Tasadduq
Electrical Engineering DepartmentKing Fahd University of Petroleum & Minerals
Dhahran, Saudi Arabia
3
Objective
Present fully differential CF/CA topologies. Investigate their characteristics. Compare and identify the best topology. Confirm the results using simulation. Give an application example.
4
Introduction
Why Fully Differential Architecture?
Fully differential architectures are essential to enhance the performance of mixed signal applications in terms of
Supply noise rejection. Dynamic range. Harmonic distortion.
5
Introduction
Theory behind fully differential opamp realization is well established.
Current Amplifier is the core analog building block for current mode circuits. Its fully differential realization is still under research.
6
Introduction
Current Amplifier (CA)/Current Follower (CF)
Conveys input current from a low impedance input terminal (X) to a high impedance output terminal (Z).
For a CA, current is conveyed with gain K. CF is a special case of CA in which gain (K) equals one. Can be classified as positive (input and output currents are
both going in the same direction) or the negative type (having currents in opposite directions).
IX
X ZpCAKIX IX
X ZnCAKIX
CA with +ve output CA with -ve output
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Low Power Current Amplifier
M13 M9 M10
M11VDD
M12
ISB
M3
M4
M8M7
M6M5
VDD
VSS
X ZpM2 M1
M20
IBP
Zn
M14
M15
M16
M17
M18
M19
K
1 K
1 K
K
M21
Single Input Dual Output Class-AB CA/CF
IX
XZn
ZpCA
KIX
KIX
Izp = -Izn = KIx
Vx=0
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Fully Differential CA (FDCA)
Four terminal device, with two input and two output currents.
1 2o o o diff diff cm cmI I I A I A I
Xp
Xn Zn
Zp Io1
Io2
I1
I2
Differential output current can be expressed as,
Ideally, Acm = 0.
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FDCA Topologies
X ZpCF
XZp
ZnCAI1
I2 I2
I1-I2
Io1=K(I1-I2)
Io2=K(I2-I1)
1
2
Topology ‘a’I1
XZn
ZpCA
XZn
ZpCA
I2
I1
I2
I2
I1
Io1=K(I1-I2)
Io2=K(I2-I1)
1
2
Topology ‘b’
Topology ‘c’
X ZpCF
X ZpCA
X ZpCF
X ZpCA
I1a
I1b
I2b
I2a
I2b
I1b
Io2=K(I2b-I1a)
Io1=K(I1b-I2a)
2
1
3
4
I1
I2
Adiff =2K
Adiff =2K
Adiff =K
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FDCA Topologies
Topology ‘a’
2 2 1( )( 1) / 2adiff p n pA K K K
Non-ideal Differential mode gain
Non-Ideal Common mode gain
_ 2 2 1( )( 1)cm a p n pA K K K
Error in Kp1 causes finite common mode output. When current gain Kp1 is represented by first order lowpass model,
common-mode gain exhibits highpass response.
Not suitable for high frequency applications.
Disadvantages
Advantages Lowest power consumption as compared to other two topologies.
X ZpCF
X Zp
ZnCAI1
I2 I2
I1-I2
Io1=K(I1-I2)
Io2=K(I2-I1)
1
2
1 1/( / 1)p oK s /( )acm oA s s i.e. if, and CF1 ideal
11
FDCA Topologies
Non-ideal Differential mode gain
Non-ideal Common mode gain
Slightly higher power consumption than topology ‘a’. Lower output resistance as compared to topologies ‘a’ and ‘c’.
Disadvantages
Topology ‘b’
1 2 1 2( ) / 2bdiff n n p pA K K K K
_ 1 2 1 2( ) ( )cm b n n p pA K K K K
Advantages Lower power consumption than topology ‘c’. Widest bandwidth (as will be shown in simulation results) Symmetric input and output resistances.
I1
XZn
ZpCA
XZn
ZpCA
I2
I1
I2
I2
I1
Io1=K(I1-I2)
Io2=K(I2-I1)
1
2
12
FDCA Topologies
Non-ideal Differential mode gain
Non-ideal Common mode gain
Highest power consumption. Most no. of active elements.Ideal differential gain
Disadvantages
Advantages Smallest input R. Output R= twice that of ‘b’
Topology ‘c’
2 1 4 2 3 4 1 1 2 2[ (1 ) (1 )] / 2cdiff p p p p p pA K K K K K K
2 1 4 2 3 4 1 1 2 2( ) [ (1 ) (1 )]ccm p p p p p pA
X ZpCF
X ZpCA
X ZpCF
X ZpCA
I1a
I1b
I2b
I2a
I2b
I1b
Io2=K(I2b-I1a)
Io1=K(I1b-I2a)
2
1
3
4
I1
I2
Io= K(I1b-I2a)-K(I2b-I1a)=K(I1b+I1a)-K(I2a+I2b)=K(I1-I2)
Io1=K(I1b-I2a) and Io2= K(I2b-I1a)
13
Simulation Results
Biasing Conditions
TSMC 0.18m CMOS process.Supply voltage = ±1.5V.
IBP=40µA and ISB=10µA.
14
Simulation Results
Differential-mode DC operation for the three topologies
All three topologies have comparable DC performance
15
Simulation Results
Differential-mode AC response for the three topologies
Topology ‘a’
57MHzTopology ‘b’
77MHz
Topology ‘c’36MHz
Topology ‘b’ has the widest bandwidth
16
Simulation Results
Ideal Common-mode AC responses
Topology ‘b’ and ‘c’ have excellent common-mode response.
Topology ‘a’ has common mode gain dependent on frequency.
18
Application Example
Fully Differential Current-Mode Sallen-Key Highpass filterUsing Topology ‘b’
Xp
Xn Zn
Zp
Io1 IopI1
I2 Io2
R1C2 C1
R1
C2 C1 Ion
Iip
Iin
R2
R2
21 2 1 2
21 2 1 2 1 2 2
( )( ) 1HP
s C C R RH s
s C C R R s C C R
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Application ExampleMagnitude response of the Sallen-Key Highpass filter
Results in good agreement
21
ConclusionTopology ‘a’
+: Least power consumption.
- : Freq. dependent Acm.
Topology ‘c’
+: Best Rin and Rout.
- : Power consumption and area are highest.
- : Differential-mode bandwidth is narrowest.
- : Mismatch results show freq. dependent Acm.
Topology ‘b’
-+: Consumes slightly more power than ‘a’ but much lower than ‘c’.
+: Widest differential-mode bandwidth.
+: Frequency independent common-mode gain. Best solution for high freq. applications.
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THANK YOU
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