reg-design [compatibility mode]

Register DesignRegister DesignRegister DesignRegister Design

EE141 Timing Issues1

Synchronous TimingSynchronous TimingSynchronous TimingSynchronous Timing

CLK

CombinationalLogic

R1 R2Cin Cout Out

In

EE141 Timing Issues2

Timing DefinitionsTiming DefinitionsTiming DefinitionsTiming Definitions

EE141 Timing Issues3

TIMING CLASSIFICATIONTIMING CLASSIFICATIONTIMING CLASSIFICATIONTIMING CLASSIFICATION

SYNCHRONOUS signal in lockstep with the SYNCHRONOUS-signal in lockstep with the system clock

MESO SYNCHRONOUS—signal has an unknown constant offset with respect to system clock

PLESIO SYNCHRONOUS l PLESIO SYNCHRONOUS- nearly same frequency

EE141 Timing Issues4

Latch ParametersLatch ParametersLatch ParametersLatch Parameters

D

Clk

Q

Clk PW

T

D thold

PWm tsu

Q tc-q td-q

EE141 Timing Issues5

Delays can be different for rising and falling data transitions

Register ParametersRegister ParametersRegister ParametersRegister Parameters

D

Clk

Q

ClkT

D thold

t»

»

Q tc-q

tsu

Delays can be different for rising and falling data transitions

NO CHANGE»

EE141 Timing Issues6

Delays can be different for rising and falling data transitionsChange in data has no impact on Q after clk edge Tdq=0

Timing DefinitionsTiming DefinitionsTiming DefinitionsTiming Definitions

t

CLK

Register

t

D

tholdtsu

DATASTABLE

CLK

D Q

tc 2 q

t

Q DATASTABLE tSTABLE

EE141 Timing Issues7

Synchronous designSynchronous designStatic gates —registers for storing the output and

provides well defined ordering of signal flow

Dynamic gates —reg. for storing the output

EE141 Timing Issues8

Designing SequentialDesigning SequentialL i Ci itL i Ci itLogic CircuitsLogic Circuits

EE141 Timing Issues9

Sequential LogicSequential Logicq gq g

OutputsInputsCOMBINATIONAL

LOGIC

Outputs

C rrent State

Inputs

RegistersNext state

Q D

Current State

CLK

2 storage mechanisms• positive feedback• charge based

EE141 Timing Issues10

• charge-based

Naming ConventionsNaming ConventionsNaming ConventionsNaming Conventions

In our text: In our text: a latch is level sensitive a register is edge triggered a register is edge-triggered

There are many different naming conventionsconventions For instance, many books call edge-

triggered elements flip-flopstriggered elements flip flops This leads to confusion however

EE141 Timing Issues11

Latch versus RegisterLatch versus Registergg Latch Register

stores data when clock is low

stores data when clock rises

D

Clk

Q D

Clk

Q

Clk

Clk Clk

D D

Q Q

EE141 Timing Issues12

Q Q

LatchesLatchesLatchesLatchesPositive Latch Negative Latch

In Out

CLK

DG

Q In OutDG

Q

clk

CLK

clk

CLK

In

Out

In

Out

Outstable

Outfollows In

Outstable

Outfollows In

EE141 Timing Issues13

LatchLatch--Based DesignBased DesignLatchLatch Based DesignBased Design

• N latch is transparent l h i• N latch is transparentwhen = 0

• P latch is transparent when = 1

N PNLatch Logic P

Latch

Logic

EE141 Timing Issues14

Timing DefinitionsTiming DefinitionsTiming DefinitionsTiming Definitions

t

CLK

Register

t

D

tholdtsu

DATASTABLE

CLK

D Q

tc 2 q

t

Q DATASTABLE tSTABLE

EE141 Timing Issues15

Characterizing TimingCharacterizing TimingCharacterizing TimingCharacterizing Timing

D Q D Q

tD 2 Q

D Q D Q

Clk Clk

tC 2 Q tC 2 Q

Register Latch

EE141 Timing Issues16

g

Maximum Clock FrequencyMaximum Clock Frequencyq yq y

FF’s

LOGIC

tp,comb

Also:tcdreg + tcdlogic > thold

t d: contamination delay = tcd: contamination delay minimum delay

tclk-Q + tp,comb + tsetup = T

EE141 Timing Issues17

LATCH DESIGN REQUIREMENTSLATCH DESIGN REQUIREMENTSLATCH DESIGN REQUIREMENTSLATCH DESIGN REQUIREMENTS

E f lk i l ti i l hEase of clk signal routing- single phase clk

Clk loadTransistor countProper data storage

Tsu=0 Thold=0 Tclk-q=0

EE141 Timing Issues18

MuxMux--Based LatchesBased LatchesMuxMux Based LatchesBased LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 0) (transparent when CLK= 1)

1 Q 0 Q

0D 1D

CLK CLK

InClkQClkQ InClkQClkQ

EE141 Timing Issues19

InClkQClkQ InClkQClkQ

Writing into a Static LatchWriting into a Static LatchWriting into a Static LatchWriting into a Static Latch

Use the clock as a decoupling signal

CLK CLK

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

CLK

Q D D

CLK

DCLK

CLK

Converting into a MUXForcing the state(can implement as NMOS-only)

EE141 Timing Issues20

MuxMux--Based LatchBased Latch

CLKCLK

Q

CLK

Q

D

CLK

EE141 Timing Issues21

MuxMux--Based LatchBased LatchMuxMux Based LatchBased Latch

CLKQ CLKQM

QM

CLK

CLK

EE141 Timing Issues22

NMOS only Non-overlapping clocks

Register designRegister design--master slave config.master slave config.Register designRegister design master slave config.master slave config.

C biCombine

a positive latch and a negative latch a negative latch

EE141 Timing Issues23

MasterMaster--Slave (Positive EdgeSlave (Positive Edge--T i d) R i tT i d) R i tTriggered) RegisterTriggered) Register

SlaveMaster

0 Q

Slave

D

CLK

1

0DQM

1QM

Q

CLK

CLK

Two opposite latches trigger on edgeAlso called master-slave latch pair

EE141 Timing Issues24

MasterMaster--Slave RegisterSlave Register----schematicschematicMasterMaster Slave RegisterSlave Register schematicschematicMultiplexer-based latch pair

QT2I2 I3 T4I5 I6

QM

Q

D

T2I2

T1I1

I3 T4I5

T3I4

I6

CLK

11 34

Clk load = 6 transistors Transistor count = 24

EE141 Timing Issues25 Single phase clk [ clk’ locally generated]

Timing propertiesTiming propertiesTiming propertiesTiming properties

Wh lk 0When clk = 0– T1 is on, T3, T4 off

D is sampled on Qm– D is sampled on Qm

– Tset up= I1 + T1 + I3 + I2Tset up I1 + T1 + I3 + I2– To ensure T2 has same voltage at its two

terminals else a wrong previous value may change Qm

EE141 Timing Issues26

Timing propertiesTiming propertiesTiming propertiesTiming propertiesWhen clk = 1

T lk Q T3 I6– Tclk-Q = T3 + I6– Thold = till T1 turns off / [0 (nearly]

– ----if D changes at the clk edge=1, – ---- D goes to T1 through I1 (gets delayed)D goes to T1 through I1 (gets delayed)– ---hence D reaches T1 after some delay – If clk’ reaches T1 earlier, T1 will turn off and

change in D will not affect Qm– If clk’ reaches T1 at the same time, T1 will turn

off and change in D will not affect Qm

EE141 Timing Issues27

off and change in D will not affect Qm

ClkClk--Q DelayQ DelayClkClk Q DelayQ Delay

CLK2.5

D1.5

tc 2 q(lh)Vol

ts

tc 2 q(hl)Q

0.5

c 2 q(hl)

2 0.50.5 1 1.5 2 2.50

time, nsec

EE141 Timing Issues28

Setup TimeSetup TimeSetup TimeSetup Time3.0 3.0

Q

QM2.0

2.5

I2 2 T22.0

2.5

D CLK

I 2 T

Vol

ts

1.0

1.5D

Q

QM

CLK

2 2

Vol

ts

1.0

1.5

I2 2 T2

0.0

0.5QM

0.0

0.5

2 0.50.2 0.4

time (nsec)

(a) Tsetup 5 0.21 nsec

0.6 0.8 102 0.5

0.2 0.4time (nsec)

(b) Tsetup 5 0.20 nsec

0.6 0.8 10

EE141 Timing Issues29

Reduced Clock Load Reduced Clock Load M tM t Sl R i tSl R i tMasterMaster--Slave RegisterSlave Register-------- reverse reverse transmission problemtransmission problem

CLK CLK

D QT1 I 1 T2 I 3

CLK CLKI2 I4

EE141 Timing Issues30

33rdrd implementationimplementation—— neg edge triggeredneg edge triggered33 implementationimplementation neg edge triggeredneg edge triggered

CLK

A

X

QCLK

AB

D

CLK

(a) Schematic diagramCLK

EE141 Timing Issues31

Non idealities of clkNon idealities of clkNon idealities of clkNon idealities of clk

Cl k l f ilClock overlap: can cause failures

CLK

CLK

(b) Overlapping clock pairs

CLK

EE141 Timing Issues32

RemedyRemedy------22--phase clock phase clock (AVOID CLK OVERLAP)(AVOID CLK OVERLAP)RemedyRemedy 22 phase clock phase clock (AVOID CLK OVERLAP)(AVOID CLK OVERLAP)

EE141 Timing Issues33

2 phase clk generation ckt.2 phase clk generation ckt.2 phase clk generation ckt.2 phase clk generation ckt.

EE141 Timing Issues34

Avoiding Clock Overlap (1Avoiding Clock Overlap (1--1 overlap)1 overlap)Avoiding Clock Overlap (1Avoiding Clock Overlap (1 1 overlap)1 overlap)CLK X

QCLK

AT1 I1 I2A

BD

QAT1 I1

T2

I2

CLK

(a) Schematic diagramCLK

CLK

(a) Schematic diagram

T1+ I1+I2+T2 > t 1-1 overlap

(b) Overlapping clock pairsCLK thold > t 1-1 overlap

EE141 Timing Issues35

Avoiding Clock Overlap (0Avoiding Clock Overlap (0--0 overlap)0 overlap)Avoiding Clock Overlap (0Avoiding Clock Overlap (0 0 overlap)0 overlap)CLK X

QCLK

AT1 I1AB

DAT1 I1

T2

I1

CLK

(a) Schematic diagramCLK

(a) Sc e at c d ag a

T1+ I1 +T2 > t 0-0 overlap

thold > t 0-0 overlap

EE141 Timing Issues36

Dynamic Storage MechanismsDynamic Storage Mechanisms--less transistorsless transistors

CLK

Dynamic (charge-based)Static

D

CLK

Q

CLK

CLKCLK

D

Q

CLK

D

EE141 Timing Issues37

Positive edge trigg. Dynamic registerPositive edge trigg. Dynamic registerPositive edge trigg. Dynamic registerPositive edge trigg. Dynamic register

Tsu ≥T1Thold = T1 to go off

EE141 Timing Issues38

holdTc-q = I1+ T2+ I2

Making a Dynamic Latch StaticMaking a Dynamic Latch StaticMaking a Dynamic Latch StaticMaking a Dynamic Latch Static

CLK

D D

CLKCLK

EE141 Timing Issues39

Other Latches/Registers: COther Latches/Registers: C22MOSMOS—A Clock-Skew Insensitive ApproachA Clock Skew Insensitive Approach

VDD VDD

M4

M2

CLK CLK M8

M6

D Q

M3CLK

M4CLK

CL1

X

CL2M7CLK

CLK M8

M1 M5

Master Stage Slave Stage

“K ” b dd d t k i it d t ti

EE141 Timing Issues40

“Keepers” can be added to make circuit pseudo-static

If D and If D and clkclk swappedswapped----??——charge sharing charge sharing problemproblemproblemproblem

D DD

D h 0 1` ft lk 0

EE141 Timing Issues41

D changes 0→1` after clk→0

Insensitive to ClockInsensitive to Clock--OverlapOverlap-- Q does not Q does not changechangechangechange

M2

VDD

M6

VDD

M2

VDD

M6

VDD

D Q

M40 0X

M8

D QX

M

Q

M

M3

M

Q

1 M71

MM1 M5

(a) (0-0) overlap

M1 M5

(b) (1-1) overlap

EE141 Timing Issues42

Dual-edge RegistersDual edge Registers

EE141 Timing Issues43

Other Latches/Registers: TSPCOther Latches/Registers: TSPC----SINGLE SINGLE PHASE CLKPHASE CLKPHASE CLKPHASE CLK

VDD VDD VDD VDD

Out

CLKIn CLK In CLK CLK

Out

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

EE141 Timing Issues44

(t a spa e t e C 0)(t a spa e t e C )

EE141 Timing Issues

Registers: TSPCRegisters: TSPCRegisters: TSPCRegisters: TSPCVDD VDD

VDD VDD

CLKIn CLK

OutIn CLK CLK

Out

I1 I2

Tsu =I1+I2T = I1 to go off

I1 I2I3 I4

EE141 Timing Issues46

Thold = I1 to go offTc-q =I3+I4

Including Logic in TSPCIncluding Logic in TSPCIncluding Logic in TSPCIncluding Logic in TSPCVDDVDD VDDVDD

QPUN

Q

In1 In2

CLKIn CLK CLKCLK

PDN In1

InIn2

AND latchExample: logic inside the latch

EE141 Timing Issues47

AND latch

Split output TSPC Register (less Split output TSPC Register (less complexity)complexity)complexity)complexity)

Less power-all nodes do not experience full swing so less current drive

VDD

M3

VDD

M6

Vdd

VDD

M

VDD

MVtp

CLKD

M3

M

YX

M6

Logic 0CLK

D

M3

M

YX

M6

Logic 1

M2

M M

M2

M1 M4

Vdd-Vt

M1 M40

EE141 Timing Issues48

Positive edge triggeredPositive edge triggered------4 stages4 stagesPositive edge triggeredPositive edge triggered 4 stages4 stages

VDD

M3

VDD

M6

Vtp

VDD

M

VDD

MVtp

CLKD

3

M

YX

6

Logic 1CLK

D

M3

M

YX

M6

Logic 1

M2

M M

M2

M1 M40

M1 M40

EE141 Timing Issues49

Modified TSPC edge triggered Modified TSPC edge triggered R iR i 3 3 RegisterRegister------3 stages3 stages

VDD

M3

VDD

QM9CLK

VDD

M6

CLKD

3

M2CLK

Y Q

9

M8X

6

M5

CLK

2

M1

8

M7

5

M41 74

EE141 Timing Issues50

An Alternative ApproachAn Alternative Approach---------- PulsePulse--Triggered Latches Triggered Latches Triggered Latches Triggered Latches (REDUCED HARDWARE)(REDUCED HARDWARE)

W d d d l ll

M t Sl P l T i d

Ways to design an edge-triggered sequential cell:

Master-Slave Latches

Pulse-Triggered Latch

L1 L2 LD

Clk

Q D

Clk

QData

D

Clk

Q

Clk

DataL1 L2 L

Clk Clk

Clk

ClkClk

EE141 Timing Issues51

Pulsed LatchesPulsed Latches-- less transistor, less less transistor, less clkclk load (load (TTsetupsetup can be zero)can be zero)clkclk load (load (TTsetupsetup can be zero)can be zero)

VDD VDDDD

M3

DD

M6

QCLK

VDD

CLKGD M2

M

CLKG M5

M

CLKGX

MP

MNM1 M4N

(a) register (b) glitch generation

CLK

CLKG

EE141 Timing Issues52

(c) glitch clock

Pulsed LatchesPulsed LatchesPulsed LatchesPulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

P1CLK P3 Qx

M3M6

M2D

M

M5

M4

P2

CM1 CLKD

EE141 Timing Issues53

SENSE AMPLIFIER BASED REG.SENSE AMPLIFIER BASED REG.——very fastvery fast

S R Q Q’

1 0 0 1

S0

R0

Q1

Q’1

0 1 1 00 1 1 0

1 0 0 1S=1 R=0

1 1 Q Q’

EE141 Timing Issues54

Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityyy

Vo1 Vi2o1

Vi1 Vo2Vo1 = Vi 2Vi1

A

Vo2

A

C

Vi2 = Vo1

Vo2 = Vi 1 B

Vi1 = Vo2

EE141 Timing Issues55

MetaMeta--StabilityStabilityyy

A

o1

A

o1

Vi2

5V

o

Vi2

5V

o

C C

B

V 5 V

B

V 5 V

Gain should be larger than 1 in the transition regiond Vi1 5 Vo2 d Vi1 5 Vo2

EE141 Timing Issues56

Overpowering the Feedback Loop ─Overpowering the Feedback Loop ─CC C l d P iC l d P iCrossCross--Coupled PairsCoupled Pairs

NOR b d NOR-based set-reset

S QQRS Q

S

R

QQ

Q

Q00 Q

101 0

010 1R Q

Forbidden State

010 1011 0

EE141 Timing Issues57

SchematicSchematic-- clocked NOR basedclocked NOR basedSchematicSchematic clocked NOR basedclocked NOR basedAdded clock Simple pull up but

ratioing of devices

VDD

grequired

QRS Q

M2 M4

QQ

Q00 Q

101 0

010 1

M1 M3M6CLK M8 CLK

Forbidden State

011 0

M5S M7 R

EE141 Timing Issues58

CrossCross--Coupled NANDCoupled NAND

Cross-coupled NANDs

SQ

Cross coupled NANDs

QRS Q

Q

Q Q

Q11 Q

110 0QR

Forbidden State

001 1100 1

EE141 Timing Issues59

Sizing IssuesSizing Issuesgg2.0 3

Q S

1.0

1.5

Volts

) 2

Volts

W 0 7W = 0.6 m

W = 0.5 m

0.5

1.0

Q (V

1

Vo

W = 0.9 mW = 0.8 m

W = 0.7 m

4.03.53.0W/L5 and 6

2.52.00.0

time (ns)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

0W = 1 m

W 0.9 m

Output voltage dependence t i t idth

Transient response

(a) (b)

EE141 Timing Issues60

on transistor width

OTHER LATCH DESIGNS OTHER LATCH DESIGNS SELF ANALYSISSELF ANALYSISOTHER LATCH DESIGNS OTHER LATCH DESIGNS SELF ANALYSISSELF ANALYSIS

EE141 Timing Issues61

EE141 Timing Issues62

EE141 Timing Issues63

EE141 Timing Issues64

EE141 Timing Issues65

PipeliningPipeliningp gp gEGa EGa

REEG

REGlog

a

CLK

CLK

Out

b

REEG

REGlog

a

CLK

CLK

REG

CLK

REG

CLK

Out

b

RE

CLK

CLKb RE

CLK

CLKCLKCLKb

R f PipelinedReference Pipelined

EE141 Timing Issues66

Minimum clock periodMinimum clock periodMinimum clock periodMinimum clock period

EE141 Timing Issues67

LatchLatch--Based PipelineBased PipelineLatchLatch Based PipelineBased PipelineCLK CLKCLK

F GIn Out

C C CC1 C2 C3

CLK

CLK

C t F t G

EE141 Timing Issues68

Compute F compute G

CC22mos pipelinemos pipelineCC mos pipelinemos pipeline

EE141 Timing Issues69

Race in 0Race in 0--0 overlap0 overlapRace in 0Race in 0 0 overlap0 overlap

EE141 Timing Issues70

NONO--Race NP CMOS pipelineRace NP CMOS pipelineNONO Race NP CMOS pipelineRace NP CMOS pipeline

EE141 Timing Issues71

NoNo--RACE NP CMOS pipelineRACE NP CMOS pipelineNoNo RACE NP CMOS pipelineRACE NP CMOS pipeline

EE141 Timing Issues72