safe machine parameters - tester smp tester hardware short historic version 1 - labview tester
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Stéphane Gabourin 29th March 2012
The Safe Machine ParametersTester
CERN, the LHC and Machine Protection 2 of 26
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
Plan
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
CERN, the LHC and Machine Protection
DATA RECEIVERMachineEnergy LHC
Safe Machine
ParameterController
DATA RECEIVERBeam Intensity
Beam Mode
LHC Beam Presence Flag 1
LHC Set-up Beam Flag 2LHC Set-up Beam Flag 1
LHC Beam Intensity 1LHC Machine Energy
LHC Beam Intensity 2Moveable Devices Allowed In
Stable Beams FlagSqueezing Factor 1/2/5/8DATA RECEIVERBeam
Presence
Squeezing Factors
LHC GeneralMachineTiming
LHC Beam Presence Flag 2LHC Beam Presence Flag 1
LHC Set-up Beam Flag 2LHC Set-up Beam Flag 1
LHC Beam Presence Flag 2
MachineEnergy
SPSSafe
MachineParameterController
DATA RECEIVERBeam Intensity
SPS Set-up Beam Flag
LHC Cycle FlagCNGS Cycle Flag
SPS Probe Beam Flag
SPS GeneralMachineTiming
Directly Transmitted
Broadcast
HiRadMat Cycle Flag
3 of 26
SMP reminder
I. SMP Tester Hardware
FramesFlags
CERN, the LHC and Machine Protection
Electronic boardElectronic board
4 of 26
Notions (1): Frames and flags
I. SMP Tester Hardware
Manchester Encoder Manchester Decoder
≈ 100us
32 b
its
ME MD
Frames transmission
Flags transmission
Electronic board Electronic board
< 1us
1 0 1 0 1 1 0 1 0 0 1
0 or 11 bit
CERN, the LHC and Machine Protection 5 of 26
Notions (2): FPGA memories
I. SMP Tester Hardware
32 bitsRegisters
History buffer (HB)
UTC Time MONITOR CONTROL Event Event Event EventSeconds Microseconds Status Status Visibility Type Sub-type Details32-bits 20-bits 12-bits 16-bits 2-bits 6-bits 8-bits 32-bitsDW0 DW1 DW2 DW3
128 bits
1024 records
CISR A
CISR B
CISGL A
CISGL B
CISA
SMPC
HW tester simulation
GMT
CISVCISC
CIBU LHCBIS
CERN, the LHC and Machine Protection 6 of 26
5 CISTR2 CISTCL1 CISTA
I. SMP Tester Hardware
BETS
DCCTEn, Int
CIBFU CIBFCCIBFU CIBFC
CIBFU CIBFCCIBFU CIBFC
CIBFU CIBFCCIBFU CIBFC
BCTs
BEMs
BPF
CIBFU CIBFCCIBFU CIBFC
CIBFU CIBFCCIBFU CIBFC
SPS ExtBIS
BPFSBF
Electrical-differential RS485Current loopsOptical
Manchester encoded framesFlags
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HW tester connections
I. SMP Tester Hardware
C I S C
CERN, the LHC and Machine Protection 8 of 26
Plan
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
Historic
CERN, the LHC and Machine Protection 9 of 26 II. Short historic
DevelopmentsVersion 1: until August 2011Version 2: from May to October 2011Version 3: from November 2011 (to May 2012?)
CERN, the LHC and Machine Protection 10 of 26
Plan
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
CERN, the LHC and Machine Protection 11 of 26
Version 1: Layers overview
III. Version 1 - LabVIEW tester
Excel
LabVIEW
FESA
VME boards
FESA vi
PowerPC (FESA drivers)
Electronic cards
Ethernet communication
FESA dll
SMPC Tester
LabExcel
Command Results
CERN, the LHC and Machine Protection
FESA vi
PowerPC (FESA drivers)
Electronic cards
Ethernetcommunication
FESA dll
SMPC Tester
LabExcel
Command Results
12 of 26
Version 1: Test steps
III. Version 1 - LabVIEW tester
FESA vi
PowerPC (FESA drivers)
Electronic cards
Ethernet communication
FESA dll
SMPC Tester
LabExcel
Command Results
VME bus
Main limitation:
New test => New LabVIEW code !
CERN, the LHC and Machine Protection 13 of 26
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
Plan
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
IV. Version 2 - Generic test and virtual SMPCCERN, the LHC and Machine Protection 14 of 26
Version 2: Brain stormingGoal 1: Add/modify tests out of LabVIEW => Tests defined in Excel
A test Operations to perform
Goal 2: Separate the test operations of the test validation
SMP controllerTest program
Expected behavior calculation
Generate inputs from Excel command
= Test successYes
Set
Get
Wait
Þ Simulates at every time (ms granularity):- The output signals- The internal memory (only registers)
How many possible operations? => 7
=> Birth of the Virtual SMP controller
SMP controllerTest program
Expected behavior calculation
Generate inputs from Excel command
= Test successYes
CERN, the LHC and Machine Protection 15 of 26
Version 2: Code overview
IV. Version 2 - Generic test and virtual SMPC
CERN, the LHC and Machine Protection 16 of 26
Version 2: User’s interfaceCtrl + Click Ctrl + Shift + ClickShift + Click
IV. Version 2 - Generic test and virtual SMPC
CERN, the LHC and Machine Protection 17 of 26
Version 2: Limitations
- Maintain the Virtual SMPC code (not really an issue)- Implementation of the History Buffer behavior- Very slow: 1Hz(FESA subscription / FESA refresh)
IV. Version 2 - Generic test and virtual SMPC
total time 120 tests:- SMPC = 6h 40m- VSMPC = 1h 20m
1. Formal Methods ?- CISR model- CISGL too complex
CISR input headers
BPF
Energy priority
2. Accelerate FESA refresh at 10Hz? => PowerPC overloaded…
CERN, the LHC and Machine Protection 18 of 26
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
Plan
Safe Machine Parameters - Tester
I. SMP Tester Hardware
II. Short Historic
III. Version 1 - LabVIEW tester
IV. Version 2 - Generic test and virtual SMPC
V. Version 3 - Need for speed
CERN, the LHC and Machine Protection 19 of 26
Version 3: Requirement
- The virtual SMP has to be removed (cannot be faster) => Expected values for registers and HB have to be in Excel
- FESA must be replaced => Nodal? Too basic, old, no support… => c code implementation !
V. Version 3 - Need for speed
Excel
LabVIEW
VME boards
FESA vi
PowerPC (FESA drivers)
Electronic cards
Ethernet communication
FESA dll
SMPC Tester
LabExcel
Command Results
PowerPC (c server)
Ethernet(TCP protocol)
C dll
Developped under Visual Studio
Socket implementation (with Jean-Christophe’s help)
- c function to access boards memories (provided by Ben)- .h libraries search (J-C’s help)
FESAServer client
CERN, the LHC and Machine Protection 20 of 26
Version 3: Timing Performances
V. Version 3 - Need for speed
Test protocol:- Read from LabVIEW a bloc of memory = (32*Nb registers read) bits
=> One 32-bits register read in 2 microseconds=> 1ms offset due to the socket connection
CERN, the LHC and Machine Protection 21 of 26
Version 3: Timing management
V. Version 3 - Need for speed
Each VME-crate has a server running → time synchronization neededHow to implement the Wait function?
Þ Use of c functions (rdtsc, usleep, nanosleep, …)? They are system dependant
Þ Use of the UTC time in the FPGA registers. 2 registers in each board:- UTC_SECOND : set by the tester through the socket- UTC_MICROSECOND : set to 0 each pulse on pps boards input (lemo cable, few nanoseconds precision).
Wait (1000us)
1000us
t [us]0
2us
Read reg
1000
Timing error
Still subject to system interruptions! => Timing error generation
CERN, the LHC and Machine Protection 22 of 26
Version 3: Tests operations
V. Version 3 - Need for speed
Tester 2 (7 op):
-Send frame-Send flag
-Write register-Read register-Read signal-Read HB
-Wait
Tester 3 (9 op):
-Set frame-Set flag-Enable generators-Write register-Read register
-HB Start read-HB Get records-Wait-For: repeats a set of operations (reduce socket data transfer)
*HB interpretation:- Presence of record- Record data expected (energy value, control status…)- Time spent between specific records (CISR validity input)
Get info back:
ÞCompare with expected (Excel)
ÞHB interpretation*ÞGenerate timing error
Need forsynchronization
Only lastevents
CERN, the LHC and Machine Protection 23 of 26
Version 3: Example (CISR headers)
V. Version 3 - Need for speed
General Goal: Test the channel 1 energy input on CISRA of the LHC SMPC
HDR Energy CRC
8 bits = 2 hexa
32 bits
Valid header: x92
Specific goals (from specification):- Test all 256 headers and check the Valid flag (1 bit in a register) is true only for x92- Check the validity time is 7 times the energy frame period
Test steps:- Send each header once, period T=1000us between each frame- Check the valid flag is false for all except x92 (check done tc=200us after the frame sending)- Check the flag stays true 7*T=7000us
FALSE TRUEValid Flag
t [us]7*T
FALSE
tc
x93 x94 … xFF x00 … x91 x92TTT
1 input frame =
CERN, the LHC and Machine Protection 24 of 26
Version 3: Example (CISR headers)
V. Version 3 - Need for speed
x93 x94 … xFF x00 … x91 x92
FALSE TRUE
TTTt [us]
7*T
FALSEValid Flag
tc
12 to 13 min VS 0.3 seconds
Time spent: 5600 + 200 + 1000*255 + 7000 = 267 800 us
CERN, the LHC and Machine Protection 25 of 26
Version 3: Limitations
None ?
V. Version 3 - Need for speed
CERN, the LHC and Machine Protection 26 of 26
Version 3: ToDo
V. Version 3 - Need for speed
Low level implementation (c):- History Buffer interpretation- Remove text file between LabVIEW and the c dll
Tests definition (Excel):- Re-define all tests (4/120 done). For both SPS and LHC- Add the CISC tests
High level language (LabVIEW, LabWindowsCVI, Java…):- Design the tests viewer- Develop a test builder
END !
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