séminaire cnes : les can pour les applications spatiales auto-test intégré des can y. bertrand,...
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Séminaire CNES : Les CAN pour les applications spatiales
Auto-Test Intégré des CAN
Y. Bertrand, F. Azaïs, S. Bernard, M. Comte et M.
Renovell
28 mai 2002, Toulouse
LIRMM : Laboratoire d’ Informatique,
de Robotique et de Microélectronique de Montpellier
2/21
Yves Bertrand
OutlineOutline
Introduction
Histogram-based BIST
BIST Implementation
Performance Evaluation
Conclusions
3/21
Yves Bertrand
IntroductionIntroduction
AnaloAnalogg
DigitalDigital
Mixed-Signal IC
Fault-Oriented Test• ATPG• DFT• BIST
Specification-Oriented Test
?
4/21
Yves Bertrand
IntroductionIntroduction
Ideal ADC
LSB = FS/2n
Analog input
Ideal Transfert Curve
111110101100011010001000D
igit
al ou
tpu
t
VT1 VT2 VT3 VT4 VT5 VT6 VT7 FS
5/21
Yves Bertrand
IntroductionIntroduction
ADC ParametersADC Parameters
Offset Error Gain Error
111
110
101
100
011
010
001
000
Analog input
Dig
ital ou
tpu
tN-Linearity Errors
Analog input
111
110
101
100
011
010
001
000
Dig
ital ou
tpu
t
INL
DNL
111
110
101
100
011
010
001
000
Analog input
Dig
ital ou
tpu
t
Ideal
Offset
Gain
6/21
Yves Bertrand
Histogram-based BISTHistogram-based BIST
Histogram-based Test
Histogram
H(i)
ou
tpu
t co
de
Analog input
Tim
e
2A
VT3 FS000001010011100101110111
7/21
Yves Bertrand
ADCADC
AnalogWaveformGenerator
Analog
Input
ADCParamete
rs
Histogram-based BISTHistogram-based BIST
Histogram-based BIST Architecture
DigitalOutputn bits
Detector Module Control Unit
2n Memory Words
(Measured Histo.)
2n Memory Words
(Ideal Histo.)
DSP
or
-Processor
Exploitation module
8/21
Yves Bertrand
Linear Histogram
Hideal
Hextreme
2 Memory Wordsfor the storage of the Ideal
Histogram
Histogram-based BISTHistogram-based BIST
Sinusoidal Histogram
Choice of the Input Waveform
Non-Uniform Distribution
2n Memory Wordsfor the storage of the Ideal
Histogram
H(i)
Uniform Distribution
A
FSisin
A
FSisin
N)i(H
n
n
n
n
nT
ideal 2222
222
211
A
FS
2
N)i(H
nT
ideal
9/21
Yves Bertrand
Histogram-based BISTHistogram-based BIST
Parameter Evaluation
Hideal
Hextreme
Offsetn
idealH2
)1(H)2(H
Code i
Code Count H(i)
Division by constantAddition Subtraction
Code 1 Code 2n
m Codes
Division by constantAddition Subtraction
Gain-1 idealm.H
)i(HN2
N1
INL (i) i
j=1
DNL (j)
DNL (i)idealH
)i(H idealH
Gain-1 idealm.H
)i(HN2
N1
Division by constantAddition Subtraction
10/21
Yves Bertrand
Histogram-based BISTHistogram-based BIST
Time Decomposition Technique
1 Memory Wordfor the storage of the Measured
Histogram
Code 1 Processing
Code 2n Processing
Code N1 Processing
Code N2 Processing
Code 1 Processing
Code 22nn Processing
Code 1 Processing
Code 2n Processing
...
....
....
Step 1:
Step 2:
Step 1:
Step m:
Step 1:
Step 2n:
Step 1:
Step 2n:
...
....
....
Phase 1:
Phase 2:
Phase 3:
Phase 4:
TIM
E
Offset Calculation
Gain Calculation
DNL Calculation
INL Calculation
Reusable test resources
11/21
Yves Bertrand
ADCADC
TriangleWave
Generator
AnalogInput
ADCADCParameterParameter
ss
Histogram-based BISTHistogram-based BIST
Optimized BIST Architecture
DigitalOutputn bits
Detector Module Control Unit
2 Memory Words
(Ideal Histo.)
1 Memory Word
(Measured Histo.)
Elementary
Operators
-
Exploitation module
12/21
Yves Bertrand
BIST ImplementationBIST Implementation
Optimized BIST Architecture
Detector Module
2 Memory Words
(Ideal Histo.)
1 Memory Word
(Measured Histo.)
Elementary Operators
-
Exploitation module
ADC Output DigitalOutput
n bits
Control Unit
Exploitation module
Control Unit Detector Mod.
13/21
Yves Bertrand
BIST ImplementationBIST Implementation
Generation of the Reference Code
Comparison of this Code with the ADC
Output
Detector Module
Counter ComparatorCounter Comparator
Exploitation module
Control Unit Detector Mod.
14/21
Yves Bertrand
BIST ImplementationBIST Implementation
Detector Module
ADC_Out [i+1]
DM_SetDM_Clear
Next_Code
Control
Comparator_Out
O1[i+1]
O2[i+1] 1-bit block
[ i+1]
O1[i-2]
O2[i-2]
ADC_Out [i-1]
1-bit block
[ i-1]
ADC_Out [i]
1-bit block
[ i]
Number of 1-bit blocks = NbitsExploitation module
Control Unit Detector Mod.
15/21
Yves Bertrand
BIST ImplementationBIST Implementation
Exploitation module
Exploitation module
Control Unit Detector Mod Up / Down Counter
Adder
1 Memory Word
(Measured Histo.) H(i)
Counterif code = i then R = R + 1
Subtractor
H(2n)-H(1)
if code = 1 then R = R + 1if code = 2n then R = R + 1
Up/Down Counter-
Divider
2 Memory Words
(Ideal Histo.)1
m.HIdeal
HIdeal = 2P & m = 2Z (P+Z)-bit shift
16/21
Yves Bertrand
BIST ImplementationBIST Implementation
Exploitation module
EM_Clear
Ext_Clock
c2c1
S1[i+1]
S2[i+1]
EM_Out[i+1]
[ i+1]
1-bit block
EM_Out[i]
[ i+1]
1-bit block
S1[i-2]
S2[i-2]
EM_Out[i-1]
[ i+1]
1-bit block
Number of blocks = F(Gain,DNL)Exploitation module
Control Unit Detector Mod.
17/21
Yves Bertrand
BIST ImplementationBIST Implementation
Control Unit
Library IEEE;
use IEEE.std_logic_1164.all
entity Contol_Unit is
port(ck,startS,endS,In0: in std_logic;
c1,c2,clr_DM : Out std_logic);
end Control_Unit
architecture ArchControl of Control_Unit is
type state is (Ini_Etat, o1,o2,o3,o4,o5,o6,o9);
signal nextEtat, presEtat: state;
begin
control : process (presEtat, startS,endS,In0)
begin
nextEtat <= presEtat
case (presEtat) is
...
VHDL
Synopsys
Exploitation module
Control Unit Detector Mod.
[ i+1]
18/21
Yves Bertrand
Performance EvaluationPerformance Evaluation
Example of BIST Structure
Number of bits : 6
Exploitation
HIdeal=25 & m=24
EM_Out[i]
[ i+1]
1-bit block
10 x
Exploitation module
Control unit
VHDL
Control Unit
ADC_Out [i]
1-bit block
[ i]
6 xDetector
Nbits
Detector Mod.
DNL DNL = 0.03 LSB= 0.03 LSB
GainGain = 0.05 LSB= 0.05 LSB
19/21
Yves Bertrand
Performance EvaluationPerformance Evaluation
AMS0.8u
Example of BIST Structure
Area
FLASH6 3.3 mm2100MS/sec 6 bits
BIST 0.22 mm2
Relative area : 7 %<6 bits
20/21
Yves Bertrand
Performances & DiscussionPerformances & Discussion
Limitation
6
8
10
12
14
Number of bits
TEST TIME
300ms
5s
1mn 15s
20mn
5h 22mn
Fs=1MHz
30ms
500ms
7.5s
2mn
32mn
Fs=10MHz
6ms
100ms
1.5s
24s
6mn
Fs=50MHz
3ms
50ms
750ms
12s
3mn
Fs=100MHzn
Trade-off Time-to-area
21/21
Yves Bertrand
Conclusion & FutureConclusion & Future
High Level Structure Linear Histogram
Simplification of the computations
Time Decomposition
Low Level Implementation Detector Module = Counter
Exploitation Module = Up/Down Counter
Small Control Unit
Integrating Histogram-based Test ?
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