sequential circuits - utep · 2013-03-10 · sequential element review! sequential elements provide...
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Sequential Circuits
Prof. MacDonald
Sequential Element Review l Sequential elements provide memory for circuits
– heart of a state machine – saving current state – used to hold or pipe data – data registers, shift registers
l Two varieties – level sensitive transparent latch – less common – edge sensitive master-slave flip-flop – everywhere
General Sequential Circuit
combinational circuits
inputs outputs
state next state 4 flip flops
General Sequential Circuit – cone of logic
D FF
D FF
D FF Chip Input
D Latch Schematic
gate
d
gateN
gateN
q
D Latch Schematic - better
gate
d q
CMOS Tri-state Inverter
~en
en
input output
D Latch Operation
time
Q
G
D
l Gate Low – Q holds value and ignores D l Gate High – transparent – Q follows D after delay
D Latch Common Uses
time
Q
G
D
Most common – basic building block of Flip-Flop Other uses – to condition enable for clock gating
Standard CMOS D Flip-Flop Diagram
D Latch
D G
Q
D Latch
D G
Q
D
Q
CLK
Two doors – never simultaneously open or closed. Q is never directly influenced by D.
D Flip-Flop Schematic
D
CLK
Q
D Flip-Flop Operation
time
Q
CLK
D
Sample input at edge and launch to output. Input must be good for “setup time” before and “hold time” after the edge to sample correctly – sampling window.
Tsu
Th
Tlaunch
D Flip-Flop Set-up Times The time before the rising edge during which the data must
be stable to be sampled correctly. Logic designers can slow the clock (bigger period) to
alleviate setup problems – but less performance. A good Flip-Flop design will have a very short set-up time.
Q
D Flip-Flop Set-up Times Data must make it to net A before clock switches the
tri-states in first latch. Need to understand the delay of the clock to the first latch
versus the delay of the data.
Q
net A
D Flip-Flop Set-up Times Adding logic in the data path increases set-ups and
therefore decreases performance. Muxes often added for either functional or test purposes.
Q
net A
d0 d1 sel clk
D Flip-Flop Hold Times Hold times describe how long the data must be stable after the rising edge. Often the hold time is zero. Although hold times do not affect frequency, if you fail to
meet them, your chip will not work and slowing it down will not help.
Q
D Flip-Flop Launch Times Time required for data at input to be sampled and launched
from the input. This adds to the time it requires to start through the cone of
logic and get to the next flip-flop therefore increases period of clock and slows performance.
Q
General Sequential Circuit – cone of logic
D FF
D FF
D FF
D FF
Tsu=1ns Tp=1ns Tp=2ns
Tp=2ns
Tlaunch=1ns
Tp=0.5ns
Tlaunch=1ns
Tlaunch=1ns
How fast can this logic run?
Alternative Designs Pulsed Latch – faster but less robust Latches not good for sequential elements due to race condition when transparent. Make a glitch enable at rising edge and can get away with a latch.
D
CLK
delay
Alternative Designs
time
Q
CLK
D
Meta-stability
time
CLK
D
Common logic or circuit design interview question. If input is asynchronous, then it is possible for input to
change exactly at rising edge and latch a middle value. This is called the meta-stable point and results in
indeterminate operation and high static power consumption.
Meta-stability
VoutA VinB
VinA VoutB
meta-stable point – theoretically possible to be stable here
Meta-stability
D FF D FF
asynch signal from different clock domain or outside world
synchronized version of signal
Many standard cell libraries claim to have meta-stable hardened sequential elements where double-registering them is not necessary. How? Change in the design? Is new technology more or less susceptible to meta-stability?
Flip-Flop Design Guidelines l Need narrow sampling window
– small setup time requirement – small hold time requirements
l Need fast launch time l Minimize the clock loading to minimize power
– clock is most active net on chip and more load = more Pd
l Buffer all inputs so internal signals are cleaner l Need good drive output to drive higher fanout l 100k-1M flip-flops on a typical design
– smaller is better – transistor counts can vary from 15-40.
Half Latch Flip Flop
clk
C – HLFF
D
clk
clk
clki
D clki
clki
Q
Qb
2.0
4.0
4.0
8.0
0.125 0.1254.0
8.0
8.0
10.0clk
C – HLFF
D
clk
clk
clki
D clki
clki
Q
Qb
2.0
4.0
4.0
8.0
0.125 0.1254.0
8.0
8.0
10.0
Sense Amp Flip Flop
4.0 4.0
2.0
2.0
2.0
Q QB
D DB
Clk
D- SAFF
4.0 4.0
2.0
2.0
Dynamic D Flip Flop
4.0
4.0
1.0
clk
clk
2.0 clk
X D
N
2.0
2.0
clk 2.0
Q Qb
0.5 Q
F - Dynamic D Flip Flop with Keepers
2.0
0.5
2
0.5
Rad-hard Latch
2.0
1.0
1.0
0.5
2.0
1.0
4.0
1.0
1.0
4.0
2.0
1.0
1.0
2.0
2.0
1.0
1.0
2.0
Clki
Clk
D
Clk
Clki
Clk
Clki
Q
Qb
A – DICE (Single Latch)
2.02.0
1.01.0
1.01.0
0.50.5
2.02.0
1.01.0
4.04.0
1.01.0
1.01.0
4.04.0
2.02.0
1.01.0
1.01.0
2.02.0
2.02.0
1.01.0
1.01.0
2.02.0
Clki
Clk
D
Clk
Clki
Clk
Clki
Q
Qb
A – DICE (Single Latch)
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