sigma delta 1.3
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SIGMAIGMA-DELTA MODULATORSELTA MODULATORSIGMAIGMA DELTA MODULATORSELTA MODULATORSDESIGN ISSUESESIGN ISSUESJose Silva-Martinez
Electrical and computer Engineering
(Amesp02.tamu.edu/~jsilva)
J. Silva-Martinez 1
Part 1.3
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Conventional (Conventional (NyquistNyquist) ADC) ADC
J. Silva-Martinez 2
. .. .
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Basic concept inBasic concept in ModulatorsModulatorsVin
1
H(s) A/D
Data
Out
DACs
sF
)s(HSTF NTF
1
J. Silva-Martinez 3
)s(H1 )s(H1
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FirstFirst--OrderOrder ModulatorModulatorw scre ew scre e-- me n egra orme n egra or
The modulators order is defined as the loop filter order
Number of bits is the bit number of the quantizer and DAC.
-
z-1
integrator
digital output
Y(n)
analog input
xc(t)
DAC
If the integrator changes to a continuous-time integrator, with the- -
J. Silva-Martinez 4
delta modulator.
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Waveforms with 0 V DC InputWaveforms with 0 V DC Input1
1.5
0
0.5
ltage
-1
-0.5
v
0 5 10 15 20 25 30 35 40 45 50-1.5
sample #
he out ut codes oscillate between 1 and -1.
CT integrator output
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Waveforms with 1/7 V DC InputWaveforms with 1/7 V DC Input
1
1.5
oltage
0
0.5
-1
-0.5
sample #0 5 10 15 20 25 30 35 40 45 50
-1.5
The output code period is 7, the sequence is [ -1, 1, -1, 1, -1, 1, 1].
CT integrator output
J. Silva-Martinez 6
Average value of the sequence is 1/7.
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Waveforms with 2/7 V DC InputWaveforms with 2/7 V DC Input
1
1.5
oltage
0
0.5
-1
-0.5
sample #0 5 10 15 20 25 30 35 40 45 50
-1.5
The output code period is 14, the sequence is [ -1, 1, 1, -1, 1, 1, -- -
CT integrator output
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, , , , , , .
Average value of the sequence is 2/7.
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Waveforms with 3/7 V DC InputWaveforms with 3/7 V DC Input
1
1.5
oltage
0
0.5
-1
-0.5
sample #0 5 10 15 20 25 30 35 40 45 50
-1.5
The output code period is 7, the sequence is [ -1, 1, 1, -1, 1, 1, 1].
CT integrator output
J. Silva-Martinez 8
Average value of the sequence is 3/7.
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Waveforms with 4/7 V DC InputWaveforms with 4/7 V DC Input
1.5
oltage
0
0.5
1
-1
-0.5
sample #0 5 10 15 20 25 30 35 40 45 50
-1.5
The output code period is 14, the sequence is [ -1, 1, 1, 1, -1, 1, 1,
CT integrator output
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, , - , , , , .
Average value of the sequence is 4/7.
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LinearizedLinearized DiscreteDiscrete--Time ModelTime Model
1
1z1H(z)
zEzYzXzHzY DelayzzYSTF
:FunctionTransferSignal
1
zE
zH1
1zX
zH1
zHzY
:FunctionTransferNoise
zEz1zXzzY
HPz1zENTF
J. Silva-Martinez 10
Caveat: E(z) may be correlated with X(z) not white.
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11stst
--Order Noise ShapingOrder Noise Shaping
f
2
Ne2
2
12 1
fs 2 0
fm
NTF2
df
2 fm 2
fs
f
fsfm
12
fs 2
2sin fs
0
df
2
1 f fm
2
12 fs 2 fs 0
2
12
2fmf
3
2
3
222
:noiseonquantizatiband-In
33OSR12
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. .
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22ndnd
--OrderOrder ModulatorModulator
2zSTF
:FunctionTransferSignal
In - band quantization noise :
2 4
NTF 1 z1 2
Ne2 12 5M5
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Doubling OSR (M) increases SQNR by 15 dB (2.5 bit/oct).
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22ndnd--OrderOrder Modulator (1Modulator (1--BitBit QuantizerQuantizer))
1
2 jy
1
zE1z
zX1z
zY22
z-plane
Simple, stable, highly-linear
Insensitive to componentmismatch
0 1 x
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Less correlation b/t E(z) and X(z)
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Generalization (Generalization (LLthth--Order Noise Shaping)Order Noise Shaping)
Modulator transfer function:
Y z zLX z 1 z1 L
E z
2L2
:noiseonquantizatiband-In
12Le
O12L12
N
SR
2L
O12L
SRSQNR
N 212
2
3
, . .
Potential instability for 3rd- and higher-order single-loop modulators.
J. Silva-Martinez 14
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Feedback DAC
In DT modulators, the feedback DAC gives sampled.
However, in CT implementations, the DAC shouldprov e e oop er w a a.
DAC should convert the DT data into CT pulses.
Most common y use DA wave orms are rectangu arDAC pulses.
The can be easil enerated and loo filter
coefficients can be obtained in a straightforwardmanner.
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Feedback DAC
Typical DAC Rectangular Pulses
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DT andDT and CTCT EquivalenceEquivalence
Continuous timeDiscrete time
Vin
sT
1
H(s)
Vin
sT1
H(z)
DAC
s
|)()( txnx
nTt s
DAC
s
|)(*)()(
|)()()(
thtRnh
sHsRLzHZ
nTtD
nTtD
s
s
Open loop impulse response is equal at t=nTs
D
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Equivalence of ContinuousEquivalence of Continuous--Time & DiscreteTime & Discrete--TimeTime
The key feature of the modulator is the noise shaping (NTF)
To achieve equivalence between a continuous-time and discrete-timeimplementations, Loop Gain should have the same properties
-discrete-time loop filters ?
The NTF is mainly determined by the transfer function of theThe NTF is mainly determined by the transfer function of the
J. Silva-Martinez 18
oop ter an t e ee acoop ter an t e ee ac
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Impulse Invariant TransformationImpulse Invariant Transformation
DT (Z-domain) loop filter into partial fractions and use S-domain
e uivalences for the Z-domain oles to et the CT loo filter.
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Inherent AntiInherent Anti--aliasing for narrowaliasing for narrow--bandband
app ca onsapp ca ons
According to impulse invariant, the above two loopsare equivalent, L(z) = 1 / (1 + H(z)) !
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Inherent AntiInherent Anti--aliasingaliasing
For CT case
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Inherent AntiInherent Anti--aliasingaliasing
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Continuous Time vs. Discrete TimeContinuous Time vs. Discrete Time
Continuous Time Discrete Time
Not drastically limited by Limited by GBW of loopamplifiers GBW filter amplifiers
Power ConsumptionLower (No high GBW required!)
Higher
Anti-aliasing-
applications
ADC
Sampling Errors Shaped by loop filter
Appear directly at ADC
output
Clock JitterSensitive to clock jitter infeedback DAC
Robust to Clock Jitter
Loop DelayModify the loop filter poles
Very little effect
Rise-Fall Time AsymmetryYield even order harmonics inthe DAC feedback signal
Very little effect
Sensitivit to Process Absolute RC or Gm C values Ca acitance ratios can be as
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variations can vary by 30 % accurate as 0.5%
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Continuous-time ADC
Key Features ower power consump on
Inherent anti-alias filtering
Lower area requirements
-
Easier to drive from external sources
Sensitive to DAC clock-jitter and non-linearity
Sensitive to excess loop delay
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Sensitive to time-constant variations
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CTCT ADC NonADC Non--idealitiesidealitiesDAC Non-idealities
Excess loop delay : Constant delay between ideal and implemented
DAC feedback pulse Decision time required by quantizer affecting latches used for
Finite response time of DAC to its clock and inputs
Excess Loop Delay can be incorporated: Z
-1Z
-1+
Inter-symbol interference : Finite slew rate of DAC outputs with
unequal rise and fall times
Clock jitter in DACProcessed by STF
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DAC and Filter Non-linearityNot noise-shaped
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Design Example: 12Design Example: 12--bit, 20MHz CTbit, 20MHz CT ADCADCSystem-level Design Considerations
Design Trade-offs:
Order of modulator, L L Reduced stability, Less robust to PVT variations
Oversampling ratio, OSR OSR Limited by fT of technologyQuantizer resolution, N N Improved stability
Improved clock jitter tolerance More power, area in quantizer
-feedback DAC
Max. NTF gain, NTFmax NTFmax Reduced stability
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Max. stable amplitude, MSA MSA L, N, NTFmax
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SystemSystem--level Optimizationlevel Optimization
Peak SQNR vs NTFmax
, No. of Quantizer levels
,settling time requirements on 1st integrator stage
L = 5, OSR = 10
88
90
Order of modulator (L),
and OSR set by targetSQNR (~80dB)
82
84
86
NR
(dB)
L = 5, OSR = 10
A number of tradeoffs
76
78
80
PeakS
Just pickingJust picking
9
10
113.5
472
74
good approachgood approach
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7
82.5
No. of Quantizer levelsNTFmax
GUESSES!GUESSES!
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SystemSystem--level Optimizationlevel Optimization
L = 5, OSR = 10, N = 9Order of modulator
(L), and OSR set by
tar et S NR ~80dB
82
84
86
High-Q filters give
76
78
80
kS
QNR(dB)
(due to picking in
the gain; better in-
band noise
70
72
74Pe
Implications onImplications on
4
6
8
2
4
6
868er s s gnaer s s gnaswing and outswing and out--
ofof--band noise?band noise?
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00Q
2(
0= 10.8MHz)Q1 (0 = 18.1MHz)
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SystemSystem--level Optimizationlevel Optimizationvs max, o. o uan zer eve s
Maximum Signal
Amplitude Increase
with number of levels
-1.5
-1
and with small NTF
values
-3
-2.5
-
SA
(dB)SeveralSeveral
tradeoffstradeoffs
-4.5
-4
-3.5nvo venvo ve
8
9
10
11
2.5
3
3.5
-5
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7 4NTF
max
No. of Quantizer levels
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SystemSystem--level Optimizationlevel Optimization
NTF vs Bi uad ualit Factorsmax L = 5, OSR = 10, N = 9
HighHigh--Q sectionsQ sections
is synonymous ofis synonymous of
hi her hi her NTFmaxNTFmax
3.6
3.8
and better inand better in--
band NTFband NTF
3.2
3.4
N
TF
maxHowever, MSAHowever, MSA
decreases,decreases,
2.8
3en sen s
unclear if yourunclear if your
SQNR is betterSQNR is better
2
4
6
8
2
4
6or notor not
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00Q
2(
0= 10.8MHz)
Q1
(0
= 18.1MHz)
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AvoidAvoid SaturationSaturation atat internalinternal nodesnodes andand quantizerquantizerinputinput;; checkcheck signalsignal swingswing everywhereeverywhere::
TheseThese simulationssimulations mustmust includeinclude inin--bandband andand outout--ofof--bandband inputinputsignalssignals toto emulateemulate realreal ADCADC operationoperation inin presencepresence ofof blockersblockers
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Selected System Parameters
10
NTF Magnitude Response
-10
0
NTFmax
= 3.431 Parameter Value
Sampling Frequency 400MHz
-30
-20
de
(dB)(dB)
Signal Bandwidth 20MHz
Order 5
-50
-40Magnit
Quantizer levels 9
Peak SQNR 80dB
-60
max .
MSA -3dBFS
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10-3
10-2
10-1
100
-
Normalized Frequency (rad/sec)
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Implementation DecisionsImplementation Decisions
Loop filter
-
gm-C type for other two. Or, you may use 3 active-RC type integrators.
uan zer
5-bit flash type,
Proper sizing of the comparator transistors is necessary to ensurea small enough offset.
DAC
Current steering is chosen for straightforward implementation,
Current calibration is utilized to linearize the DAC. Pulse shaping
J. Silva-Martinez 34
compared.
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Loop Filter Design ConsiderationsLoop Filter Design Considerations -- 11
Low powerdue to lower internal
signal swings
High gain in 1st stage of filter
Relaxed noise and linearity
specs on later stages Reduced complexity: Only one DAC
s or er an -a as ng
Out-of-band peaking in STF
Reduced stable input range for
adjacent channels
Higher power consumption due to
larger internal signal swings
Moderate ain in 1st sta e of
filter Higher bias currents in later
stages to reduce noise and non-
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Multiple DACs
Lth - order anti-aliasing
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CTCT ADC NonADC Non--idealitiesidealitiesInput locations for non-idealities in a CT ADC
Most critical
Quantizer Non-idealities
DC offset, non-linearity are noise-shaped by the loop
-,
Filter Non-idealities
Finite op-amp GBW product causes incomplete settling of integrator outputs
Finite slew rate and output swing introduce non-linearity
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Circuit noise and non-linearity of 1st integrator
Integrator time constant variation may cause instability
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Broadband ADC Architecture: 3Broadband ADC Architecture: 3rdrd order LPorder LP
k4
k5
k6kz
quantizer
k1Ts/s k2Ts/s k3Ts/s
Integrator_1Integrator_2 Integrator_3
fb2
kfb1
z-1
DAC
z-1/2
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A broadband continuous-time sigma-delta modulator architecture Blockers tolerant ?
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Loop Filter Design ConsiderationsLoop Filter Design Considerations -- 22
AC1
AC3
Block Order DC Gain Cut-off Q IM3 SNR
BIQUAD1 2 20 18.4 3 -78 74
BIQUAD2 2 20 10.8 4 -60 60
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. - -
Filter 5 59 20 - < -76 72
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System ArchitectureSystem Architecture
- -
Feed-forward architecture
9-level quantizer-
High linearity Low power, area, less complexity
Realizability
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o eran o c oc er
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Loop Filter Design ConsiderationsLoop Filter Design Considerations -- 22
60
70
)
Loop filter H(s) : Bode Diagram
20
30
40
Magnitude(d
106
107
108
0
10
-100
-50
0
(deg)
-250
-200
-
Pha
se
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106
107
108
-
Frequency (Hz)
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Loop FilterLoop Filter
Active-RC
Higher linearity (+)RZ CI
Rail-to-rail signal swing (+)
Slower speed (-)
-
RIN
In Outwith higher power consumption (-) RIN
gm-C
Higher bandwidth (+)
Poor linearit -CI
Smaller signal swing (-) Parasitic sensitive (-) CI
In Outgm
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Local calibrations: Loop Filter RCLocal calibrations: Loop Filter RC
To overcome large ( > 10% ) RC product variation, automatic tuning
RZ CI
RIN
In Out
RZ CI
RIN
4 bitcontrolword
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RC Time Constant VariationsRC Time Constant Variations
96
RC time constant variation may hurt stability and SNR of theRC time constant variation may hurt stability and SNR of themodulatormodulator
92
94
Unstable10% RC productaccuracy could
88
90
N
R
(dB)
Stable operation
sa s y our nee s
84
86S
80
82
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0.8 1 1.2 1.4 1.6 1.8 278
Normalized RC time constant
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Loop Filter RC Time Constant TuningLoop Filter RC Time Constant Tuning
CI 4-bit control word
R
C
A(s)
Vref
Counter &AA
Vo
LogicAA
integratorcomparator
Vo
time
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BetterBetter to tune the loop gain (to be discussed)to tune the loop gain (to be discussed)
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Loop Filter Design ConsiderationsLoop Filter Design Considerations -- 33
Biquad section 1st order lossy integrator
Quality factors of biquadratic sections optimized
Lower Qs minimize sensitivity to saturation at internal nodes
Lower Qs suitable for practical realization
To suppress noise and distortion of later stages To minimize peaking in STF
BIQUAD1 has maximum bandwidth to suppress noise over a wider frequency range
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Overall input-referred noise designed to be limited by input resistance of loop filter
and 1st integrator
Excess phase in loop filter amplifiers critical to minimize excess loop delay
Oversampled A/D ConversionOversampled A/D Conversion
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Oversampled A/D ConversionOversampled A/D Conversion Specifications and Matlab/Verilog-A simulations Order and quantization levels Feedback, Feedforward, Mixed-mode
er rea za on Noise, Power, linearity
Quantizer (ADC) Input impedance, Kickback noise, Power consumption, Delay
DAC Speed, Jitter performance, Linearity, Output impedance
Clocks , System verification (Cadence)
SQNR, SJNR, SNR, SDNR, stability, loop delay Clocks
Calibration Cover PVT variations, mismatch, add non-linearities
Extensive post-layout Simulations
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Isolate as much as possible critical blocks from noisy digital.
Be careful with your assumptions; in many cases are not totally
true!
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T icalT ical uantizeruantizer:: FlashFlash ArchitectureArchitecture S/H operates at clock rate
Kick back noise
Re uires a recise low-
impedance resistive ladder:
Power-accuracy-Speed
tradeoff
Limited by comparator
Speed and accuracy
se vo age
Hard to improve its resolution
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State of the art:State of the art: ~ 2.4~ 2.4 GS/s 6 bits resolutionGS/s 6 bits resolution
Fl h B dFl h B d Q tiQ ti A hit tA hit t
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Flash BasedFlash Based QuantizerQuantizer ArchitectureArchitecture
Reference ladderVFS Vi Strobe
consists of 2N equal
size resistors
In ut is com ared
fs
to 2N-1 reference
voltages.
coder
Dout
Fastest ADC
architecture
En
a ency = = s
Throughput = fs
Complexity = 2N2
N-1
com arators
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Th t C dTh t C d
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Thermometer CodeThermometer Code
b2 b1 b0VFS Vi Strobe Thermometer code
1111
fs
0
01101
1
1010
1
1
000
2N-1 1-of-n code
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ROM encoder
M Off t R l tiM Off t R l ti
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Max. Offset vs. ResolutionMax. Offset vs. Resolution
DNL < .5 L B
s,
max
Large VFS relaxes
offset tolerance
Small VFS benefits
convers on spee
(settling, linearity)
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ADC Input CapacitanceADC Input Capacitance
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ADC Input CapacitanceADC Input Capacitance
22
00
2 /10 mfFCWL
AV g
VTT
N = 6 bits
V = 1V
63 comparators
1 LSB = 16mV
N (bits)# of
comp. Cin (pF)
= LSB/4
AVT0 = 10mVm
= 4mV
L = 0.24m,
.
8 255 250
10 1023 ??!=
SmallSmall VVosos leads to large device sizes, hence large area and power.leads to large device sizes, hence large area and power.
Large comparator leads to large input capacitance, difficult to drive andLarge comparator leads to large input capacitance, difficult to drive and
difficult to maintain bandwidth.difficult to maintain bandwidth.
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KickKick back noise and couplingback noise and coupling
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KickKick--back noise and couplingback noise and coupling
capac orscapac ors
M3 M4 M5 M6
Cgd1 Cgd2 Mode
M1 M2
VinCgs1 Cgs2
VRRS
M8M7
M9Vo
+Vo
- high Track
low Regen.
th 9 -
signal-dependent sampling point (aperture error)
A major challenge of distributing clock signals across 2N-1 comparators
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n as w t m n mum c oc s ew rout ng, th m smatc o 9
FullyFully Differential ArchitectureDifferential Architecture
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FullyFully--Differential ArchitectureDifferential Architecture
VFS doubled
3-dB gain in SNR
e er
Noise immunity
Input feedthroughder
cancelled
Cin nonlinearityEnc
Effect of Vcmi diff.mitigated
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55--bitbit QuantizerQuantizer Design (Flash ADC)Design (Flash ADC)
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55 bitbit QuantizerQuantizer Design (Flash ADC)Design (Flash ADC)
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5 bit5 bit quantizerquantizer schematic; looks a bit complex but it is a S/Hschematic; looks a bit complex but it is a S/H--FlashFlash
FullyFully--Differential ComparatorDifferential Comparator
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FullyFully--Differential ComparatorDifferential Comparator
Double-balanced, fully-differential preamp Switches (M7, M8) added to stop input propagation during regeneration
-
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DAC NonDAC Non idealitiesidealities
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DAC NonDAC Non--idealitiesidealities
Sources of jitter error Jitter errors in rectangular DACpulse
Pulse-width jitter: Random variation in charge fed back per clock cycle
- - -
quantization noise to in-band
Pulse-position jitter: Random variation in integration interval of constant charge
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Amplitude errors due to PP jitter are at least 1st-order noise-shaped
Ideal DAC TransferIdeal DAC Transfer CharacteristicsCharacteristics
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Ideal DAC TransferIdeal DAC Transfer CharacteristicsCharacteristics
out
FS
FS
000in
001 011 101010 100 110 111
DigitalDigital quantizerquantizer output to Analog Filter input converteroutput to Analog Filter input converter
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Diff ti l d I t l N li itDiff ti l d I t l N li it
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Differential and Inte ral NonlinearitDifferential and Inte ral Nonlinearit
out
DNL < -1 ?
FS
FS
i
000in
001 011 101010 100 110 111
jji
0
DNL = deviation of an output step from 1 LSB (= = VFS/2N)
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= ev a on o e ou pu rom e ea rans er c arac er s c
DNL and INLDNL and INL
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DNL and INLDNL and INL
Vout Vout
VFS
VFS-
VFS
VFS-
2 2
000Din
001 011 101010 100 110 111 000Din
001 011 101010 100 110 111
Smooth Noisy
DNL measures the incremental (local) nonlinearity.
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INL measures the cumulative (global) nonlinearity.
BinaryBinary--Weighted CR DACWeighted CR DAC
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yy gg
Cu = unit capacitance VoCP
VX
2C C C8C 4C
R
b3 b2 b1 b0
Binary-weighted capacitor array most efficientarchitecture
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R
Binary-Weighted CR DAC
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y g
NN
RN
1j
u
jN
up
1j
ujN
o V
C2CC
V
RN
N
1j
u
jN
jN
V
C2b
up
N
1jj
j-N
R
u
N
p
u
N
o2
bV
C2C
C2V
Cp gain error (nonlinearity if Cp is nonlinear) INL and DNL limited by capacitor array
J. Silva-Martinez 61
mismatc
Stray-Insensitive CR DAC
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Stray Insensitive CR DAC
N
1j j
j-N
R
uu1Np
u
N
u
N
o
2
bV
ACC2CC2
C2V
Large gain A
attenuatesumming-nodecharge sharing
J. Silva-Martinez 62
ResistorResistor--String DACString DAC
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gg
Ri
0 0 1 1
o
o
Simple, inherently monotonic good DNL performance
Complexity speed for large N, typically N 8 bits
J. Silva-Martinez 63
Has to be connected to a high impedance node
CodeCode--DependentDependent output impedanceoutput impedance
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VRDi
Vo
Co
RoSignal-dependent
RoC causes HD.
Ro of ladder varies with signal (code).
-
J. Silva-Martinez 64
.
RR--2R DAC2R DAC
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N
j-NbIRV
1j
X
o
3 2 1 0
A binary-weighted current DAC
Com onent s read reatl reduced 2:1
J. Silva-Martinez 65
BinaryBinary--Weighted CurrentWeighted Current SteeringSteering
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BinaryBinary Weighted CurrentWeighted Current SteeringSteering
DACDAC
Nj-Nb
IRV1j
.
Vo depends on Rout of current sources without op-amp. INL and DNL depend on matching, not inherently monotonic.
J. Silva-Martinez 66
Large component spread (2N-1:1)
INL and DNL
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INL and DNL
j1 j1 j1 N
Vj k
1
RkN
VR
k1
NR RkN
VR
j 1
NVR
- k1
kj
N2RVR
Vj j 1
N
VR, Vj2
j 1 N - j 1
N3
R2
R2
VR2.
Vj
2max 1
4N
R2
R2VR
2, when j
N
21
N
2.
INLj Vj j -1
NVR
VR
N INL 0, INL max N
2RR
.
J. Silva-Martinez 67
CurrentCurrent Steering DACSteering DAC
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gg
Io
I I I
Binary-to-Thermometer Decoder
Fast inherentl monotonic ood DNL erformance
J. Silva-Martinez 68
Complexity increases for large N, requires B2T decoder.
Unit Current CellUnit Current Cell
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Unit Current CellUnit Current Cell
2N current cells typically broken up into a (2N/2 X2N/2) matrix
Current source cascoded to improve accuracy Coupled inverters improve synchronization of
J. Silva-Martinez 69
curren sw c es.
Randomization and DummiesRandomization and Dummies
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J. Silva-Martinez 70
Example: 8+2 Segmented Current
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p g
DAC
- " - - 2 "
J. Silva-Martinez 71
. . . , , . ,Journal of Solid-State Circuits, vol. 33, pp. 1948-1958, issue 12, 1998.
Measured INL and DNLMeasured INL and DNL
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J. Silva-Martinez 72
DAC NonDAC Non--idealities in CTidealities in CT ADCsADCs -- 22
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Effects of DAC non-linearity
Non-linearity caused due to mismatch between different output levels of
DAC
ariation in feedback levels yields signal-dependent feedback charge
error directly fed to the modulator input.
J. Silva-Martinez 73
w u u y v
modulator
DAC ArchitecturesDAC Architectures
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any ot er opt ons w edescribed later
Charge redistribution DAC
Buffer amplifier is required (-)
Vref+
Large capacitor area (-)
Dynamic element match linearization
for multi-level DACs
Vref-Vout
Current steering DACIo- Io+
No buffer amplifier is required (+) Current calibration for linearization
J. Silva-Martinez 74
DAC Current CalibrationDAC Current Calibration
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Current calibration principle
Io+Iout Shared by 32current
Iref
Scal
Sout
C
When one currentsource is beingcalibrated, the spare
Spare
currentsource
Each currentsource has its
J. Silva-Martinez 75
one takes its positioncopy
DAC Current CalibrationDAC Current Calibration
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Comparison of two current calibration schemes
IrefIout
IrefIout
Current couldonly flow in thedirection as Current couldflow in both
arrowrect ons
gm
. ref m Iref
Vcm
Ileak
??
CcalX2
VTleak
Ileak
J. Silva-Martinez 76
(a) Conventional scheme (b) Revised version
DAC Current Calibration (SDR)DAC Current Calibration (SDR)
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Current calibration schemes Off-line process: for analog implementation it requires
Reliable low leakage analog memory
Assume small sensitivity of system parameter to T variations (?)
Could be used for on-line applications too Do the calibration when circuit is working, then use fast switching networks
an ex ra ce s o s connec e ce s o e ca ra on ma n oop.
Glitches at the switching (in-band) speed are generated
Io- Io+Shared by 32
Iref
Scal
Sout
J. Silva-Martinez 77
When one current source isbeing calibrated, the spare onetakes its position
Spare currentsource
C
DAC CalibrationDAC Calibration ((SignalSignal--toto--Distortion RatioDistortion Ratio))
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This is a major (hot) research area in multi-bit sigma-delta modulators.Several alternatives have been reported; main trends are:
Randomize the errors such that the non-linear errors are converted in
Dynamic element matching techniques (I. Galton Approach)
Pseudo Randomizers such as Rotators (Terry Fitz Approach)
Di ital si nal rocessors Schreirer A roach
Drawbacks?
Calibration By design using large overdrive voltages and large dimensions
Pre-calibration of current cells Other options?
J. Silva-Martinez 78
We will revise these techniques in the following section!
MultiMulti--bit DAC Architecturebit DAC Architecture
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Dynamic Element Matching (DEM), Self-calibration combined to achieve
hi h linearit
J. Silva-Martinez 79
When DACi is under calibration, demultiplex Datai to dummy current cell
Dynamic Element MatchingDynamic Element Matching
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Representing DAC input vusing a thermometer DAC
I6
I7
I8
I6
I7
I8
I6
I7
I8
I6
I7
I8
I6
I7
I8
I6
I7
I8
I6
I7
I8
I6
I7
I8
I2
I3
I4
I5
I2
I3
I4
I5
I2
I3
I4
I5
I2
I3
I4
I5
I2
I3
I4
I5
I2
I3
I4
I5
I2
I3
I4
I5
I2
I3
I4
I5
1 1 1 1 1 1 1 1
t
0 Ts 2Ts 3Ts
t
0 Ts 2Ts 3Ts
v = 1 can be represented by any one of I1-8
Averaging all possible combinations produces the ideal output
J. Silva-Martinez 80
Errors are randomized
Implementation of DEM SchemeImplementation of DEM Scheme
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Shifter performs a Rotate-right shift on its inputs PN-sequence generator indicates number of shifts
J. Silva-Martinez 81
DEM is operated at 2GHz to maximize randomization
Shifter ImplementationShifter Implementation
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J. Silva-Martinez 82
- -
Z0 Z7 = Qout0 Qout7
Z8 Z14 = Qout0 Qout6
PNPN--Sequence GeneratorSequence Generator
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Generates maximal length sequence based on 3rd-order primitive polynomial
J. Silva-Martinez 83
Analog SelfAnalog Self--Calibration of Current SourcesCalibration of Current Sources
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Current Calibration PrincipleCurrent Calibration Principle
At the end of a calibration c cle C attains the correct V
J. Silva-Martinez 84
required to generate Iref
MultiMulti--bit Calibrated DACbit Calibrated DAC
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Calibration control signals generated using a N-bit CMOS RingCounter
J. Silva-Martinez 85
Extra dummy current cell used to implement continuous
background calibration
Current Calibration CircuitCurrent Calibration Circuit
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J. Silva-Martinez 86
Current Cell Design ConsiderationsCurrent Cell Design Considerations
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Matching considerations
Sizin of current source transistors
Trade-off
Hi her overdrive volta e rovides
better area efficiency at the
expense of reduced output swing
Larger area results in greater
parasitic capacitances which limit
the speed of operation
Output impedance
Greater than 700k over 100MHz
DACi Unit
current
(W/L),
m=4
Total
area, m2
DAC1-coarse 610uA 203/3.84 7795
signal bandwidth
Sufficient for 12-bits static
(INL) and dynamic linearity
DAC1-fine 35uA 48/16 7680
DAC2 1.55mA 323/2.4 6976
DAC3 960uA 255/3 6885
J. Silva-Martinez87
FDR DAC4 790uA 231/3.36 6985
Simulation ResultsSimulation Results
0
Output Spectrum
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-20
0
Ideal
1% mismatch
-40
1% mismatch +DEM + Calibration
-
-60
ower(dB)
-100Mismatch DEM
Self-
calibration
SNR
(dB)
-
-120
.
Y N N 55Y Y N 63.6
J. Silva-Martinez88
100
101
102
103
Frequency (MHz)
Y Y Y 72.7
Clock Jitter Sensitivity (SJNR)Clock Jitter Sensitivity (SJNR)
i i i d l d l h ff
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For a continuous-time sigma-delta modulator, the effectof clock jitter is noise-shaped at the input of the
.
But for the DAC, the pulse width will be affected by theclock jitter, which is a serious problem for continuous-
me s gma- e a mo u a or.
Out utLoo Filter uantizer(digital)
1/sInput
Y(n)uc(t)
DAC
xc(t)
Clock jitter introduceuncertainty at the DAC
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Clock Jitter Sensitivity (SJNR)Clock Jitter Sensitivity (SJNR)
Relationship between jitter and Phase noise: Lets consider a jittered signal
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Relationship between jitter and Phase noise: Lets consider a jittered signal
no tcos
The phase of the noisy signal is then computed as
nn *T
Therefore, timing error can now be estimated as follows:
2o
o
o
2
n
T
T
We can find the clock jitter varianceemploying the eye diagram, and making
J. Silva-Martinez93
Clock Jitter Sensitivity (SJNR)Clock Jitter Sensitivity (SJNR)
Relationship between jitter and Phase noise:
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Relationship between jitter and Phase noise:
no tcos
2
n
o
o
n
o
*T
tt
Therefore, timing error can now be estimated as follows:
T
Notice that the fre uenc S ectrum of boththe fre uenc S ectrum of both T and VCO hase noiseT and VCO hase noise2T
are correlatedare correlated, hence it make sense to analyze the phase noise.
In general, frequency synthesizer noise profile will determine the
J. Silva-Martinez 94
er per ormance
Lets consider the LC tank based VCOLets consider the LC tank based VCO
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Assume only the R (thermal noise) contributes to
222
;2
4
Q
KTRZff
nn
i2 Noiseless
ftank
J. Silva-Martinez 95
Tank ImpedanceTank Impedance
Around the resonant frequency we
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L
Around the resonant frequency wehave:
0
00
2
Unloaded tank Q, we have
RL0
;20
0
GZ
J. Silva-Martinez 96
Output SpectrumOutput Spectrum
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impulse
c c -
The spectrum exhibits skirts around the carrier frequency,
respect to c, calculate the noise power in this bandwidth and dividethe result by the carrier (average) power
J. Silva-Martinez 97
DefinitionDefinition: This what the phase noise: This what the phase noise
meters measuremeters measure
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meters measuremeters measurePhase noise inPhase noise in dBcdBc SNR with res ect to carrierSNR with res ect to carrier
carrier
sideband
P
HzP 1,log10 0
Psideband(0+,1Hz) represents the single sidebandpower at a frequency offset of from the carrier with
J. Silva-Martinez 98
LeesonsLeesons phase noise modelphase noise model
If normalizing the mean-square noise voltage density to the
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If normalizing the mean-square noise voltage density to the
-
power, then the single-sideband noise spectral density can be
written as
2 instead of 4
02
lo10
FKT
L
sig
J. Silva-Martinez 99
Adding 1/f noiseAdding 1/f noise
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results, then the model is approximated by adding a
parameter
31
2
0
10 112
log10fFKT
Lsig
1 f
J. Silva-Martinez 100
Main issues in Leesons model
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he noise factor F is not known for differenttechnologies and topologies, and this parameter
should be defined by numerous runs ofmeasurement for a specific technology
he is also a fitting parameter
depending on technology. 3
J. Silva-Martinez 101
A 3.5GHz LC tank VCO Phase NoiseA 3.5GHz LC tank VCO Phase Noise
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-30dB/dec
-20dB/dec
-105dBc
J. Silva-Martinez 102
PhasePhase Noise measured in the labNoise measured in the lab
For a periodic sinusoidal signal with noise addedto the VCO cont ol oltage then
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to the VCO control voltage, then
X(t)=Acos(0t+n(t)) t is small random excess hase re resentin
variations in the period.
For |n(t)|
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Assume n(t) = mcos(t+)
X(t)=Acos(0t)-(A m/2)sin[(0 - )t+ ]+0
00 a you measure n e spec rum ana yzer s
nC (t)=A m/2; therefore m=2nC (t)/AJ. Silva-Martinez 104
Clock Jitter Sensitivity (SJNR)Clock Jitter Sensitivity (SJNR)o ng ac o e er ssue,
tcos no
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dBcL
2
2
2
2
2
2
2 A
n
A
n
T
T ccn
L n Bc 1010fL
Then
A
nTT
c
2
22
2 2
2
Timing spectrum is correlated with phase fnTfT c2
2
22 2
no se measure n e spec rum ana yzer
RMS value of total jitter L (usually in dBc) T 22 T
J. Silva-Martinez 105
A
cper
2
02
per
Jitter Issues: High Clock FrequencyJitter Issues: High Clock Frequency
D(n-1)Vi
Loop Filter
Dout
ttere
Clock
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D(n-1)Vin
D(n)
T(t)
QuantizerVDAC
Re-timed
DataMulti-Bit
Flip-Flops
Error FunctionError FunctionJitteredClock
DAC
T
tTnDnDnJ outouterror
1
In the frequency domain: Differential of Dout convolves with Jn()
noutSnouterror JDT
si nJDZJ
2
21 1
J. Silva-Martinez 106
In-band signal is shaped by , then it is not very criticalOut-of-Band quantization noise and blockers convolve with the clock jitter
11
Effect of clock jitter on SNREffect of clock jitter on SNR
NTF*Vq
then
T
nVnV)n(e outoutj 1 uan za on
noise
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ZJZVZ)Z(E outj 11
ZJZVZNTFZV*ZSTFZ)Z(E
Or
qinj
11
Jn
f
Jn
ZJZV*NTFZ
ZJZV*STFZ)Z(E
ere ore
q
inj
1
1
1
1
Clock
Noise
21 1 sT
sinZ
f
fs-fs dZEP jOSR/
S,j
221
02 SJNR is function of
J. Silva-Martinez 107
dZJZVZNTFZP qOSR/
Q,j
2121
012
NTF and J(Z)
ContinuousContinuous--Time BPTime BP-- ADC: Jitter effectsADC: Jitter effects
sTsi nc
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2
si nc
si n
NRZ
TPOSR
dBSJNR
6
2
10*
60
sj
j
T3104
2
2
si nc**
l o10l o10
so
i n
i n
TPOSRP
SJNR
, ,noise has been usually approximated as:
J. Silva-Martinez 108
124
1
s
jBW
onQuanti zatin
T
dfPZJ
ContinuousContinuous--TimeTime ADC: Jitter & BlockersADC: Jitter & Blockers
RF clock filtering is anCLK Qn
ffck
0 ff0 ff
0 fckf0
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RF clock filtering is aneffective method to +
0 fckf00 fckf0
partially overcomethis issue!
J Silva et.al., SRC
Data
out2-bit
Quantizer
Multi-bitZ
-1
- Quantizationand Jitter
0 fckf0 0 f0 fck
repor ec
JnXfck
1-Z-1
Jitter induced noise
f00 fck
f0
inP
logSJNR 1010
High frequency blockers convolve with Jn and are folded back in band.
Considering
n
BWkerBlocnonQuantizatin
dfPZJ
dfPZJPZJ
212 1
11Pblocker and
PPquantization
J. Silva-Martinez 109
BW
onQuantizatin
BWkerBlocno
dfPZJ
logSJNR212
101
110
STF*Blockers
+ NTF*Vq
STF*Blockers
+ NTF*Vq
Effect of clock jitter on SNR:Effect of clock jitter on SNR:++
nt
nVnV)n(e 1
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nVnV)n(e outoutj 1
ZJZVZ)Z(E outj 1
1
Jn
f
Jn
f
ZJZV*NTFZ
ZJZV*STFZ)Z(E inj
1
1
1
1
OSR/ 221 Clock Phase Noise
ffs
ffs
,
J. Silva-Martinez 110
sqskerBlocOSR/
inbandj TdJVNTFVSTFZP 2
121
012
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No Blockers
J. Silva-Martinez 111
JitterInsensitivityofSwitchedJitterInsensitivityofSwitched
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Jittererror
Sofar,SCDACisthemostjittertolerantapproach
Quitepreciseandmaynotrequirefurthercalibrationprocedures
Drawbacks
of
the
SC
DACDrawbacks
of
the
SC
DACPeakcurrentintheSCDACcanbeashighas10timeIDACusedinthecurrentmodeDAC!
J. Silva-Martinez 112
ClassABOPAMPmayhelpwhiledealingwiththisissue
MultiMulti--bit Hybrid DACbit Hybrid DAC
Effects of DAC pulse shape on clock jitter error, Ejit
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Relaxed slew rate, GBW requirements
More sensitive to DAC clock jitter
Requires higher slew rate, faster op-
amps
Less sensitive to DAC clock itter
Ejit varies negligibly with S
Moderate slew rate, GBW requirements IHYB 1.6 INRZ
J. Silva-Martinez 113
ess sens t ve to c oc tter
Multi-bit Hybrid DAC Implementation
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- ,
C2, C3 implement 7 output levels
Unit-weighted C4 implements 2
additional levels
, s mp ement
Fully-differential DAC currents
Complete clock cycle used for
capacitor discharge
Multiple capacitor banksused
Inherent dynamic element
DAC controller selects one of the
capacitor banks during a clockcycle
J. Silva-Martinez 114
apac ors are pre-c arge o refwhen not selected by controller
Hybrid DAC Switch Operation
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When 2N = 1, switch operates as a current source for VC1 > (VGSN Vt)
C1 discharges linearly, peak currents are limited
J. Silva-Martinez 115
C1 GSN t
C1 discharges exponentially, clock jitter error is reduced
Simulation Results
Comparison of DAC full-scale currents SNR vs. % Jitter for NRZ and Hybrid DACs
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p y
2
Non-Return-to-Zero DAC
Switched-Capacitor-Resistor DAC
Hybrid DAC70
75
SNR vs Clock Jitter: -6 dBFS Input Signal @ 5MHz
NRZ DAC
Hybrid DAC
1
1.5
ut,
FS(mA)
55
60
65
SNR
(dB)
0.5
Io
45
50
0 0.5 1 1.5 2 2.5
0
Ts (ns)
10-3
10-2
10-1
40
Clock Jitter (% Ts)
J. Silva-Martinez 116
ConnectionoftheSCDACs
This is the traditional switched-capacitor DAC
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p
Several blocks are connected inparallel and selected by the
randomizer
1 block is used every singleperiod. Capacitors are chargedwhen not selected by the
C1 till C4 are binary weightedCapacitors and are routed to the
-terminals to emulate the multi-
bit operation
-
J. Silva-Martinez 117
overlapping clocks
Suggestedarchitecture:UseofSCDACs
Encoder converts the
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t ermometer co e nto
code
are generated
have to be synchronized
Instead of using a large number of comparators:Use S/H
J. Silva-Martinez 118
Minimize power
ConnectionoftheSCDACs
If properly designed, thisarchitecture have the following
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a c tectu e a e t e o o gproper es:
i) low-sensitive to clock jitter
ii) Peak current is no more than2 times larger than theconventional current-node
iii) Loop gain may not suffervariations when operated asmulti-bit DAC
iv)iv) Key element: Switch inKey element: Switch in
J. Silva-Martinez 119
oo
ProposedSolution
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eyconcep s:Let us maintain the transistor in saturation region as much time as possible (at
least T/2 seconds). The circuit operates as a currentmode circuit!
When Vds
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SNR>12bits,Power
-
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Maingoal:ENOB14bits,SQNR>16bits,Totalpower
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-, ,
Filter realization Noise, Power, linearity
Quantizer (ADC) Input impedance, Kickback noise, Power consumption, Delay
DAC Speed, Jitter performance, Linearity, Output impedance
Jitter, duty cycle and phase errors
System verification (Cadence) SQNR, SJNR, SNR, SDNR, stability, loop delay
oc s
Calibration Cover PVT variations, mismatch, add non-linearities
Extensive ost-la out Simulations
J. Silva-Martinez 123
Metal delays, bondwire inductors, do not use ideal GND and ideal power supplies Isolate as much as possible critical blocks from noisy digital.
Be careful with your assumptions; in many cases are not totally true!
Oversampled A/D ConversionOversampled A/D Conversion
Architecture Specifications and Matlab/Verilog-A simulations Order and quantization levels
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-, ,
Filter realization Noise, Power, linearity
Quantizer (ADC) Input impedance, Kickback noise, Power consumption, Delay
DAC Speed, Jitter performance, Linearity, Output impedance
Jitter, duty cycle and phase errors
System verification (Cadence) SQNR, SJNR, SNR, SDNR, stability, loop delay
oc s
Calibration Cover PVT variations, mismatch, add non-linearities
Desi n exam lesDesi n exam les
J. Silva-Martinez 124
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J. Silva-Martinez 131
-
7/29/2019 Sigma Delta 1.3
132/144
The DEM is usuallyslow and may lead tosi nificant loo dela !
May require loopcompensation
J. Silva-Martinez 132
132
against blockers!
-
7/29/2019 Sigma Delta 1.3
133/144
J. Silva-Martinez 133
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134/144
J. Silva-Martinez 134
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7/29/2019 Sigma Delta 1.3
135/144
J. Silva-Martinez 135
-
7/29/2019 Sigma Delta 1.3
136/144
J. Silva-Martinez 136
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7/29/2019 Sigma Delta 1.3
137/144
J. Silva-Martinez 137
-
7/29/2019 Sigma Delta 1.3
138/144
J. Silva-Martinez 138
-
7/29/2019 Sigma Delta 1.3
139/144
J. Silva-Martinez 139
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7/29/2019 Sigma Delta 1.3
140/144
J. Silva-Martinez 140
-
7/29/2019 Sigma Delta 1.3
141/144
J. Silva-Martinez 141
-
7/29/2019 Sigma Delta 1.3
142/144
J. Silva-Martinez 142
-
7/29/2019 Sigma Delta 1.3
143/144
The DEM is usuallyslow and may lead tosi nificant loo dela !
May require loopcompensation
J. Silva-Martinez 143
143
against blockers!
-
7/29/2019 Sigma Delta 1.3
144/144
J. Silva-Martinez 144
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