silicon odometer: an on-chip reliability monitor for

1

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency

Degradation of Digital Circuits

Tae-Hyoung Kim, Randy Persaud and Chris H. Kim

Department of Electrical and Computer EngineeringUniversity of Minnesota, Minneapolis

chriskim@umn.eduwww.umn.edu/~chriskim

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Outline• NBTI Overview• Previous NBTI Measurement Method• Proposed Silicon Odometer Circuit

– Beat Frequency Detection Scheme

• Test Chip Measurement Results– Voltage and Temperature Dependency– DC and AC Stress

• Conclusions

3

Negative Bias Temperature Instability

SiH + h+→ Si+ + H

• One of the most critical reliability issues today• Holes in inversion layer interact with Si-H bonds at

interface when device is under stress (Vgs= -Vdd),à leave interface traps

• NBTI manifests itself as an increase in |Vtp|

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Stress and Recovery

• When a stressed PMOS is turned off– Si-H bond breaking stops– H diffused back to Si/SiO2 interface and anneals broken bonds

• AC stress increases lifetime projection• Increasing field and temperature, reduced gate overdrive

reintroduce NBTI concerns in the late 90s

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NBTI Signal Probability Dependence

• Device is stressed when input signal is low• Signal Probability (SP): Probability that the

input signal is low• NBTI effect is SP dependent

Time (s)∆

V tp

(mV)

0

2

4

6

8

10

0 100 200 300 400 500 600 700 800 900 1000

SP=1.0SP=0.75SP=0.5SP=0.25

SP=0.75

SP=0.5

SP=0.25

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NBTI Impact on Digital Circuits

VL

WL

BLBLB

VR

1

5

o1

o2

3

24

8

7

6

Logic circuits§ FMAX degrades§ Leakage power reduces

Memory circuits§ Read margin worsens§Write stability improves§ Read delay remains the same

i1

i3

i2

• NBTI affects critical circuit parameters• Need to design circuits with NBTI-induced shifts

comprehended

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Circuit Techniques to Mitigate the Impact of NBTI Degradation

• Product margin-testing, guard-banding• Size up devices

– Negates benefits of scaling, increases power• Toggle circuit nodes

– Less degradation under AC stress• Lower temperature

– Difficult task now…dense/fast designs are hot• Progressive Vtp and Vdd tuning

– We can slowly increase Vdd or forward body bias PMOS as performance degrades with aging (Intel, ISSCC07)

Bottom line: Need to accurately measure the NBTI effect and develop compact models

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Previous NBTI Measurement Technique

V. Reddy et al., IRPS, 2002

• Measure ring oscillator frequency shift• Main limitations

– Low sensing resolution (few % frequency change)– Sensitive to environmental variation during measurement– Invasive, not suitable for run-time monitoring

Before Stress Stress After

Stress

Ring Osc./Critical Path Replica Counter

F = Frosc/N

F = Frosc

Vcc_ring

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Proposed Silicon Odometer Circuit

• Two free running ROSCs for beat frequency detection• Sample stressed ROSC output using reference ROSC

output• Count PC_OUT to determine frequency degradation• Insensitive to environmental variation

Phase Comp.

Stressed ROSC (freq=fstress)

...

...

Reference ROSC

A

BC

PC_OUT

Measurement

Stress period

VDD_NOM

VDD_STR

0V

(freq=fref)

(freq=fref - fstress)

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Principle of Silicon Odometer Circuit

• Operation example– 1% delay difference before stress à N = 100– 2% delay difference after stress à N´ = 50– N´ changes by 50 for 1% change in delay à sub-ps resolution

degradation measurements

Stressed ROSC

stressref f(N – 1)

fN 11

)1( ---NN´

NN´f

ff´stress

stressstress

frefN 1.

A

C

B

. = .

stressref f´(N´ – 1)

fN´ 11. = .

=

- Before stress

- After stress

- % frequency degradation

Reference ROSC

PC_OUT

(freq=fstress)

(freq=fref)

(freq=fref - fstress)

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Sensing Resolution Comparison

• High delay sensing resolution– For N=100 and T=4ns, maximum sensing resolution is

0.4ps (0.01%)

020

4060

80100

120

0 0.5 1 1.5 2Frequency degradation (%)

Coun

t ero

utpu

t(N

)99 98

50

33ProposedConventional

ΔN=1 @ 1%

N=50 @ 1%Δ

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Test Chip Architecture

• Frequency trimming capacitors set the initial frequency difference between the stressed and reference ROSC

• 5 bit majority voting circuit for bubble rejection

Ring oscillator(reference )

Phase compar -

ator

8-bitcounter

5-bitmajority voting

ckt .

Beat freq .

detector

Register

ROSC frequencytrimming

Ring oscillator(stressed)

DETECT

… 11101000 … …11110000 …Bubble rejection

Scan outN

Reset Reset

DETECT

frefN 1.

Controlsignals

(Meas_stress,Toggle,OSC_en )

Controlsignals

(Meas_stress,AC_stress,AC_CLK,

Recv_stress )

ROSC_REF

ROSC_STRESS

B

A

C D

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Ring Oscillator Circuit Design

• 4ns ROSC period, frequency trimming capacitors• Stress mode and measurement mode• Meas_Stress triggers the measurement

Meas_StressAC_Stress

AC_CLK

Recv_Stress Virtual VDD

Stress Mode

Control #1

Stress Mode

Control #2

Meas_StressAC_Stress

Toggle

….

2 0C

S0

Stress mode

Measurementmode

VDD_STRESS V DD_NOM 21C

S1

22C

S2

23C

S3

24C

S4

ROSC Frequency Trimming

Stress VDD Control

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Various Stress/Recovery Modes

X11AC_StressX00Measurement

001DC_Stress w/o toggle101DC_Stress w/ toggle

ToggleAC_StressMeas_StressStress Mode

Meas_Stress

<1µs

Stress StressMeas. Meas.Meas.

Meas _StressAC_Stress

AC_CLK

Recv _Stress Virtual V DD

Stress Mode

Control #1

Stress Mode

Control #2

Meas _StressAC_Stress

Toggle

….

Stress mode

Measurementmode

VDD_STRESSV DD_NOM

Stress VDD Control

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Phase Comparator Circuit Design

• Delayed ROSC_REF used as reference clock• Dynamic circuit implementation• PC_OUT contains the beat frequency

CLK

CLK CLK

PC_OUT

CLK

ROSC _REF

PC_OUT

ROSC _STRESS

Beat frequency

CLK : Delayed RSOC _REF

CLK CLK

CLK

B

B

A A

A

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Simulated Waveforms

• 3 ROSC cycles of measurement latency• Static signal from 5b majority voting circuit• DETECT signal gives beat frequency

ROSC _STRESS (A in Fig . 4 )

ROSC _REF (B in Fig . 4 )

PC_OUT(C in Fig . 4 )

VOTE _OUT(D in Fig . 4)

DETECT Beat frequency

Latency

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Test Chip Implementation

• 0.13µm MM/RF CMOS, 265 x 132 µm2 layout area• Stressed and reference ROSCs have identical layout• Chips were not recycled since once stressed, they will not

fully recover

Labview GUI

Measurement work bench

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Odometer Measurement Results

0.00%

0.05%

0.10%

0.15%

0.20%

0.25%

0.30%

0 2000 4000 6000

Time (sec)

Freq

uenc

y de

grad

atio

n

Stress and recovery behavior Temperature dependency

0.00%

0.05%

0.10%

0.15%

0.20%

0.25%

0.30%

0.35%

0 500 1000 1500 2000

Time (sec)Fr

eque

ncy

degr

adat

ion

130°C, 1.2V DC stress

30°C, 1.2V DC stress

1.2V, 30°C

• Resolution high enough (<0.02% or <0.8ps) for non-accelerated stress measurements

• 80% recovery rate due to relatively thick Tox

• Worse degradation at higher temperature

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• Degradation exponentially dependent on the electric field• Delay degradation has same power-law dependency as ΔVtp

0.67%

0.24%

Stress Voltage Dependency

y = 0.0010 x 0.1220

y = 0.0028 x0.1158

0.10%

1.00%

1 10 100 1000 10000

Time (sec)

Freq

uenc

y de

grad

atio

n

1.2V DC stress, 30C

1.8V DC stress, 30C

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• AC stress results in 43-50% less frequency degradation• Weak frequency dependency

– Many baby steps takes you same distance as a few giant steps• This behavior also confirmed by recursive RD models

0.67%

0.33%0.38%

DC Stress versus AC Stress1.8V, 30°C

0.00%

0.10%

0.20%

0.30%

0.40%

0.50%

0.60%

0.70%

0.80%

0 500 1000 1500

Time (sec)

Freq

uenc

y de

grad

atio

n

AC stress (120MHz)AC stress (1GHz)DC stress

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Conclusions• NBTI is a growing threat to circuit reliability• On-chip NBTI monitor circuits are needed to

understand aging impact on circuits• Silicon odometer circuit demonstrated

– Fully digital, minimal calibration– Sub-picosecond sensing resolution– Sub-microsecond measurement time for minimal

annealing– Differential measurement eliminates common-mode

environmental variation impact

Acknowledgements:IBM for financial support and UMC for chip fabrication