silicon photonics: a platform for integration, wafer level
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Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging
M. AsghariKotura Inc
April 2007
2
Contents:
► Who is Kotura
► Choice of waveguide technology
► Challenges and merits of Si photonics packaging
Integration: High functionality and lower component count
Fibre interface
Stress related issues
Thermal management
Hybrid assembly
► Examples of current activities
3
Who is Kotura?
► Founded in 2003: Merger of two companies
► A Leading Silicon Photonics CompanyShipping in volume to Tier-1 customers
Products deployed in live networks
Over 50 patents issued / pending and license to all Bookham Si based IP.
► Strategy based on partnershipBuild competence on chip design and fabrication
Be a high value, high functionality chip supplier
Form partnerships for product development, fast market penetration and achieving maximum application coverage
► In house Si Fab, prototype packaging and low volume A&T
0.25um DUV Scanner, World Class Dry Etch Capability, ...
► Sub Con manufacturing partner in China
► Happy to work as partner / foundry on a joint development or sub-contract basis
4
Si Technology: Basics
Material Property Si
Refractive Index 3.47 Well controlled
Material Type Crystal
dn / dT 1.8x10-4K-1
Thermal Conductivity, K 130-156 W/mK
Tuning 85 pm / oC
Temp Stability + / - 0.1 oC
Key Strengths- Manufacturability- Scalability- Volume cost curve- Process control- Potential for integration- Solid state reliability- Electronic integration- Full set of functionality
Passive devicesCurrent injection devices
Detectors, VOAs etc
Hybridisation capability
Key Challenges- Fibre interface- Temperature control- Stress issues on packaging
Si
Si substrate
Oxide
Waveguide width
Silicon thickness
Ridge height
5
Choice of Waveguide Technology
Photonics sweet spot
0.01
0.1
1
10
100
0.1 1 10
Deep etch technology
Bend Radius (mm)
Propagation Loss (dB/cm)
Experimental data
Waveguide Dimension (um)
0.01
0.1
1
10
100
Ben
d R
adiu
s (m
m)
Prop
agat
ion
Loss
(dB
/cm
)
Kotura
FiberIII/VElectronics
6
Choice of Waveguide Technology
► Propagation loss independent of Wavelength and Polarization
► Very low group velocity and polarization mode dispersion
► Very low waveguide crossing loss and X-talk► Optimum core size for most optical
functionalities is at 3 to 4um.
0.5 1 1.5 2 2.5
2
3
4
WG Thickness (um)
Effe
ct a
nd g
roup
inde
x
Group index
Effective index
TETM
TE TM
-0.3
-0.2
-0.1
0
1520 1530 1540 1550 1560 1570
Wavelength (nm)
Propagation Loss (dB)3um Core Waveguide
Experimental
TE(dB/cm)TM(dB/cm)
-120
-100
-80
-60
-40
-20
0
0 1 2 3 4 5 6 7 8 9Waveguide Width, W ( um)
Cro
ssta
lk (d
B)
101.8
1.5
1.2
0.9
0.6
0.3
0
Loss
(dB
)
XTalk_TE(0.5um)XTalk_TE(1um)XTalk_TE(3um)Loss_TE(0.5um)Loss_TM(0.5um)Loss_TE(1um)Loss_TM(1um)Loss_TE(3um)Loss_TM(3um)
H
Theoretical
H
Loss
X-Talk
0.5
1
3
0.5
13
7
Passive Waveguide Technology
Key ComponentsBends and MirrorsCouplers and splittersMode transformersWavelength Mux / Demux / selective elementsPolarisation splitters, rotators and discriminatorsOptical / modal Filters
-40
-35
-30
-25
-20
-15
-10
-5
0
191.8 192.3 192.8 193.3 193.8 194.3 194.8 195.3 195.8
Frequency (THz)
Tran
smis
sion
(dB
)
R
Part 1Part 2
Part 3
<0.1dB Loss for U-bend with 250um Radius
22--
24
24--
26
26--
28
28--
30
30--
32
32--
34
34--
36
36--
38
38--
40
40--
42
42--
44
44--
46
46--
48
48--
50
50--
52
52--
54
54--
56
56--
58
Intra-channel Crosstalk (dB)
Num
ber
of Com
bin
atio
ns.
0
100
200
300
400
500
8
Current Injection Devices: VOA example
n-type
p-type
p+ n+
Silicon
BOX
0
5
10
15
20
25
30
35
40
45
50
0 5 10 15 20 25 30 35 40 45 50
Current (mA)
Atte
nuat
ion
(dB
)
01234567
0 2 4 6 8 10
Attenuation (dB)
Phas
e Sh
ift
(uni
ts o
f Pi)
00.10.20.30.40.50.60.70.80.9
1
0.0001 0.001 0.01 0.1 1 10
Time (ms)
Nor
mal
ised
pha
se c
hang
e
SOI Thermal Thin BOX 400mW
SOI - Carrier injection 10 mW
Silica 400mW
SOI Thermal Thick BOX
40mW
-22-20-18-16-14-12-10-8-6-4-20
0 5 10 15 20 25 30 35 40Applied Current / mA
Extin
ctio
n / d
B
Bar TE Cross TEBar TM Cross TM
MZ switch
9
III/V Device Hybridization
Si MetalizationVertical plinth
wirebond
Solder
Si Waveguide
Horizontal taper in Si can improve lateral coupling loss due to lateral placement in-accuracies
Shelf on which the laser is mounted
Metal track
Accurate vertical alignment is achieved by removing low tolerance layers from the laser and accurate etching in Si of mounting shelfAlignment marks aim to achieve maximum lateral placement accuracySi plated with solder and includes some simple electronics componentsOn placement of laser local heating is applied to reflow the solder
Solder
MirrorWaveguide
Photo-diode Hybridization
Laser / SOA Hybridization
Commodity actives for low
cost
High Resisitivity Si for RF Lines
10
Fiber Coupling
• A three dimensional taper (mode expander) reduces coupling loss to <0.5dB.• The back reflection from such a facet is <-50dB• PDL is <0.05dB• Wavelength and Temperature insensitive• Technology offers low cost passive V-groove based fibre attach
Kotura’s Patented Epi Taper technology enables: - Fiber mode matching with no compromise in device performance- Core size reduction evolution
3D Taper
-70
-60
-50
-40
-3020 30 40 50 60 70
Vertical Fibre position (um)
Back
Ref
lect
ion
-65dB
1um to 4um core
12um core
11
Stress Management
Ex field Ey field
Strain not included
Ex field Ey field
Typically 0.1% TM
Stress induced x & y index
change
Stress and roughness can cause mode conversion
Strain included
~0.0% TM
Challenges:
► Si is prone to stress induced index change
► This can cause polarization conversion, polarization mode dispersion and PDL
► A combination of stress and roughness can also cause mode conversion
12
Stress Management
After PDF Compensation
-12-11.5
-11-10.5
-10-9.5
-9-8.5
-8-7.5
-7-6.5
-6
191.8 191.85 191.9 191.95 192 192.05 192.1 192.15 192.2 192.25 192.3 192.35 192.4 192.45 192.5 192.55 192.6 192.65 192.7 192.75 192.8 192.85 19
-10.5-10
-9.5-9
-8.5-8
-7.5-7
-6.5-6
-5.5-5
-4.5
192.8 192.85 192.9 192.95 193 193.05 193.1 193.15 193.2 193.25 193.3 193.35 193.4 193.45 193.5 193.55 193.6 193.65 193.7 193.75 193.8 193.85 19
Before PDF Compensation
Benefits► Stress can be used for performance
correction eg on AWG array for PDF.► Stress can be utilized for sensor
applications
0
0.5
1
1.5
2
2.5
3
3.5
0 10 20 30 40
Channel
PDF (GHz)
13
Thermal Considerations
► High Si dn/dT requires a high level of thermal stability
► High thermal conductivity of Si enables excellent temperature uniformity and effective heat removal
► Developments in Si packaging have enabled better than 0.1oC thermal management even with high power and time varying thermal dissipation at chip level.
► Integrated temperature sensors can be fabricated into the fabric of the Si chip close to sensitive areas
-600
-400
-200
0
200
400
600
-10 0 10 20 30
40 50 60 70
Ambient Temperature / DegC
Grid
Offs
et /
pm
Improvements made in thermal management of Si PLCs
0
2000
2500
010 20 30 40 50 60 70 80
Temperature (deg C)
Resistance (Ohms) nin: 0.5% °C-1, pip: 0.7%°C-1
DT = 0.37 oC
10 channel VOA
3 channels on
9 channels on
Temp differential on chip, DT = 0.38 oC
14
Thermal Considerations ….
-4
-3
-2
-1
0
1
2
3
4
0 10 20 30 40 50 60 70
Temperature (C)
Wavelength Shift (nm)
DFB (0.1)DFB(0.08)AWG (Si)AWG (SiO2)
Thermal isolation trench
► Thermal isolation features such as deep etches and bridge structures can be fabricated to enable thermal isolation
► Si and InP based devices have very similar wavelength drift with temperature
15
Si Integrates Waveguides and Micro-Bench Capabilities
Laser: Passive Auto-aligned
Passive Fiber Attach
VOAs
Surface Mount PD
Front Facet Monitor
Grating or WDM Coupler
- Wafer scale testing
- Flip chip technology for fiber attachFuture Development
WDM Coupler
WDM Coupler
Monitor VOA Laser
VOA
PIN
APD
Active area
p+
n+BOX
Developed in collaboration with Enablence
16
100Ge CWDM Solution
Tx► 10 CWDM DFB Lasers hybridized into the Si
chip either individually or as a bar► Integrated AWG or Echelle grating, to Mux
channels together► Lasers directly modulated► Front facet detectors integrated to provide
power monitoring► VOAs can be integrated to provide power
balancing without the need to modify laser drive conditions
Rx► Individual PINs or a bar, surface mounted
onto wet etched 54 degree vertical coupling mirrors.
► Demux is integrated into the same chip ► Fast VOAs can be integrated to improve
dynamic range or provide protection
Lasers Detectors
DFB λ registration: +/- 2nm
12nm6.5nm
17
Kotura’s CWDM 100Ge Solution
Au:Sn solder
Active area
WDM DFB Array(Cyoptics)
Mux / DeMux
PD / Surface mount technology
Monitor / VOAs
p+ n+
BOX
- High level of integration both monolithic (waveguide) and hybrid (micro-bench)- Developed in partnership with Cyoptcis into a very small form factor package
VOAs
15mm
7mm
18
Fitting 100G into ~10G Footprint !
100Ge Module
100Ge TxRx
10 x 10G ROSAs
Micro-bench assembly
Si PLC Tx Chip 100G TOSA
MuxDe Mux+ +
10 x 10G TOSAs
Or
Si PLC Rx Chip
Conventional technology can not support the footprint
Si Solution can support 10G FXP footprint for 100G and offers huge cost saving potential
100G ROSA
&
19
Key Challenges & Merits
► Key ChallengesLow propagation and fiber coupling lossFacet preparationOptical, Electrical & Thermal X-talkLow stress chip attachThermal management
► Key meritsLow component count: IntegrationLow cost fiber attach: V-grooveStress engineering for compensationThermal tuningExcellent thermal conductivity and temperature uniformitySmall foot printHighly scaleable and cost effective manufacturing: CMOS fabLow cost, automated A&T: Wafer scale hybridization and test, Peak and place assembly, Lead frame packaging…
Lead frame
Simple assembly
Ceramic Carrier
Fiber Block
Si AWG
20
Reliability and Stability
Damp Heat (85C - 85% RH)in-situ monitoring 40 VOA channels
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
1000 1100 1200 1300 1400 1500
Time (hours)
Del
ta IL
(dB
)
500 hr for qualification and 2,000 hrs for information
Si is a proven Technology platform:- Well known material system- Solid state switching …
Mea
n lif
e (3
,000
hr t
est)
( ) )()( 11 nnTtTuk
E RuRtaeAF −+−=Ayring acceleration model
Mean life over 35 years
Predicted mean life based on 85/85 life testsa=0.0005, n=2, 0.024 kg water per kg dry air
0
20
40
60
80
100
120
140
160
180
200
0.2 0.4 0.6 0.8 1.0 1.2
Activation Energy [eV]
Acc
eler
atin
fact
or [-
]
0
10
20
30
40
50
60
70
80
90
100
AF (2,500Hr)
ML [yr]
Real proof is:- Real & qualified products - Tier 1 customers- In live networks carrying traffic
Reliability is always a key barrier to deployment of a new technology- Higher integration increases the possibility and consequences of failure- Takes time and a lot of hard data
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