team 1k design overview
Post on 03-Jan-2016
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TEAM 1kDesign overview
LBNL group
8/25/09
Sensor
TEAM 1k 1024x1024 16 outputs Vhigh, Vlow
edge m
ount connector
Analog out
Digital I/oPow
er supply
AuxPow
er supply
Voltage filtering and Reg.
Pseudo to fully diff.
line driver
Ref voltage
Out 1..15
Clock DriversVolt/cur
DABias current/voltages
To all circuitsIn this board
OUTL,OUTH
PeltierPower supply
connector
TemperatureMonitor
TempBias/ driver
Clock signals
CurrentMonitor
DiodeBias/ driver
Voltage reference
DACs 13 DAC 7811
6 Voltage output 7 current output
Analog J1-35: Bias-n3SRE: 300 uA to GND J1-36: Bias-n3SBuf: 300 uA to GND J1-37: Bias-PreDrv: 100 uA to GND J1-38: BiasPin: 500 uA to GND J1-39: BiasNin: 20 uA to VDD
Digital part J2-36: BiasPin BIAS: 100 uA to GND
Voltages Pos rail : 35mA VDDR: ? Pos Rail Analog: 22mA
DAC7811
*For voltage buffer OPA277 (U612 in this picture) was substituted by BUF63
Clock
Clock wave forms
RINIT
CCK1
CCK2
CINIT
Digitize
RCK1
RCK2
Row 0 10Col 1 2 3 4 0 1 2 3
External signals are only Reset (RINIT), CCk1, CCk2
Hybrid board
Differential Drivers
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