the future of field-programmable gate arrays · programmable logic wsplds (simple pogrammable logic...

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The Future ofField-Programmable

Gate ArraysPeter Alfke

Director, Applications EngineeringXilinx, Inc

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wThe future is exciting

wLe future est formidable

wDie Zukunft ist rosig

w Il futuro é fantastico

wEl futuro es formidable

wFramtiden är fantastisk

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Why Programmable Logic?

w Ideal for customized designs

w Offers the advantages of high integration— complexity, density, size— cost, power consumption, reliability

w Avoids the problems of ASICs— high NRE cost and long delay— testing problems— increasingly complex electrical issues

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Programmable Logic

w SPLDs (Simple Pogrammable Logic Devices =PALs)– $ 227 M, shrinking rapidly = 12% of a $1.955B market,

w CPLDs (Complex Programmable Logic Devices)– $ 688 M = 35%

w FPGAs (Field-Programmable Gate Arrays)— Anti-fuse-based FPGAs

– $ 183 M = 9%— SRAM-based FPGAs

– $ 859 M =44%, growing fast

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CPLDs

w AND-OR Structure, derived from PALs

w Advantages— fast pin-to-pin delays, wide input decoding— simple software, easy to understand

w Disadvantages— low complexity, few flip-flops— not scalable in size— high static power consumption ( except CoolRunner )

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Anti-Fuse Based FPGAs

w Gate-Array-like structure

w Advantages:— non-volatile, single-chip, instant-on— logic circuits tolerate radiation, — but flip-flops are SEU-sensitive

w Disadvantages— one-time programmable, slow programming— limited complexity, slow process evolution— second-tier suppliers, niche market

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SRAM-based FPGAs

w Gate-Array-like structure — look-up-table logic, medium granularity— configured by latches and pass-transistors

w Advantages— highest complexity, many flip-flops— re-configurable, rapid evolution (standard process)— main-stream market, major suppliers

w Disadvantages— Volatile, configuration is radiation-sensitive

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Design Alternatives

w Microprocessors— ideal, if fast enough

w Gates, MSI, PALs— inefficient, inflexible, outdated

w Dedicated Standard Chips and Chip Sets— cheap, but inflexible

w ASICs— only for rock-stable, very high-volume designs

w Programable Logic— for flexibility, reconfigurability, fast time-to-market

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ASICs Getting Less Attractive

w Non-Recurring Engineering cost increases— more masking steps, more expensive masks

w Minimum order quantities increase— larger wafers, smaller die

w Silicon capability often exceeds user needs

w Suppliers abandon unprofitable market

w Low-tech ASICs have lost their technicaladvantage over FPGAs

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User Expectations

w Logic capacity at reasonable cost— 50,000 to a million gates

w Clock speed— 100 MHz and above

w Design effort and time— synthesis, fast compile times, tested and proven cores

w Power consumption— must stay within reasonable limits

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FPGA History (XC4000)

w > 20x Bigger

w > 5x Faster

w > 50x Cheaper1/91 1/92 1/93 1/94 1/95 1/96 1/97 1/98 1/99

Year

CapacitySpeedPrice

1

10

100

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FPGA Density

Virtex V100075 million Transistors

Den

sity

(sys

tem

gat

es)

50M Gates

Virtex 0.13µ

XC40250XV

50M

2M

1M

500K

1998 1999 2000 2001 2002 2003 2004

4M Virtex 0.15µ

Virtex 0.18µ

10M

50 Million System Gates in 2004

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1997 1998 1999 2000 2001 2002

FPGA Speed

0

20

40

60

80

100

120

140

160

180

200

250

300

350

400

450Sy

stem

Clo

ck R

ate*

(MH

z)

4200 MHz D-P Memory4143 MHz ZBT SRAM I/F4155 MHz SONET4125 MHz SDRAM I/F4 66 MHz 64-bit PCI

*1/(Tsetup+Tclock-to-out)

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Three Pillars of Progress

w Technology— smaller geometries, more and faster transistors— better defect densities, larger chips

w Architecture— system features: Memory, clocks, I/O— hierarchical interconnect

w Design Methodology— powerful and reliable cores, faster compile time— modular, team-based design, internet-based tools

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Recent Developments

w Deep sub-micron arrived earlier than expected— 0.5µ - 0.35µ - 0.25µ - 0.18µ - (0.15µ) -

w Better speed, density, cost “for free”

w Requires voltage migration— 5V - 3.3V - 2.5V - 1.8V - (1.5V) -

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Process TechnologyEvolution

Feat

ure

Size

(mic

ron)

5V

3.3V

2.5V1.8V

1.3V

1.2

1.0

0.8

0.6

0.4

0.2

0.1 1.0VV0.8V

1990 1992 1994 1996 1998 2000 2002 2004

1.5V

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Cutting-Edge Technology

w FPGA technology is in step with microprocessors,and benefits directly from their fast evolution

w 0.18 micron now, 0.15 in development

w Clear roadmap to 0.13, even 0.10 micron

w Copper technology in 2000

w Copper with low-k dielectric in 2001

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Chip Scale 0.8 mmFinePitch BGA 1.0 mm

Flip ChipTechnology

PLCC

PGAPQFP

HQFP

BGA

SBGA

FPGA Packages

1.0mm

1.27mm

100

300

500

700

1000

Pins

1997 1998 1999 2000 2002

FinePitchBGAs

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A System-Level SolutionNot Just a High Density Device

2 System Memory

3 SystemTiming

1 SystemIntegration

4 System Interfaces

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The FPGA Solution

4th Generation FPGALogic+Memory+Routing

Multi-Standard Select I/O

Temperature Sensing

Delay-Locked Loop for Fast Clock and I/O

3.3 ns SynchronousDual-Port SRAM

500 Mbps SelectMAP Configuration

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Memory

w Three-level memory hierarchy:— distributed 4-input look-up-table RAMs

– 16-bit single- and dual-port RAM– 16-bit shift register in Virtex

— versatile dual-port BlockRAMs– 4k x 1 to 256 x 16 format, selectable per port

— 200 MHz interface to large external RAMs

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High Performance ClockNetworks

Delay Locked Loops Synchronize on-chip and board level clocks

DLL1 DLL2

DLL3 DLL4

DeskewClockson Chip

Manage up to 4System Clocks

DeskewClocks

on Board

CascadeDLLs

GenerateClocks - multiply - divide - shift

4 DLLs in eachVirtex Device

ConvertClockLevelsusing

SelectI/O

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Multi-Standard Select I/OGTL+

5V Tolerant

2.5V SSTL

1.8V

3.3V LVTTL

5V

MicroProcessorMicroProcessor SRAMSRAM

DSPDSP

Mixed SignalMixed Signal

Busses/Backplanes(3/5V PCI, ISA, GTL…)

Busses/Backplanes(3/5V PCI, ISA, GTL…)

FLASHFLASH

SDRAMSDRAMSDRAM

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Virtex Supports17 I/O Standards

SDR

AM

SSTL

GT

L+

LVTTL

LVCMOSCTT

SRA

M

HSTL

Chip to ChipLVTTL, LVCMOS

Chip to MemorySSTL2-I, SSTL2-II, SSTL3-I,SSTL3-II, HSTL-I, HSTL-III,HSTL-IV, CTT

Chip to BackplanePCI66, PCI33-5V, PCI333.3V, GTL, GTL+, AGP

Select I/OTM TechnologyAny standard on any pinMultiple standards at once

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Interconnect Hierarchy

w Segmented interconnect structure reducesload capacitance and power consumption

w Four high-drive low-skew clock nets— each can drive all flip-flops and registers— each can be driven by its own DLL

w 24 additional low-skew global nets

w Horizontal bi-directional longlines

w Segmented lines between logic blocks

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HardwareProgrammable

Programmable SystemExample

Inherently Programmable

SSTL3

1x C

LK

2x C

LK

LVTTL

LVCMOS

GT

L+

2x CLK

SDR

AM

Backplane Logic

Tra

nsla

tors

Custom Logic

Clock Mgmt

OldFPGA

Glue Logic

OldFPGA

Cache Memory

Processor

100MHz System Performance

1M Gates

SoftwareProgrammable

Inherently Programmable

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Design Methodology

w Million-Gate Designs

Communication, Coordination and Integration!Communication, Coordination and Integration!

w Variety of Design Flows

w Multiple HDLs In Use

w Global Design Teams

This Requires…This Requires…

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Designer1Module

DesignReuse

Designer2Module

Designer3Module

Reduces Compile Time & Increases Performance

Modular Designw Autonomy between team

members

w High Level Floorplanning

w Modular Place and Route

w Modular Time Specs— With industry’s best timingconstraint language

w Modular Incremental Compile— Extensive R&D investment

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Internet-Based Design

w WebFITTER,— an Internet-based tool to evaluate CPLD designs

w Internet Team Design— for team-based design over the Internet/Intranet

w Internet Reconfigurable Logic— modify, upgrade, test, and repair FPGA-based systems

by downloading new configurations via the Internet

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System on an FPGA

VHDL DesignEnvironment

Verilog DesignEnvironment CoreGen

Designer#2 DSPDesigner

#1New

Modules FIFO

133MhzSDRAM

GbitEthernet

66MhzPCI

IP Modules

LogiCore

AllianceCore

CPU

DesignReuse

160 MHz I/O Performance133 MHz Memory Performance

1 Million System Gates

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Reconfigurable Logic

Spectrum of Reconfiguration

Once-and-awhile

Once in a while

Field Upgrades

Application

Multi-PersonalityProducts

Tasks

ReconfigurableComputing

Continuous

Evolving Logic

Turn-on

Adaptive Products

w Cost-effective field upgrades

w New business model

w New types of products

w Mind-boggling opportunities in the long term

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Reconfigurable Instrument

w Multipurpose instrumentcan be reconfigured in milliseconds

w Single box for multiple applications

w Painless change,upgrade,or fix— longer lifetime, lower cost

w Encourages experimentation— faster progress

w Extends system lifetime— lower cost

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Challenges

w PC-board interconnects and reflections

w Power consumption

w Radiation effects

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Moore Meets Einstein

Speed Doubles Every 5 Years…...But the speed of light never changes

’65 ’70 ’75 ’80 ’85 ’90 ’95 ’00 ’05 ’10

Year

Clock Frequency in MHz

Trace Length in cm per 1/4 clock period

2048

1024

512

256

128

64

32

16

8

4

2

1

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Transmission Lines

w Some traces must be treated as transmission linesto minimize ringing— transmission line if round trip > transition time— lumped-capacitance if round trip < transition

time

w Signal delay on a PCB:— 140 to 180 ps per inch ( 50 to 70 ps/cm)

w Lumped-capacitance trace length:— 3 inches max for a 1-ns transition time (7.5 cm)— 6 inches max for a 2-ns transition time (15 cm)

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Evolution

2010(?)

1000

0.05

10

25

8-16

1995

100

0.5

3

100

4-8

1980

10

5

2

500

2-4

1965

1

-

1

2000

1-2

Max Clock Rate (MHz)

Min IC Geometries (µ)

# of IC Metal Layers

PC Board Trace Width (µ)

# of PC-Board Layers

w Every 5 years: System speed doubles, IC geometry shrinks 50%

w Every 7-8 years: PC-board minimum trace width shrinks 50%

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Power Consumption

w Power and heat are serious concerns

w All CMOS power consumption is dynamic— proportional to capacitance = device utilization— proportional to clock frequency— proportional to Vcc2

w Virtex conserves power— 2.5 V ( 1.8 V) supply, small geometries reduce capacitance— built-in temperature-sensing diode for thermal management

w Airflow and heatsink achieve <10 / W

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Radiation Effects

w Xilinx XQR-series devices use7-micron epitaxial layer to eliminatelatch-up at LET up to 120 MeVcm2/mg

w Single-Event Upset (SEU) rates have beenmeasured and reported

w FPGAs are being designed into aircraft and LowEarth Orbit Satellites (LEOS)

See www.xilinx.com/products/hirel_qml.htm#Radiation_Hardened

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Living with Single-Event Upsets

w Read back configuration in <100 ms— readback does not interfere with normal operation

w Error detection— serial bit-comparison against original configuration— abort and reconfigure whenever an error is detected

w Error correction— use triple redundancy to sustain operation— internal triple redundancy and fast partial reconfiguration

in Virtex devices

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Conclusion

w SRAM-based FPGAs are the fastest-growingIC product category

w Technology equals that used for the mostadvanced microprocessors and memories

w Offers fast time-to-market and low design risk

w Density, speed, and cost challenge ASICs

w Reconfigurability is a unique advantage

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This is the

Dawning of the Age

of Programmable Logic