the physical structure (nmos)users.encs.concordia.ca/~asim/coen 451/lectures/w_5... · concordia...

CONCORDIAVLSI DESIGN LAB

The Physical Structure (NMOS)

Field Oxide

Gate oxide

Field Oxide n+ n+

Al Al SiO2 SiO2

Polysilicon Gate

channel

P Substrate

(D) (S)

contact

Transistor Resistance

Two Components:

Drain/ Sources Resistance: RD(S) = Rsh x no. of squares+ contact resistance.

Channel Resistance:

Depends on the region of operation:

(D) (S) n+ n+

RS Rch RD

Linear

L----- V

T– 2

----------------------------------------------------= Saturation

L----- V

T– VDS–

---------------------------------------------------------------- '=

Transistor Geometry

Transistor Geometry- Detailed

NMOS Operation-Linear

K Cox= Process Transconductance uA/V2 for 0.35u, K’ (Kp)=196uA/ V2

-------= Gate oxide capacitance per unit area

ox = 3.9 x o = 3.45 x 10-11 F/m

tox Oxide thickness

for 0.35 , tox=100Ao

Quick calculation of Cox: Cox= 0.345/tox (Ao) pf/um2

= mobility of electrons 550 cm2/V-sec for 0.35 process

IDS N KN VGSN VTN– VDSN1

2---VDSN

= KN=K’. W/L

NMOS Operation-Linear

Effect of W/L Effect of temperature

Rds W/L

Variations in Width and Length

Wdrawn WD WD

1. Width Oxide encroachment Weff= Wdrawn-2WD

2. Length Lateral diffusion LD = 0.7Xj Leff= Ldrawn-2LD

Ldrawn

LD Leff LD

polysilicon

Large Transistors

Rchannel decrease with increase of W/L of the transistor

Semiconductor Resistors

R= p(l /A) = (p/t). (l /w) = Rsh. (l /w) For 0.5u process: N+ diffusion : 70 / □ M1: 0.06 P+ diffusion : 140 /□ M2: 0.06 Polysilicon : 12 /□ M3: 0.03 Polycide:2-3 /□ P-well: 2.5K N-well: 1K

current

n n q p p q +

------------------------------------------------=

Rsh values for 0.35u CMOS Process: Polysilicon 10 /□ Polycide 2 /□ Metal1 0.07 /□ Metal II 0.07 /□ Metal III 0.05 /□

Contact resistance: PolyI to MetalI 50

Via resistance: Metal I to Metal II 1.5 Via resistance: Metal II to metal III 1.

Modelling: Resistance

1. Resistance: Rint= Rsh [l/w] Rsh values for 0.35u CMOS Process: Polysilicon 10 / Polycide 2 / Metal1 0.07 / Metal II 0.07 / Metal III 0.05 / Contact resistance: PolyI to MetalI 50 Via resistance: Metal I to Metal II 1.5 Via resistance: Metal II to metal III 1.

Semiconductor Resistors

Diffusion n+

Field oxide

polysilicon

Polysilicon Resistor Diffusion Resistor

Delay Definitions

Semiconductor Capacitors

1. Poly Capacitor: a. Poly to substrate b. Poly1 to Poly2 2. Diffusion Capacitor

n+ (ND)

depletion region

substrate (NA)

bottomwall

capacitance

sidewall

capacitances

Dynamic Behavior of MOS Transistor

CGDCGS

CSB CDBCGB

Prentice Hall/Rabaey

SPICE Parameters for Parasitics

SPICE Transistors Parameters

Computing the Capacitances

V DD V DD

V in V out

M 4 C db 2

C db 1

C gd 12

V out 2

Fanout

Interconnect

V out V in

Simplified

Computing the Capacitances

CMOS Inverter: Steady State Response

V DD V DD

V out V out

V in = V DD V in = 0

V OH = V DD

V OL = 0

Switching Characteristics of Inverters

Vin = VDD

tpHL = f(Ron.CL)

= 0.69 RonCL

ln(0.5)

Transient Response

Step Response

Fall Delay Time: TPHL

IDN V in = 5

V in = 4

V in = 3

VDD=5V

VDD Vo VDD-VT

MN OFF Saturation Linear

(VDSAT)

Step Response- Fall time, tf

KPVDD 1 p+( )

---------------------------------------2–( ) 1 p+( )

1 p+( )---------------------------- 19 20p+( )ln+=

vo 1-n

td1 td2

VDD 1 n–( )---------------------------------------

2 n 0.1–( )

1 n–( )------------------------ 19 20n–( )ln+=

tf=~ k is a constant

tr=~ k is a constant

Step Response-tPHL

Vo VDD-VTN

td1 td2

vo 1-n

td1 td2

VDD/ 2

Assume normalized voltages vin= Vin/ VDD vo= Vo/ VDD n = VTN/ VDD p = VTP/ VDD tPHL=td1+td2

VDD 1 n–( )---------------------------------------

1 n–( )---------------- 3 4n–( )ln+=

VDD----------------------=

Step Response Rise Delay tPLH and Rise Time tr

VDD 1 p+( )---------------------------------------

1 p+( )----------------- 3 4p+( )ln+=

VDD---------------------=

KPVDD 1 p+( )

---------------------------------------2–( ) 1 p+( )

1 p+( )---------------------------- 19 20p+( )ln+=

VDD---------------------= (P= - 0.2)

Factors Influence Delay

Inverter Delay,td = (tPHL+tPLH)/2 The following factors influence the delay of the inverter: • Load Capacitance • Supply Voltage • Transistor Sizes • Junction Temperature • Input Transition Time

Delay as a function of VDD

2.00 4.001.00 5.003.00

VDD (V)

Delay as a function of Transistor Size

tPHL and tf decrease with the increase of W/L of the NMOS tPLH and tr decrease with the increase of W/L of the PMOS

Temperature Effect

Temperature ranges: commercial : 0 to700C industrial: -40 to 850C military: -55 to 1250C Calculation of the junction temperature tj= ta + ja X Pd Effect of temperature on mobility Delay and speed implications

Effect of Input Transition Times

r Vin Vo

The delay of the inverter increases with the increase of the input transition times r and f

tPHL = (tPHL) step + (r /6).(1-2p) tPLH = (tPLH) step + (f/6).(1+2n)

Define = (W/L)p/(W/L)n For Equal Fall and Rise Delay KN=KP

= n/ p For Minimum Delay dtD/d = 0

opt = Sqrt (n/ p)

Transistor Sizing

Power Dissipation in CMOS

Two Components contribute to the power dissipation:

» Static Power Dissipation

– Leakage current

– Sub-threshold current

» Dynamic Power Dissipation

– Short circuit power dissipation

– Charging and discharging power dissipation

Static Power Dissipation

Leakage Current: • P-N junction reverse biased current: io= is(e

qV/kT-1) • Typical value 0.1nA to 0.5nA @room temp. • Total Power dissipation:

Psl= i0.VDD

Sub-threshold Current • Relatively high in low threshold devices

Analysis of CMOS circuit power dissipation

The power dissipation in a CMOS logic gate can be

expressed as

P = Pstatic + Pdynamic

= (VDD · Ileakage) + (p · f · Edynamic)

Where p is the switching probability or activity factor

at the output node (i.e. the average number of output

switching events per clock cycle).

The dynamic energy consumed per output switching event is defined as

Edynamic = eventswitching

DDDD dtVi__1

Analysis of CMOS circuit power dissipation

SCDDMDDLdynamic EVCVCE 22 2

SCDDgdpgdndbndbpDDload EVCCCCVC 22 )](2[

The first term —— the energy dissipation due to the

Charging/discharging of the effective load capacitance CL.

The second term —— the energy dissipation due to the input-to-

output coupling capacitance. A rising input results in a VDD-

VDD transition of the voltage across CM and so doubles the

charge of CM.

CL = Cload + Cdbp +Cdbn

CM = Cgdn + Cgdp

• distributed,

• voltage-dependent, and

• nonlinear.

So their exact modeling is quite complex.

The MOSFET parasitic capacitances

Even ESC can be modeled, it is also difficult to calculate the

Edynamic.

On the other hand, if the short-circuit current iSC can be Modeled,

the power-supply current iDD may be modeled with the same

method.

So there is a possibility to directly model iDD instead of iSC.

Schematic of the Inverter

The short-circuit energy dissipation ESC is due to the rail-

to-rail current when both the PMOS and NMOS devices

are simultaneously on.

ESC = ESC_C + ESC_n

nDDcSC dtiVE0

0 DDVv

pDDdSC dtiVE

Analysis of short-circuit current

Charging and discharging currents

Discharging Inverter Charging Inverter

Factors that affect the short-circuit current

VI TDD

3)2(12

For a long-channel device, assuming that the inverter is

symmetrical (n = p = and VTn = -VTp = VT) and with zero load

capacitance, and input signal has equal rise and fall times (r = f

= ), the average short-circuit current [Veendrick, 1994] is

From the above equation, some fundamental factors that

affect short-circuit current are:

, VDD, VT, and T. )(L

Parameters affecting short cct current

For a short-channel device, and VT are no longer

constants, but affected by a large number of

parameters (i.e. circuit conditions, hspice

parameters and process parameters).

CL also affects short-circuit current.

Imean is a function of the following parameters (tox is process-

dependent):

CL, , T (or /T), VDD, Wn,p, Ln,p (or Wn,p/ Ln,p ), tox, …

The above argument is validated by the means of simulation in

the case of discharging inverter,

The effect of CL on Short CCt Current

Effect of tr on short cct Current

Effect of Wp on Short cct Current

Effect of timestep setting on simulation results

Tr (ps) Timestep (ps) MaxStep (ps) iMax (uA) iaverage_inT/2 (uA)

2 10 802.6 1.258

4 10 413.8 1.264

5 10 336.4 1.24

6 10 284.9 1.234

8 10 221 1.245

10 20 183 1.231

2 10 73.09 1.202

4 10 64.4 1.213

5 10 58.69 1.21

6 10 65.64 1.208

8 10 76.13 1.207

10 20 63.1 1.217

2 10 50.96 1.311

5 10 49.78 1.295

5 20 50.46 1.313

8 10 50.72 1.311

8 20 52.08 1.311

10 20 51.25 1.311

Thank you !

the physical structure (nmos)users.encs.concordia.ca/~asim/coen 451/lectures/w_5... · concordia...

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