track e magma redefining mixed so c chipex2011 - magma da

May 4, 2011 1May 4, 2011 1

REDEFINING MIXED SYSTEM-ON-CHIP DESIGN

Rajeev MadhavanCEO and Chairman, Magma Design Automation

May 4, 2011 2May 4, 2011 2

System-on-Chip Complexity Continues to Rise

• More functionality

• Much more Analog IP

• Large, complex digital blocks

• Shorter time-to-market

Motorola DroidX

Communication

Memory

Power

Software

Multimedia

GPS

Computing

NFC

Connectivity

Gyrometer

May 4, 2011 3May 4, 2011 3

SoC Example - 28nm 4G/3G Wireless Mobile Chip

• Chip Stats:– Instances: ~20 Million

• Top Level: 3.5 Million

– Blocks: 25-30• Block sizes: 100K – 1M

cells

– Clocks: >70– Frequency: 400MHz-

1.5GHz – Utilization: 70-80%– Timing Scenarios: 70-80

• 10 Modes• 7 Corners

Components

Application Processor

RF Interfaces

ADCDAC

Video CODEC

Display & Imaging Support

Modem

A/R Interfaces

GSMGPS

Audio CODEC

Graphics

Memory

Connectivity

SDIOUSBSIM

GPIO

Internal Functions

Clock GenerationPower Optimization

SecurityPLL

Analog Digital Mixed

May 4, 2011 4May 4, 2011 4

Challenges to Build this SoC

• Increasing Analog IP

• Increasing Digital Capacity & Complexity

• Final Signoff Closure

May 4, 2011 5May 4, 2011 5

Complexity Is Ever Increasing For Analog IP

• Complexity of analog IP has increased multiple fold• Current design flows are manual and very iterative.

Not scalable for increasing complexity of analog IP designed using advance process nodes

• Productivity has to be improved for next generation analog IP

May 4, 2011 6May 4, 2011 6

Analog IP Design Flows Have Not Evolved

• Entire design flow must be manually repeated to accommodate any change in: – Design

Specifications & Constraints

– Process node– Target Fab

Traditional Iterative Analog Design

Each new derivative requires nearly complete redesign

Schematic Capture

Simulation

Manual Layout

DRC/LVSExtraction

May 4, 2011 7May 4, 2011 7

New Model-Based Analog Design

Circuit Models Customized Analog IP

Optimization&

Placement/Routing

Target Specs

Process Models (PDK)

OpampsVoltage Reg

Charge Pump

SerDes

Layout

Optimization Goals

May 4, 2011 8May 4, 2011 8

Analog Optimization – Multiple Specs in a Week Spec - TTN / FFC / SSC / FFH / SSH Spec 1 Spec 2 Spec 3 Spec 4

Reference frequency range 16-200MHz 6-150MHz 27MHz 25-250MHz

VCO frequency range 1-2GHz 0.4-1.2GHz 0.81-1.62GHz 0.125-1.25GHz

PLL area 310m x 310m 295m x 295m 538m x 538m 628m x 628m

Power 5.9mW 2.2mW 16.5mW 10mW

Period jitter (Tpj @ Fvco,max) 1 1.7ps 2.5ps 0.5ps 0.95ps

Tpj (5% Vdd step @ Fvco,max) 16ps 17ps 15ps 19ps

Acc. jitter (Taj @ Fvco,max) 1 6.4ps 6.8ps 4.8ps 2.9ps

Taj (5% Vdd step @ Fvco,max) 89ps 126ps 191ps 91ps

Static phase error 1 53ps 82ps 68ps 87ps

Acquisition time 5.6us 19us 3.2us 30us

PLL bandwidth (typ) 1.4MHz 0.5MHz 1.9MHz 0.83MHz

Main loop filter capacitor 258pF 282pF 600pF 1200pF

DC VCO power-supply rejection -35dB -34dB -42dB -36dB

PLL’s generated for many specs simultaneously (Frequency ranges, Jitter, Bandwidth, Area, Power etc.)

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Analog Optimization – Power vs Area

• Analog optimization provides quick tradeoffs of power and area for design exploration

• Example: Regulator circuit– Analog optimization characterized on 5 corners– Tradeoff 40% power reduction vs 50% area reduction

Performance Hand Design Optimization for Power Optimization for AreaArea (um2) 20000 20000 10000 (-50%)Max Current (mA) 13.6 8.2 (-40%) 15.1 (+11%)Min DC Gain (dB) 35 40 345Min PM (degree) 84 86 77Min BW (Hz) 1.9M 2.5M 5.7MMax PSRR (dB) -11 -13 -5

May 4, 2011 10May 4, 2011 10

Challenges to Build this SoC

• Increasing Analog IP

• Increasing Digital Capacity & Complexity

• Final Signoff Closure

May 4, 2011 11May 4, 2011 11

Digital Designs: Increasing CapacityDramatic throughput needed

1999 2007 2009 2010 2012 2014100

1000

10000

100000

Flat

Blo

ck C

apac

ity(0

00s

of In

stan

ces)

250K

500K

3M

Capacity-DrivenProductivity Gap

10M

Achievable Flat Block Capacity

Needed Flat Block Capacity

1M

May 4, 2011 12May 4, 2011 12

Limitations in Tool Capacity Create Risk

• Limitations force design teams to artificially break up design– 5 blocks, 10 blocks, 20 blocks, 50 blocks or more?

• Partitioning increases complexity – more iterations!!!– Requires budgeting, clocks and interface timing closure

• Introduces schedule risks, requires more engineering resources

1M

500K 500K

1M

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Multi-Threading: Good, but not Good Enough

Typical “sweet spot” for EDA multi-threading

Number of cores/threads

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Current Digital Design Methodology

80M Cells

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4-5M

Place & Route

Place & Route

Place & Route

Place & Route

Place & RouteDistributed

Implementation(Master Process)

1 – ImplementationEngineer

New Distributed Digital Design

• Multi-million cells/day throughput• Design capacity per engineer up to 10M cells, flat!

May 4, 2011 16May 4, 2011 16

Benefit of Distributed Design

• Greatly increases designer productivity

• Leverages existing hardware and P&R licenses

• Implements bigger designs faster using existing engineering resources

May 4, 2011 17May 4, 2011 17

Design Example

• ~4M cells hierarchical design• Redefined as flat and distributed across 8 servers

Stage WNS (ps)

TAT (hrs)

Peak Mem (Gb)

Original Goal -200 168.0 <70Final Results -200 61.7 51

May 4, 2011 18May 4, 2011 18

Challenges to Build this SoC

• Increasing Analog IP

• Increasing Digital Capacity & Complexity

• Final Signoff Closure

May 4, 2011 19May 4, 2011 19

Final Signoff Closure Too LongP&R Timing Closure ECOs

Signoff

Mask

Prep

Metal Fill Insertion

Extraction

Timing

LogicalECO

ECOP&R

DRC Checking

8-20Iterations

• 4-17 hoursExtraction STAR RC

• 3-7 hoursSTA PT & PTSI

• 1-7 hoursMetal Fill Calibre

• 5-15 hoursFile Transfers:

• 5- 80 hoursLogical ECO :

• 3-24 hoursECO P&R:

3-5 days per iteration!Final Netlist Closure: 100 days!

~50 days ~50 days

May 4, 2011 20May 4, 2011 20

SignoffVerification

New ZERO ECO Approach

• Best-in-class runtime for each tool Improves TAT of each iteration

• Integrated flow Fewer iterations

• Result: Faster Total Throughput

10 days

Metal Fill Insertion

Extraction

Timing

LogicalECO

ECOP&R

DRC Checking

1-2 days per iteration

20 days 5 days

5 days

P&RTiming

Closure ECOs

SignOff

Mask

Prep

Final Netlist Closure: 40 days!

Place & Route

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Summary

• Every SoC is Mixed Signal• Every EDA tool must focus on Silicon first• Mixed Signal SoC redefined EDA must comprehend

& solve new mixed signal challenges