triplet finder jinyuan wu dec. 2003 triplets triplet finding (1) filling bit arrays note: flipped...
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Triplet Finder
Jinyuan Wu
Dec. 2003
Triplets
Triplet Finding (1) Filling Bit Arrays
Note: Flipped Bit OrderPhysical Planes
Bit Arrays
For any hit… Fill a corresponding logic cell.
Triplet Finding (2) Looping, Shifting and Matching
For any center plane hit…
Logically shift the
bit array.
Bit-wise AND in
this range.
Triplet is found.
Physical Planes
Bit Arrays
Triplet Finding (2) Looping, Shifting and Matching
Triplet is found.
Fake triplet will be cut out in the
later stages.
Physical Planes
Bit Arrays
Triplet Finding (2) Looping, Shifting and Matching
Physical Planes
Bit Arrays
Triplet Finding (2) Looping, Shifting and Matching
Physical Planes
Bit Arrays
Triplet Finding (2) Looping, Shifting and Matching
Physical Planes
Bit Arrays
Bit Array/shifterXILINX Implementation
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
• Each Bit Array/Shifter has 64 bins.
• Each bin is a 16-bit RAM (look-up table).
• The RAM operates like a D Flip-flop.
• Each xc2v1000 FPGA has 10,240 such RAM’s.
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
Bit Array/shifterFilling the Hits
• Each hit is written into 8 to 16 different RAM’s with different addresses.
• One clock cycle (not 8 to 16) is used to fill a hit.
Bit Array/shifterShift Reading
• With given addresses of the RAM’s, hit patterns appear at the outputs of the arrays.
• Changing addresses shifts the hit patterns.
• One array shifts in unit of 1 bin, the other in unit of 8 bins.
• The relative shift of the two patterns covers 128 bins.
• One clock cycle is used for a reading, regardless the distance of the relative shifting.
Bit Array/shifterComments
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
• Writing/reading operations need only single clock cycle.
• Storage and shifter are combined — big resource saving.
• Maximum 16 clock cycles are needed for resetting.
• Non-xilinx implementation: Additional 64x8=512 LE’s may be needed. But resetting is a single clock one.
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
D QWEA(3:0)
Multiple Hits, TripletsKeep Them All
• Each bin may be filled with more than one hits.
• Hits data are kept in hash sorters – allowing multiple hits per bin.
• There are may be more than one matches in each bit-wise AND operation.
• They are all sent out, one-by-one, to the later stages for fine cut and arbitration processes.
DA
BitLogic
KA
XB
EN
C KC
Pop
Halt
Bit64A
Q
KS
WR
EN
SR
Bit64C
Q
KS
WR
EN
SR
Hash2blk
DI QQ
K
Push
Pop
WT
RePop
SR
RDY
MD
Hash2blk
DI QQ
K
Push
Pop
WT
RePop
SR
RDY
MD
Cutand
Arbitration
QT
DA
EN
DB
RDYDC
ShiftReg.6 steps
D Q4
EN
FIFOInterface
HitFeeder A
QAD
EN
KA
Push
FIFOInterface
HitFeeder C
QCD
EN
KC
Push
A
FIFOInterface
HitFeeder B
SAD
EN
QB
Chk
SC
XB
172 LUT FF
92 LUT FF
192 LUT111 FF
77 LUT66 FF
77 LUT66 FF
A3
A2
A1
A0
S0,S1
K(8:0)
DI(27:0) DOB(27:0)
IdN(7:0)
CB8RECE
SR
Q
CB10ECE
Q
A0
A1
S0
COMP
A
EQ
B
FDD Q
FDD Q
EN
FDD Q
FDD Q
EN
RAM512x18D
A
O
WE
EN
D O
FDD Q
RAM256x36D
A
O
WE
EN
D O
FDD Q
EN
RDY
MD
PUSH
POP
WT
REPOP
DUMPD
SRCLK
POPQ
PUSHQ
DIQ(27:0)
IdP(7:0) IdQ(7:0)
IdK(7:0) IdKQ(7:0)
EVeqEV(9:0)
EV(8:0)
Vertex II Implementation
A3
A2
A1
A0
S0,S1
K(7:0)
DI(28:0) DOB(28:0)
IdN(6:0)
CB7RECE
SR
Q
CB9ECE
Q
A0
A1
S0
COMP
A
EQ
B
FDD Q
FDD Q
EN
FDD Q
FDD Q
EN
RAM256x16D
A
O
WE
EN
D O
FDD Q
RAM128x36D
A
O
WE
EN
D O
FDD Q
EN
RDY
MD
PUSH
POP
WT
REPOP
DUMPD
SRCLK
POPQ
PUSHQ
DIQ(28:0)
IdP(6:0) IdQ(6:0)
IdK(6:0) IdKQ(6:0)
EVeqEV(8:0)
EV(7:0)
Cyclone Implementation
The End
Thanks
RAMD
A
O
WE
EN
D
CC8RLE
Q
L
CE
SR
A0
A1
A2
A3
S
CB8SE
S1
CE
SS
QFD
D Q
CE
RAMD
A
O
WE
EN
D O
NBin
DIDOB
IdNextFD
D Q
CE
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