uic thesis corbetta
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A Flexible Tile-Based Communication Infrastructure for
Partial Reconfigurable Architectures
BY
Simone Corbetta
simone.corbetta@dresd.org
Thesis committee:
Shantanu Dutt (chair), Donatella Sciuto, Ashfaq Ahmad Khokhar
UIC Thesis Defense: May, 8th 2008
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AimsAims
[A1] Define a communication infrastructure for partially reconfigurable architectures
[A2] Design the communication protocol
[A3] Design network nodes
[A4] Implementation
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Rationale and InnovationRationale and Innovation
Problem statementDynamic capabilities of modern devices demands for flexibility, reliability and adaptabilityAdaptability to dynamic context changes
Innovative contributionsNetwork-based communication infrastructure tailored for partial reconfigurable architectures
Device-independentResource-aware designReliable communication Adaptable communication schema
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OutlineOutline
Introduction
Related works
Proposed approach & implementationExperimental results
Conclusions and future works
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What’s nextWhat’s next
IntroductionA bird’s eye-view on communication infrastructures
Related works
Proposed approach & implementationExperimental results
Conclusions and future works
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Communication-centric designCommunication-centric design
Increasing complexity in modern Systems-on-ChipsIncreasing applications scenariosCommunication requirements increaseCommunication-centric design [1,2]
Static versus dynamic environmentExecuting applications are not known a priori Communication requirements cannot be specified prior to system execution
“Classical” widely-used communication approaches lack of flexibility and scalability
Need to define a flexible, adaptable solution
[1] “Communication Centric SoC Design for Nanoscale Domain”. Ogras, U. Y.; Jingcao, Hu; Marculescu, R. 16th IEEE International Conference on Application-Specific Systems, Architecture and Processors. July 2005. pp.73-78.
[2] “On-Chip Networks: a Scalable, Communication-Centric Embedded System Design Paradigm”. Henkel, J.; Wolf, W.; Chakradhar, S. Proceedings of the 17th International Conference on VLSI Design, 2004. pp.845.851.
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Communication infrastructure and dynamic Communication infrastructure and dynamic featuresfeatures
Dynamic reconfiguration can be used to effectively realize communication infrastructures that are
FlexibleReliableAdaptable (at run-time) to communication requirements
Dynamic reconfiguration as a specific feature of the communication infrastructure layer design
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Point-to-point linksPoint-to-point links
Directly connect communicating modules
(a) ad-hoc connection (b) regular topology (complete graph)
Advantages Drawbacks
Simplicity; ensures high performance, and low latency; no overhead
Scalability is affected, due to high resource requirements; reusability is low, interfaces are application-dependent
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Bus-based systemsBus-based systems
Single, centralized and shared communication architectureAn arbiter grants access to the shared resource
Advantages Drawbacks
Simplicity; reusability, commercial standards
Bottleneck; level of contention increases, concurrent accesses are serialized; single point-of-failure
...
Arbiter
(a) single bus
... ...
Bridge
(b) multiple buses
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Crossbar switchCrossbar switch
MxN matrix of programmable components
Advantages Drawbacks
True parallellism, physically different concurrent communication links can be established
Resource requirements, in terms of programmable components
Line 1
Line 2
Programmable interconnect point
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Network-on-ChipNetwork-on-Chip
Borrow main ideas from data-network (LANs, WANs)Based on distributed communication nodes (switches) [3,4]
[3] “Networks-on-Chip: a New SoC Paradigm”. De Micheli, G.; Benini, L. Computer. 2002, Volume 35. pp.70-78.
[4] “Networks-on-Chip: a New Paradigm for System-on-Chip Design”. Nurmi, J. Proceedings of the International Symposium on System-on-Chip, Nov. 2005. pp.2-6.
Advantages Drawbacks
Flexibility; scalability; reusability; reliability, no single point-of-failure
Computational overhead; high resource requirements
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What’s nextWhat’s next
IntroductionFPGAs and dynamic reconfiguration
Brief overview of devices and dynamic features
Related works
Proposed approach & implementationExperimental results
Conclusions and future works
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Field Programmable Gate Field Programmable Gate ArraysArrays
Programmable logic devices(Re)programmable logic blocks and interconnects
Configuration is stored within the configuration memory architecture
Image taken from “Bebop to the Boolean Boogie: an Unconventional Guide to Electronics Fundamentals, Components and Processes” by Clive Maxfield [Everyday Practical Electronics]
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Reconfiguration and Reconfiguration and ReconfigurabilityReconfigurability
Reconfiguration is the process of alteration of the system configuration/behaviorReconfigurability is the ability to support reconfiguration
Which is the granularity of the reconfiguration process
Total versus partial reconfiguration
Who is the responsible of the reconfiguration taskInternal versus external reconfiguration
When the reconfiguration is performedDynamic versus static reconfiguration
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What’s nextWhat’s next
IntroductionFPGAs and dynamic reconfiguration
Related worksXPipesDyNoCCoNoChi
Proposed approach & implementationExperimental resultsConclusions and future works
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XPipes XPipes (1/2)
Designed for multi-processors systems [5]Ad-hoc network topology defined at synthesis-time
XPipesCompiler
Based on a layered approach: Smart Stack protocol
[5] Bertozzi, D.; Benini, L. “XPipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip”. Circuits and Systems Magazine, IEEE, 2004, 4, pp.18-31.
DATA-LINK LAYER
NETWORK LAYER
TRANSPORT LAYER
physical link
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XPipes XPipes (2/2)
Advantages Layered stacked protocol allows for independent optimization of different aspects
DrawbacksTopology is fixed at synthesis-time
No flexibility
Routing path is defined once for all at synthesis-time
No reliability
Resource requirements(See experimental results)
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DyNoC DyNoC (1/2)
Static NoC for heterogeneous systems [6]Static 2D-mesh interconnection topologyStatic routing mechanism (modified XY-Algorithm)
[6] Bobda, C.; Ahmadinia, A.; Majer, M.; Teich, J.; Fekete, S.; Van der Veen, J. “DyNoC: A Dynamic Infrastructure for Communicationin Dynamically Reconfigurable Devices”. International Conference on Field Programmable Logic and Applications, August 2005, pp.151-158.
DyNoC Rule
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DyNoC DyNoC (2/2)
Advantages 2D-mesh topology guarantess high connectivity
DyNoC Rule
DrawbacksStatic topology guarantees no flexibilityHigh overhead
One network node for each “slot” in the architecture
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CoNoChi CoNoChi (1/2)
Reconfigurable packet-switched communication architecture [7]
[7] Pionteck, T.; Koch, R.; Albrecth, C. “Applying Partial Reconfiguration to Networks-on-Chips”. International Conference on Field Programmable Logic and Applications, August 2006, pp.1-6.
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CoNoChi CoNoChi (2/2)
Advantages Network nodes can be added at run-timeFlexibilty
DrawbacksNo multiple communication sessions are supportedNo clear distinction between communication and computational layer
Hard to manage system complexityResource requirements
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Qualitative ComparisonQualitative Comparison
XPipes DyNoC CoNoChi
ConnectivityRelies upon
synthesis-time choices
Static meshRelies on run-time
choices
Flexibility No flexibility No flexibilityFlexibility thanks
to dynamic reconfiguration
Dynamic Reconfigurati
onNot supported Not supported Supported
Computation and
communication
No clear distinction
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What’s nextWhat’s next
IntroductionFPGAs and dynamic reconfiguration
Related works
Proposed approach & implementationMain features and implementation
Experimental results
Conclusions and future works
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A light-weight approachA light-weight approach
“Light-weight” w.r.t.Communication protocol, to reduce computational overheadResource requirements, to keep reconfiguration complexity lowNetwork nodes design, to reduce overhead and latencyRouting mechanism, to reduce latency
To master system complexity a layered approach has been used
COMPUTATIONAL LAYER
COMMUNICATIONLAYER
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OverviewOverview
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Packet-switched communicationPacket-switched communication
Packet-switching instead of circuit-switching [8]
General packet structure
[8] Dally, W.; Towles, B. “Route packets, not wires: on-chip interconnection networks”. In proceedings of the Design and Automation Conference in Europe, 2001, pp.684-689.
HeaderContains preliminary information on the current communication session, useful for the recipient
Data Contains data of the current communication request
Control Contains communication-related information (route update, communication tail, replies…)
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Session-oriented communicationSession-oriented communication
Communication based on the concept of sessionA precise sequence of packets
Communication based on the minimal information required
HeaderDataTile
For each Master-Slave couple multiple concurrent sessions are supported
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A layered protocolA layered protocol
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Routing mechanisms Routing mechanisms (1/2)
Who chooses the routing path?
INITIATOR-BASED: the initiator chooses the entire path to reach the destination end-pointDESTINATION-BASED: information is kept within the routing tables, local decisions
initiator-based destination-based
Initiator-based Destination-based
PROSSwitch design has low complexity; switch-related overhead is low
Flexibilty and transparency on the communication details
CONS
Update of the information is complex; overhead increases
Switch-related overhead is greater, due to routing table read process
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Routing mechanisms Routing mechanisms (2/2)
An hybrid approach takes advantage from both mechanisms
BROKENESEE SEE/
E///
EE//
////
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What’s nextWhat’s next
IntroductionFPGAs and dynamic reconfigurationRelated works
Proposed approach & implementationImplementation
Experimental results
Conclusions and future works
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Target architectureTarget architecture
Target architectureStatic sideReconfigurable side
Static Reconfigurable
FPGA Bus-macro
TILE
columns
row
s
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Switch designSwitch design
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Master NI DesignMaster NI Design
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Slave NI DesignSlave NI Design
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What’s nextWhat’s next
IntroductionFPGAs and dynamic reconfiguration
Related works
Proposed approach & implementationExperimental results
Case studies
Conclusions and future works
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Experimental ResultsExperimental Results
Purpose is to demonstrate the validity of the proposed approach
Resource requirementsSwitch designMaster and Slave NI
Virtex-II Pro Case Study Comparison with XPipes
Virtex-4 Case Study
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Switch Resource RequirementsSwitch Resource RequirementsSwitch design is effectively light-weight
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Switch PerformanceSwitch Performance
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Master NI Resource RequirementsMaster NI Resource Requirements
Depends on number of concurrent sessions, packet size
Linear relationXC3S200
XC2VP7
XC4VFX12
27-bits packet
32-bits packet
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Slave NI Resource RequirementsSlave NI Resource Requirements
Depends expecially on concurrent sessions allowed
Linear27-bits packets case
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Virtex-II Pro Case Study Virtex-II Pro Case Study (1/3)(1/3)
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Virtex-II Pro Case Study Virtex-II Pro Case Study (2/3)(2/3)
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Virtex-II Pro Case Study Virtex-II Pro Case Study (3/3)(3/3)
XPipes versus proposed solution
Resource requirements
Latency
618/1215 = 50.8%
846/1520 = 55.5%
Half clock cycles required
IMPROVEMENT !
• Resource-aware design
• High performance
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Virtex-4 Case Study Virtex-4 Case Study (1/2)(1/2)
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Virtex-4 Case Study Virtex-4 Case Study (2/2)(2/2)
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_
___
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What’s nextWhat’s next
IntroductionFPGAs and dynamic reconfiguration
Related works
Proposed approach & implementationExperimental results
Conclusions and future works
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Concluding Remarks Concluding Remarks (1/2)(1/2)
A suitable communication infrastructure has been designed and implemented
Flexibility and
adaptability
Dynamic switch insertion; dynamic switch deletion; dynamic topology; dynamic routing mechanism;
support of dynamic reconfiguration
Reliability Dynamic routing; dynamic topology
Resource-aware design
Switch-design; communication protocol complexity
Device independen
t designTile-based implementation and tile dimensioning
Layered approach
Communication protocol and Network Interface designs
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Concluding Remarks Concluding Remarks (2/2)(2/2)
Work under development for ACM TRETS Transaction (Transactions on Reconfigurable Technology and Systems)
Future worksDefine and realize a tool to automatically generate application-specific networkImplement the Network and Reconfiguration MonitorAnalysis and study of the power characterization of the proposed approach
“A Light-Weight Network-on-Chip Architecture for Dynamically Reconfigurable Systems”. Corbetta, S.; Rana, V.; Santambrogio. M. D. Proceedings of the 8th edition of the International Symposium on Systems, Architectures, Modeling and Simulation (IEEE Conference Session), July 2008.
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General InformationGeneral Information
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QuestionsQuestions
Thanks for your attention.Any questions?
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