unit 7 multi-level gate circuits / nand and nor gates ku-yaw chang canseco@mail.dyu.edu.tw assistant...

Unit 7Unit 7Multi-Level Gate Circuits / Multi-Level Gate Circuits /

NAND and NOR GatesNAND and NOR Gates

Ku-Yaw ChangKu-Yaw Changcanseco@mail.dyu.edu.twcanseco@mail.dyu.edu.tw

Assistant Professor, Department of Assistant Professor, Department of Computer Science and Information EngineeringComputer Science and Information Engineering

Da-Yeh UniversityDa-Yeh University

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ContentsContents

7.1 Multi-Level Gate Circuits7.1 Multi-Level Gate Circuits7.27.2 NAND and NOR GatesNAND and NOR Gates7.37.3 Design of Two-Level Circuits Using NANDDesign of Two-Level Circuits Using NAND and NOR Gates and NOR Gates

7.47.4 Design of Multi-Level NAND and NOR Design of Multi-Level NAND and NOR GateGate Circuits Circuits7.57.5 Circuit Conversion Using Alternative GateCircuit Conversion Using Alternative Gate Symbols Symbols7.67.6 Design of Two-Level, Multiple-OutputDesign of Two-Level, Multiple-Output Circuits Circuits7.77.7 Multiple-Output NAND and NOR CircuitsMultiple-Output NAND and NOR Circuits

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7.4 Design of Multi-Level NAND-7.4 Design of Multi-Level NAND- and NOR-Gates Circuits and NOR-Gates Circuits

Multi-Level NAND-gate circuitsMulti-Level NAND-gate circuits Simplify the switching function to be realized.Simplify the switching function to be realized. Design a multi-level circuit of AND and OR gates. The Design a multi-level circuit of AND and OR gates. The

output gate must be OR. AND-gate outputs cannot be output gate must be OR. AND-gate outputs cannot be used as AND-gate inputs; OR-gate outputs cannot be used as AND-gate inputs; OR-gate outputs cannot be used as OR-gate inputs.used as OR-gate inputs.

Number the levels starting with the output gate as Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving level 1. Replace all gates with NAND gates, leaving all interconnections between unchanged. Leave the all interconnections between unchanged. Leave the inputs to levels 2, 4, 6, …unchanged. Invert any inputs to levels 2, 4, 6, …unchanged. Invert any literals which appear as inputs to levels 1, 3, 5,…literals which appear as inputs to levels 1, 3, 5,…

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Multi-Level NAND-gate circuitsMulti-Level NAND-gate circuits

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ContentsContents

7.1 Multi-Level Gate Circuits7.1 Multi-Level Gate Circuits7.27.2 NAND and NOR GatesNAND and NOR Gates7.37.3 Design of Two-Level Circuits Using NANDDesign of Two-Level Circuits Using NAND and NOR Gates and NOR Gates7.47.4 Design of Multi-Level NAND and NOR GateDesign of Multi-Level NAND and NOR Gate Circuits Circuits

7.57.5 Circuit Conversion Using Alternative GateCircuit Conversion Using Alternative Gate Symbols Symbols7.67.6 Design of Two-Level, Multiple-OutputDesign of Two-Level, Multiple-Output Circuits Circuits7.77.7 Multiple-Output NAND and NOR CircuitsMultiple-Output NAND and NOR Circuits

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7.57.5 Circuit Conversion UsingCircuit Conversion Using Alternative Gate Symbols Alternative Gate Symbols

An inverter can be represented byAn inverter can be represented by

Inversion bubbleInversion bubbleAt the input At the input

At the outputAt the output

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Alternative Gate SymbolsAlternative Gate Symbols

AND, OR, NAND, and NOR gatesAND, OR, NAND, and NOR gates Based on DeMorgan’s lawBased on DeMorgan’s law

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Alternative Gate SymbolsAlternative Gate Symbols

Why alternative symbols?Why alternative symbols? Facilitate the analysis and design of NAND and NOR Facilitate the analysis and design of NAND and NOR

gate circuitsgate circuits

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NAND Gate Circuit ConversionNAND Gate Circuit Conversion

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Conversion to NOR GatesConversion to NOR Gates

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Conversion of AND-OR Circuit to Conversion of AND-OR Circuit to NAND GatesNAND Gates

Convert all AND gates to NAND gatesConvert all AND gates to NAND gates Adding an inversion bubble at the outputAdding an inversion bubble at the output

Convert all OR gates to NAND gatesConvert all OR gates to NAND gates Adding inversion bubbles at the inputsAdding inversion bubbles at the inputs

An inverted output drives an inverted inputAn inverted output drives an inverted input No further actionNo further action

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Conversion of AND-OR Circuit to Conversion of AND-OR Circuit to NAND GatesNAND Gates

A non-inverted gate output drives an A non-inverted gate output drives an inverted gate input or vice versainverted gate input or vice versa Insert an inverterInsert an inverter

A variable drives an inverted inputA variable drives an inverted input Complement the variableComplement the variable

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Conversion of AND-OR Circuit to Conversion of AND-OR Circuit to NAND GatesNAND Gates

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ContentsContents

7.1 Multi-Level Gate Circuits7.1 Multi-Level Gate Circuits7.27.2 NAND and NOR GatesNAND and NOR Gates7.37.3 Design of Two-Level Circuits Using NANDDesign of Two-Level Circuits Using NAND and NOR Gates and NOR Gates7.47.4 Design of Multi-Level NAND and NOR GateDesign of Multi-Level NAND and NOR Gate Circuits Circuits7.57.5 Circuit Conversion Using Alternative Gate Circuit Conversion Using Alternative Gate Symbols Symbols

7.67.6 Design of Two-Level, Multiple-OutputDesign of Two-Level, Multiple-Output Circuits Circuits7.77.7 Multiple-Output NAND and NOR CircuitsMultiple-Output NAND and NOR Circuits

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7.6 Design of Two-Level,7.6 Design of Two-Level, Multiple-Output Circuits Multiple-Output Circuits

The realization of several functions of the The realization of several functions of the same variablessame variables A more economical realizationA more economical realization

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Multi-Output FunctionMulti-Output Function

Given FunctionsGiven Functions

FF11(A, B, C, D) = (A, B, C, D) = ∑ m(11, 12, 13, 14, 15)∑ m(11, 12, 13, 14, 15)

FF22(A, B, C, D) = (A, B, C, D) = ∑ m(3, 7, 11, 12, 13, 15)∑ m(3, 7, 11, 12, 13, 15)

FF33(A, B, C, D) = (A, B, C, D) = ∑ m(3, 7, 12, 13, 14, 15)∑ m(3, 7, 12, 13, 14, 15)

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Separate RealizationsSeparate Realizations

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Multiple-Output SimplificationMultiple-Output Simplification

FF1 1 = AB + ACD= AB + ACD

FF2 2 = ABC’ + CD= ABC’ + CD

FF33 = A’CD + AB = A’CD + AB

AB: FAB: F11 and F and F33

CD (FCD (F22) can be replaced by A’CD + ACD) can be replaced by A’CD + ACD

FF22 = ABC’ + = ABC’ + A’CD + ACDA’CD + ACD

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Multiple-Output RealizationMultiple-Output Realization

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ComparisonComparison

GatesGates Gate Gate InputsInputs LevelLevel

Separate Separate RealizationRealization 99 2121 22

Multiple-OutputMultiple-Output

RealizationRealization77 1818 22

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Multiple-Output SimplificationMultiple-Output Simplification

If several solutions are availableIf several solutions are available Try to minimize the total number of gates Try to minimize the total number of gates

requiredrequired Choose the one with minimum gates inputsChoose the one with minimum gates inputs

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ContentsContents

7.1 Multi-Level Gate Circuits7.1 Multi-Level Gate Circuits7.27.2 NAND and NOR GatesNAND and NOR Gates7.37.3 Design of Two-Level Circuits Using NANDDesign of Two-Level Circuits Using NAND and NOR Gates and NOR Gates7.47.4 Design of Multi-Level NAND and NOR GateDesign of Multi-Level NAND and NOR Gate Circuits Circuits7.57.5 Circuit Conversion Using Alternative GateCircuit Conversion Using Alternative Gate Symbols Symbols7.67.6 Design of Two-Level, Multiple-Output Design of Two-Level, Multiple-Output Circuits Circuits

7.77.7 Multiple-Output NAND and NOR CircuitsMultiple-Output NAND and NOR Circuits

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7.77.7 Multiple-Output NAND and Multiple-Output NAND and NOR Circuits NOR Circuits

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Homework #1Homework #1

1.1. 7.17.1

2.2. 7.37.3

3.3. 7.47.4

4.4. 7.87.8

5.5. 7.107.10

6.6. 7.177.17

7.7. 7.197.19

8.8. 7.207.20

9.9. 7.257.25

10.10. 7.267.26

Paper Submission, due on March 22, 2004.Late submission will not be accepted.